coreboot-gerrit August 2019

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Change in coreboot[master]: mediatek/mt8183: Set DRAM vlotage for each DRAM frequency
by Yu-Ping Wu (Code Review) 29 Aug '19

29 Aug '19

Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35017 ) Change subject: mediatek/mt8183: Set DRAM vlotage for each DRAM frequency ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/35017/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/35017/2//COMMIT_MSG@7 PS2, Line 7: vlotage voltage -- To view, visit https://review.coreboot.org/c/coreboot/+/35017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9539473ff708f9d0d39eb17bd3fdcb916265d33e Gerrit-Change-Number: 35017 Gerrit-PatchSet: 3 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-Reviewer: Huayang Duan <huayang.duan(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-Reviewer: huayang duan <huayangduan(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 29 Aug 2019 08:02:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86: Fix clearing .bss section
by Paul Menzel (Code Review) 29 Aug '19

29 Aug '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35139 ) Change subject: arch/x86: Fix clearing .bss section ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/35139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie54fcfcb7e5a2a5a88d988476aa69b2a163e919c Gerrit-Change-Number: 35139 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Aug 2019 07:27:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86: Fix clearing .bss section
by Paul Menzel (Code Review) 29 Aug '19

29 Aug '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35139 ) Change subject: arch/x86: Fix clearing .bss section ...................................................................... Patch Set 1: > Patch Set 1: > > > Patch Set 1: > > > > I wonder will break by this being correct? > > I think the error was harmless; CAR after _car_global_end is either unallocated or (yet) unused stack space. It’d be great, if you added that to the commit message. -- To view, visit https://review.coreboot.org/c/coreboot/+/35139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie54fcfcb7e5a2a5a88d988476aa69b2a163e919c Gerrit-Change-Number: 35139 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 29 Aug 2019 07:27:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/crossgcc/patches: facilitate successful build of ipxe
by Name of user not set (Code Review) 29 Aug '19

29 Aug '19

Name of user not set #1002476 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35144 ) Change subject: util/crossgcc/patches: facilitate successful build of ipxe ...................................................................... util/crossgcc/patches: facilitate successful build of ipxe New changes in the latest binutils 2.32 leads to assembler errors causes ipxe build failure. IPXE uses the divide test which requires /dev/null as input as well as the output file name. This patch facilitates the /dev/null as an exception to the current changes in binutils package while building crossgcc for coreboot leads to successful build of ipxe and further tests to pass based on /dev/null and applies automatically during the crossgcc rebuild. Also, this can be reverted once binutils/ipxe provides update release in this respect. Change-Id: I111cfae98286baef38bb95b9f30f0382b047ea03 Signed-off-by: Himanshu Sahdev <himanshusah(a)hcl.com> --- M 3rdparty/blobs M 3rdparty/fsp M 3rdparty/libgfxinit M 3rdparty/libhwbase M 3rdparty/opensbi M 3rdparty/vboot M util/crossgcc/patches/binutils-2.32_as-ipxe.patch M util/nvidia/cbootimage 8 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/35144/1 diff --git a/3rdparty/blobs b/3rdparty/blobs index 62aa0e0..ca6cfcd 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit 62aa0e0c54295bbb7b1a3e5e73f960bafdb59d04 +Subproject commit ca6cfcdbe1cdeb38c2622ee2e5236cc4657e3377 diff --git a/3rdparty/fsp b/3rdparty/fsp index 5996417..162719b 160000 --- a/3rdparty/fsp +++ b/3rdparty/fsp @@ -1 +1 @@ -Subproject commit 59964173e18950debcc6b8856c5c928935ce0b4f +Subproject commit 162719b6cb5efc6c50dcb23dfdb378358573e2b6 diff --git a/3rdparty/libgfxinit b/3rdparty/libgfxinit index a815704..f70edda 160000 --- a/3rdparty/libgfxinit +++ b/3rdparty/libgfxinit @@ -1 +1 @@ -Subproject commit a815704c84b4823f5b723404a37efed9d6c85d66 +Subproject commit f70eddafbc2c6045a14e2f8bbb3273ee738fbaf7 diff --git a/3rdparty/libhwbase b/3rdparty/libhwbase index bd0ed91..637f2a4 160000 --- a/3rdparty/libhwbase +++ b/3rdparty/libhwbase @@ -1 +1 @@ -Subproject commit bd0ed91cb985a697033edd9fd62d322aa017e791 +Subproject commit 637f2a4f21ead8ccc45d5256834eb27ce72088db diff --git a/3rdparty/opensbi b/3rdparty/opensbi index ce228ee..804b997 160000 --- a/3rdparty/opensbi +++ b/3rdparty/opensbi @@ -1 +1 @@ -Subproject commit ce228ee0919deb9957192d723eecc8aaae2697c6 +Subproject commit 804b997ed415001097803e4b537fd63d043874b9 diff --git a/3rdparty/vboot b/3rdparty/vboot index e6700f4..304aa42 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit e6700f4c70fe72850ae4f3f5df19c9281ebcefc8 +Subproject commit 304aa429c1a04cda3ab2ce37b9e31af84405bfca diff --git a/util/crossgcc/patches/binutils-2.32_as-ipxe.patch b/util/crossgcc/patches/binutils-2.32_as-ipxe.patch index df95630..4d2c00a 100644 --- a/util/crossgcc/patches/binutils-2.32_as-ipxe.patch +++ b/util/crossgcc/patches/binutils-2.32_as-ipxe.patch @@ -1,5 +1,5 @@ From 6984bd861cc595e56d26ea033851d9174e855129 Mon Sep 17 00:00:00 2001 -From: CunningLearner <sahdev.himan(a)gmail.com> +From: Himanshu Sahdev aka CunningLearner <sahdev.himan(a)gmail.com> Date: Mon, 26 Aug 2019 16:57:13 +0530 Subject: [PATCH] as: facilitate tests based on /dev/null diff --git a/util/nvidia/cbootimage b/util/nvidia/cbootimage index 65a6d94..64045f9 160000 --- a/util/nvidia/cbootimage +++ b/util/nvidia/cbootimage @@ -1 +1 @@ -Subproject commit 65a6d94dd5f442578551e0a81ecbe5235e673fd4 +Subproject commit 64045f993c2cd8989838aeaad3d22107d96d5596 -- To view, visit https://review.coreboot.org/c/coreboot/+/35144 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I111cfae98286baef38bb95b9f30f0382b047ea03 Gerrit-Change-Number: 35144 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002476 Gerrit-MessageType: newchange

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Change in coreboot[master]: intel/fsp_broadwell_de: Use smm_subregion()
by Kyösti Mälkki (Code Review) 29 Aug '19

29 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34745 ) Change subject: intel/fsp_broadwell_de: Use smm_subregion() ...................................................................... intel/fsp_broadwell_de: Use smm_subregion() Change-Id: I986bbe978d3f68693b2d4538ccbcc11cdbd23c6a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/fsp_broadwell_de/include/soc/smm.h M src/soc/intel/fsp_broadwell_de/memmap.c M src/soc/intel/fsp_broadwell_de/smmrelocate.c 3 files changed, 64 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/34745/1 diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/smm.h b/src/soc/intel/fsp_broadwell_de/include/soc/smm.h index 72aa7fa..42cadb3 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/smm.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/smm.h @@ -27,10 +27,10 @@ } __packed; struct smm_relocation_params { - u32 smram_base; - u32 smram_size; - u32 ied_base; - u32 ied_size; + uintptr_t smram_base; + size_t smram_size; + uintptr_t ied_base; + size_t ied_size; msr_t smrr_base; msr_t smrr_mask; msr_t prmrr_base; diff --git a/src/soc/intel/fsp_broadwell_de/memmap.c b/src/soc/intel/fsp_broadwell_de/memmap.c index 7510094..c1a685b 100644 --- a/src/soc/intel/fsp_broadwell_de/memmap.c +++ b/src/soc/intel/fsp_broadwell_de/memmap.c @@ -14,10 +14,62 @@ * GNU General Public License for more details. */ +#define __SIMPLE_DEVICE__ + #include <cbmem.h> +#include <cpu/x86/smm.h> +#include <device/pci_ops.h> #include <drivers/intel/fsp1_0/fsp_util.h> +#include <soc/broadwell_de.h> void *cbmem_top(void) { return find_fsp_reserved_mem(*(void **)CBMEM_FSP_HOB_PTR); } + +void smm_region(uintptr_t *start, size_t *size) +{ + u32 tseg_base = pci_read_config32(PCI_DEV(0, 0, 0), TSEG_BASE); + u32 tseg_limit = pci_read_config32(PCI_DEV(0, 0, 0), TSEG_LIMIT); + *start = tseg_base; + *size = tseg_limit - tseg_base; +} + +/* Intel Enhanced Debug region must be 4MB */ +#define FIXED_IED_REGION_SIZE (4 << 20) + +int smm_subregion(int sub, uintptr_t *start, size_t *size) +{ + uintptr_t sub_base; + size_t sub_size; + const size_t ied_size = FIXED_IED_REGION_SIZE; + const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; + + smm_region(&sub_base, &sub_size); + + switch (sub) { + case SMM_SUBREGION_HANDLER: + /* Handler starts at the base of TSEG. */ + sub_size -= ied_size; + sub_size -= cache_size; + break; + case SMM_SUBREGION_CACHE: + /* External cache is in the middle of TSEG. */ + sub_base += sub_size - (ied_size + cache_size); + sub_size = cache_size; + break; + case SMM_SUBREGION_IED: + /* IED is at the top. */ + sub_base += sub_size - ied_size; + sub_size = ied_size; + break; + default: + *start = 0; + *size = 0; + return -1; + } + + *start = sub_base; + *size = sub_size; + return 0; +} diff --git a/src/soc/intel/fsp_broadwell_de/smmrelocate.c b/src/soc/intel/fsp_broadwell_de/smmrelocate.c index 57ba432..3086acb 100644 --- a/src/soc/intel/fsp_broadwell_de/smmrelocate.c +++ b/src/soc/intel/fsp_broadwell_de/smmrelocate.c @@ -190,22 +190,11 @@ write_prmrr(relo_params); } -static u32 northbridge_get_base_reg(pci_devfn_t dev, int reg) -{ - u32 value; - - value = pci_read_config32(dev, reg); - /* Base registers are at 1MiB granularity. */ - value &= ~((1 << 20) - 1); - return value; -} - static void fill_in_relocation_params(pci_devfn_t dev, struct smm_relocation_params *params) { - u32 tseg_size; - u32 tseg_base; - u32 tseg_limit; + uintptr_t tseg_base; + size_t tseg_size; u32 prmrr_base; u32 prmrr_size; int phys_bits; @@ -225,25 +214,18 @@ * The result is that BASE[19:0] is effectively 00000h and LIMIT is * effectively FFFFFh. */ - tseg_base = northbridge_get_base_reg(dev, TSEG_BASE); - tseg_limit = northbridge_get_base_reg(dev, TSEG_LIMIT) + 1 * MiB; - tseg_size = tseg_limit - tseg_base; - params->smram_base = tseg_base; - params->smram_size = 4 << 20; - params->ied_base = tseg_base + params->smram_size; - params->ied_size = tseg_size - params->smram_size; - - /* Adjust available SMM handler memory size. */ - params->smram_size -= CONFIG_SMM_RESERVED_SIZE; + smm_region(&tseg_base, &tseg_size); /* SMRR has 32-bits of valid address aligned to 4KiB. */ - params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK; + params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK; params->smrr_base.hi = 0; - params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | - MTRR_PHYS_MASK_VALID; + params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; params->smrr_mask.hi = 0; + smm_subregion(SMM_SUBREGION_HANDLER, &params->smram_base, &params->smram_size); + smm_subregion(SMM_SUBREGION_IED, &params->ied_base, &params->ied_size); + /* The PRMRR is at IEDBASE + 2MiB */ prmrr_base = (params->ied_base + (2 << 20)) & rmask; prmrr_size = params->ied_size - (2 << 20); -- To view, visit https://review.coreboot.org/c/coreboot/+/34745 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I986bbe978d3f68693b2d4538ccbcc11cdbd23c6a Gerrit-Change-Number: 34745 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/fsp_broadwell_de: Implement SystemAgent TSEG functions
by Kyösti Mälkki (Code Review) 29 Aug '19

29 Aug '19

Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33418 ) Change subject: soc/intel/fsp_broadwell_de: Implement SystemAgent TSEG functions ...................................................................... soc/intel/fsp_broadwell_de: Implement SystemAgent TSEG functions Implement sa_get_tseg_base and sa_get_tseg_size. Used by Intel TXT and the new SMM API. Tested on OCP/Wedge100S. Change-Id: I22123cbf8d65b25a77fbf72ae8411b23b10c13b4 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33418 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h M src/soc/intel/fsp_broadwell_de/memmap.c 2 files changed, 33 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h b/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h index edfeafc..4167895 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h @@ -18,6 +18,9 @@ #ifndef _SOC_BROADWELL_DE_H_ #define _SOC_BROADWELL_DE_H_ +uintptr_t sa_get_tseg_base(void); +size_t sa_get_tseg_size(void); + #define VTBAR_OFFSET 0x180 #define VTBAR_MASK 0xffffe000 #define VTBAR_ENABLED 0x01 diff --git a/src/soc/intel/fsp_broadwell_de/memmap.c b/src/soc/intel/fsp_broadwell_de/memmap.c index 7510094..36f400c 100644 --- a/src/soc/intel/fsp_broadwell_de/memmap.c +++ b/src/soc/intel/fsp_broadwell_de/memmap.c @@ -14,10 +14,40 @@ * GNU General Public License for more details. */ +#define __SIMPLE_DEVICE__ + #include <cbmem.h> #include <drivers/intel/fsp1_0/fsp_util.h> +#include <soc/broadwell_de.h> +#include <soc/pci_devs.h> +#include <device/pci_ops.h> void *cbmem_top(void) { return find_fsp_reserved_mem(*(void **)CBMEM_FSP_HOB_PTR); } + +/* + * Get TSEG base. + */ +uintptr_t sa_get_tseg_base(void) +{ + const pci_devfn_t dev = PCI_DEV(BUS0, VTD_DEV, VTD_FUNC); + + /* All regions concerned for have 1 MiB alignment. */ + return ALIGN_DOWN(pci_read_config32(dev, TSEG_BASE), 1 * MiB); +} + +size_t sa_get_tseg_size(void) +{ + const pci_devfn_t dev = PCI_DEV(BUS0, VTD_DEV, VTD_FUNC); + + /* All regions concerned for have 1 MiB alignment. */ + size_t ret = ALIGN_DOWN(pci_read_config32(dev, TSEG_LIMIT), 1 * MiB); + + /* Lower 20bit of TSEG_LIMIT are don't care, need to add 1MiB */ + ret += 1 * MiB; + + /* Subtract base to get the size */ + return ret - sa_get_tseg_base(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/33418 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22123cbf8d65b25a77fbf72ae8411b23b10c13b4 Gerrit-Change-Number: 33418 Gerrit-PatchSet: 8 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/fsp_broadwell_de: Implement SystemAgent TSEG functions
by Kyösti Mälkki (Code Review) 29 Aug '19

29 Aug '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33418 ) Change subject: soc/intel/fsp_broadwell_de: Implement SystemAgent TSEG functions ...................................................................... Patch Set 7: Code-Review+2 (5 comments) I broke master once again. I will address the issues with follow-up instead of reverting bunch of stuff. https://review.coreboot.org/c/coreboot/+/33418/7/src/soc/intel/fsp_broadwel… File src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h: https://review.coreboot.org/c/coreboot/+/33418/7/src/soc/intel/fsp_broadwel… PS7, Line 21: uintptr_t sa_get_tseg_base(void); > <types. […] Ack https://review.coreboot.org/c/coreboot/+/33418/7/src/soc/intel/fsp_broadwel… File src/soc/intel/fsp_broadwell_de/memmap.c: https://review.coreboot.org/c/coreboot/+/33418/7/src/soc/intel/fsp_broadwel… PS7, Line 33: uintptr_t sa_get_tseg_base(void) > <types. […] Ack https://review.coreboot.org/c/coreboot/+/33418/7/src/soc/intel/fsp_broadwel… PS7, Line 39: } > <commonlib/helpers. […] Ack https://review.coreboot.org/c/coreboot/+/33418/7/src/soc/intel/fsp_broadwel… PS7, Line 48: /* Lower 20bit of TSEG_LIMIT are don't care, need to add 1MiB */ > That could have been ALIGN_UP(limit, 1 * MiB) for the same result? Ack https://review.coreboot.org/c/coreboot/+/33418/3/src/soc/intel/fsp_broadwel… File src/soc/intel/fsp_broadwell_de/ramstage.c: https://review.coreboot.org/c/coreboot/+/33418/3/src/soc/intel/fsp_broadwel… PS3, Line 95: * > Add spaces around the operator. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/33418 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22123cbf8d65b25a77fbf72ae8411b23b10c13b4 Gerrit-Change-Number: 33418 Gerrit-PatchSet: 7 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Aug 2019 06:34:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: mediatek/mt8183: Set DRAM vlotage for each DRAM frequency
by Huayang Duan (Code Review) 29 Aug '19

29 Aug '19

Huayang Duan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35017 ) Change subject: mediatek/mt8183: Set DRAM vlotage for each DRAM frequency ...................................................................... Patch Set 2: Code-Review-1 wait vddq volatge adjust API from hsin-hsiung wang. -- To view, visit https://review.coreboot.org/c/coreboot/+/35017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9539473ff708f9d0d39eb17bd3fdcb916265d33e Gerrit-Change-Number: 35017 Gerrit-PatchSet: 2 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-Reviewer: Huayang Duan <huayang.duan(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-Reviewer: huayang duan <huayangduan(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 29 Aug 2019 05:55:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86: Fix clearing .bss section
by Kyösti Mälkki (Code Review) 29 Aug '19

29 Aug '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35139 ) Change subject: arch/x86: Fix clearing .bss section ...................................................................... Patch Set 1: > Patch Set 1: > > I wonder will break by this being correct? I think the error was harmless; CAR after _car_global_end is either unallocated or (yet) unused stack space. -- To view, visit https://review.coreboot.org/c/coreboot/+/35139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie54fcfcb7e5a2a5a88d988476aa69b2a163e919c Gerrit-Change-Number: 35139 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Aug 2019 04:09:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/soc/intel/common/itss: Add support to get IRQ configuration for P...
by Tim Wawrzynczak (Code Review) 29 Aug '19

29 Aug '19

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34089 ) Change subject: src/soc/intel/common/itss: Add support to get IRQ configuration for PCI devices ...................................................................... Patch Set 18: (7 comments) https://review.coreboot.org/c/coreboot/+/34089/8/src/soc/intel/common/block… File src/soc/intel/common/block/itss/irq.c: https://review.coreboot.org/c/coreboot/+/34089/8/src/soc/intel/common/block… PS8, Line 32: create_device_node > nit: This doesn't have anything to do with a device, rather with a list of IRQ information; maybe cr […] Ack https://review.coreboot.org/c/coreboot/+/34089/8/src/soc/intel/common/block… PS8, Line 71: static struct irq_node *info; : static int slot; : /* PIRx mapped from IRQ# 16:23 starting from PIRQA */ : static int int_line = PIRQA_APIC_IRQ; : static int int_lpss = PIRQA_APIC_IRQ; > This is more to keep track on previous assignment and use it abide by following IRQ allocation rules […] Ack https://review.coreboot.org/c/coreboot/+/34089/8/src/soc/intel/common/block… PS8, Line 93: * only interrupt 16-23 can be shared */ : if (int_line > 23) > I think initializing it with static int int_line = PIRQA_APIC_IRQ would ensure it. […] Ack https://review.coreboot.org/c/coreboot/+/34089/8/src/soc/intel/common/block… PS8, Line 102: static bool is_irq_dev(struct device *dev) : { : static size_t size; : static const int *devlist; : : if (!devlist) : devlist = soc_irq_devices_list(&size); : for (int i = 0; i < size; i++) { : if (dev->path.pci.devfn == devlist[i]) : return true; : } : return false; : } : > yeah, for each pci device in the tree , wanted to avoid soc call backs Ack https://review.coreboot.org/c/coreboot/+/34089/17/src/soc/intel/common/bloc… File src/soc/intel/common/block/itss/irq.c: https://review.coreboot.org/c/coreboot/+/34089/17/src/soc/intel/common/bloc… PS17, Line 31: * 3. LPSS controllers need to be assigned unique IRQs > Done. […] Ack https://review.coreboot.org/c/coreboot/+/34089/18/src/soc/intel/common/bloc… File src/soc/intel/common/block/itss/irq.c: https://review.coreboot.org/c/coreboot/+/34089/18/src/soc/intel/common/bloc… PS18, Line 41: Is there a concern there could be more than 8 LPSS devices requiring IRQ assignment? Maybe we need an error here if int_lpss > 23 ? https://review.coreboot.org/c/coreboot/+/34089/18/src/soc/intel/common/bloc… PS18, Line 99: index To me, exiting early if index becomes >= num_entries shows the error a little more clearly. What do you think? -- To view, visit https://review.coreboot.org/c/coreboot/+/34089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7066432ff5f0d7017ac5a44922ca69f07da9556 Gerrit-Change-Number: 34089 Gerrit-PatchSet: 18 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 29 Aug 2019 02:31:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Aamir Bohra <aamir.bohra(a)intel.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit August 2019