coreboot-gerrit August 2019

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Change in coreboot[master]: mb/dell: Add Dell Optiplex 790
by Angel Pons (Code Review) 29 Aug '19

29 Aug '19

Angel Pons has uploaded a new patch set (#58) to the change originally created by Christoph Pomaska. ( https://review.coreboot.org/c/coreboot/+/21774 ) Change subject: mb/dell: Add Dell Optiplex 790 ...................................................................... mb/dell: Add Dell Optiplex 790 This port was generated by autoport and has been tweaked (see below) There are (at least) three different mainboards: - DT: 4 RAM slots, PEG, PCIe x1, PCI, PCIe x16 - MT: 4 RAM slots, PEG, PCIe x1, PCI, PCIe x16 - SFF: 4 RAM slots, PEG, PCIe x16 - USFF: 2 RAM slots, mPCIe The variants have different PCI/PCIe configurations and are not exactly compatible towards each other. This port has been tested with: SFF, USFF What works: - Booting Arch Linux with kernel 5.2.3-arch1-1-ARCH - PCIe (Hotplug on PCIe X1 only!) - Onboard graphics with libgfxinit (via VGA) - Turning on and off (S5) - Harddrive activity LED - Onboard sound - Onboard ethernet - SATA (hotplug) - IOMMU - Suspend/resume (S3) - EHCI debug (rear side, bottom port on the block with ethernet) What does not work: - SuperI/O (Chip is a SCH5544-NS) - Serial port - PS/2 - Fan control (fans go to full speed) - VBT is missing Further notes: - Default IFD settings block reads/writes to some regions. This can be bypassed by plugging the SERVICE_MODE jumper. BIOS version A05 does not set any protected ranges, so internal flashing is possible (use a layout if the SERVICE_MODE jumper is not plugged). - Setting the jumper slows down the boot process of coreboot significantly, as coreboot waits 900ms for the ME to report an OK DRAM (which doesn't happen with the jumper set) - The controller that controls the POST code LEDs on the front of the case (likely the SuperIO) stays on slow blinking POST 234, corrupt or defect BIOS according to [1]. - The mainboard has one SOIC16 8192KiB and one SOIC8 2048KiB BIOS chip that are recognized as one "Opaque flash chip" of 10240K in size. - Without the VGA_BIOS_FILE the make process starts behaving weird, so I will keep it in until further notice (Is this still true?) [1] http://www.dell.com/support/article/us/en/04/sln284978/a-reference-guide-to… Change-Id: If3d3a13163d5da1368259a7498019d42fb3ed57f Signed-off-by: Christoph Pomaska <github(a)aufmachen.jetzt> Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/mainboard/dell/Kconfig A src/mainboard/dell/Kconfig.name A src/mainboard/dell/optiplex_790/Kconfig A src/mainboard/dell/optiplex_790/Kconfig.name A src/mainboard/dell/optiplex_790/Makefile.inc A src/mainboard/dell/optiplex_790/acpi/ec.asl A src/mainboard/dell/optiplex_790/acpi/platform.asl A src/mainboard/dell/optiplex_790/acpi/superio.asl A src/mainboard/dell/optiplex_790/acpi_tables.c A src/mainboard/dell/optiplex_790/board_info.txt A src/mainboard/dell/optiplex_790/dsdt.asl A src/mainboard/dell/optiplex_790/gma-mainboard.ads A src/mainboard/dell/optiplex_790/hda_verb.c A src/mainboard/dell/optiplex_790/mainboard.c A src/mainboard/dell/optiplex_790/romstage.c A src/mainboard/dell/optiplex_790/variants/optiplex_790_mt-sff/devicetree.cb A src/mainboard/dell/optiplex_790/variants/optiplex_790_mt-sff/gpio.c A src/mainboard/dell/optiplex_790/variants/optiplex_790_mt-sff/hda_verb.c A src/mainboard/dell/optiplex_790/variants/optiplex_790_usff/devicetree.cb A src/mainboard/dell/optiplex_790/variants/optiplex_790_usff/gpio.c A src/mainboard/dell/optiplex_790/variants/optiplex_790_usff/hda_verb.c 21 files changed, 1,140 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/21774/58 -- To view, visit https://review.coreboot.org/c/coreboot/+/21774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3d3a13163d5da1368259a7498019d42fb3ed57f Gerrit-Change-Number: 21774 Gerrit-PatchSet: 58 Gerrit-Owner: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: arch/x86: Fix clearing .bss section
by Aaron Durbin (Code Review) 29 Aug '19

29 Aug '19

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35139 ) Change subject: arch/x86: Fix clearing .bss section ...................................................................... Patch Set 1: I wonder will break by this being correct? -- To view, visit https://review.coreboot.org/c/coreboot/+/35139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie54fcfcb7e5a2a5a88d988476aa69b2a163e919c Gerrit-Change-Number: 35139 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 28 Aug 2019 23:16:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86: Fix clearing .bss section
by Aaron Durbin (Code Review) 29 Aug '19

29 Aug '19

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35139 ) Change subject: arch/x86: Fix clearing .bss section ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/35139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie54fcfcb7e5a2a5a88d988476aa69b2a163e919c Gerrit-Change-Number: 35139 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 28 Aug 2019 23:16:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86: Drop weak attribute on stage_cache
by Kyösti Mälkki (Code Review) 29 Aug '19

29 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34741 ) Change subject: arch/x86: Drop weak attribute on stage_cache ...................................................................... arch/x86: Drop weak attribute on stage_cache There are no more cases that need to override this. Change-Id: Iafa94af19eae00cc5be5d4ff7454066558e3c74f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/x86/smm/stage_cache.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/34741/1 diff --git a/src/cpu/x86/smm/stage_cache.c b/src/cpu/x86/smm/stage_cache.c index 0a816ba..1c0309c 100644 --- a/src/cpu/x86/smm/stage_cache.c +++ b/src/cpu/x86/smm/stage_cache.c @@ -23,7 +23,7 @@ return -1; } -void __weak stage_cache_external_region(void **base, size_t *size) +void stage_cache_external_region(void **base, size_t *size) { if (smm_subregion(SMM_SUBREGION_CACHE, (uintptr_t *)base, size)) { printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/34741 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iafa94af19eae00cc5be5d4ff7454066558e3c74f Gerrit-Change-Number: 34741 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: intel/broadwell: Use smm_subregion()
by Kyösti Mälkki (Code Review) 29 Aug '19

29 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34738 ) Change subject: intel/broadwell: Use smm_subregion() ...................................................................... intel/broadwell: Use smm_subregion() Change-Id: I95f1685f9b74f68fd6cb681a614e52b8e0748216 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/broadwell/Kconfig M src/soc/intel/broadwell/include/soc/smm.h M src/soc/intel/broadwell/memmap.c M src/soc/intel/broadwell/smmrelocate.c 4 files changed, 57 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/34738/1 diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 696cf98..5b29728 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -91,10 +91,6 @@ hex default 0x800000 -config IED_REGION_SIZE - hex - default 0x400000 - config SMM_RESERVED_SIZE hex default 0x100000 diff --git a/src/soc/intel/broadwell/include/soc/smm.h b/src/soc/intel/broadwell/include/soc/smm.h index d3e1cdd..0c6f587 100644 --- a/src/soc/intel/broadwell/include/soc/smm.h +++ b/src/soc/intel/broadwell/include/soc/smm.h @@ -26,10 +26,10 @@ } __packed; struct smm_relocation_params { - u32 smram_base; - u32 smram_size; - u32 ied_base; - u32 ied_size; + uintptr_t smram_base; + size_t smram_size; + uintptr_t ied_base; + size_t ied_size; msr_t smrr_base; msr_t smrr_mask; msr_t emrr_base; diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index 7c53fa6..08d7b36 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -16,6 +16,7 @@ #define __SIMPLE_DEVICE__ #include <cbmem.h> +#include <cpu/x86/smm.h> #include <device/pci.h> #include <device/pci_ops.h> #include <soc/pci_devs.h> @@ -46,14 +47,50 @@ return (void *) dpr_region_start(); } -void stage_cache_external_region(void **base, size_t *size) +void smm_region(uintptr_t *start, size_t *size) { - /* The ramstage cache lives in the TSEG region. - * The top of RAM is defined to be the TSEG base address. */ - u32 offset = smm_region_size(); - offset -= CONFIG_IED_REGION_SIZE; - offset -= CONFIG_SMM_RESERVED_SIZE; + uintptr_t tseg = pci_read_config32(PCI_DEV(0, 0, 0), TSEG); + uintptr_t bgsm = pci_read_config32(PCI_DEV(0, 0, 0), BGSM); - *base = (void *)(cbmem_top() + offset); - *size = CONFIG_SMM_RESERVED_SIZE; + *start = tseg; + *size = bgsm - tseg;; +} + +/* Intel Enhanced Debug region must be 4MB */ +#define FIXED_IED_REGION_SIZE (4 << 20) + +int smm_subregion(int sub, uintptr_t *start, size_t *size) +{ + uintptr_t sub_base; + size_t sub_size; + const size_t ied_size = FIXED_IED_REGION_SIZE; + const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; + + smm_region(&sub_base, &sub_size); + + switch (sub) { + case SMM_SUBREGION_HANDLER: + /* Handler starts at the base of TSEG. */ + sub_size -= ied_size; + sub_size -= cache_size; + break; + case SMM_SUBREGION_CACHE: + /* External cache is in the middle of TSEG. */ + sub_base += sub_size - (ied_size + cache_size); + sub_size = cache_size; + break; + case SMM_SUBREGION_IED: + /* IED is at the top. */ + sub_base += sub_size - ied_size; + sub_size = ied_size; + break; + default: + *start = 0; + *size = 0; + return -1; + } + + *start = sub_base; + *size = sub_size; + return 0; } diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c index 9ea73b2..7e893c1 100644 --- a/src/soc/intel/broadwell/smmrelocate.c +++ b/src/soc/intel/broadwell/smmrelocate.c @@ -179,22 +179,11 @@ } } -static u32 northbridge_get_base_reg(struct device *dev, int reg) -{ - u32 value; - - value = pci_read_config32(dev, reg); - /* Base registers are at 1MiB granularity. */ - value &= ~((1 << 20) - 1); - return value; -} - static void fill_in_relocation_params(struct device *dev, struct smm_relocation_params *params) { - u32 tseg_size; - u32 tsegmb; - u32 bgsm; + uintptr_t tseg_base; + size_t tseg_size; u32 emrr_base; u32 emrr_size; int phys_bits; @@ -209,25 +198,17 @@ * SMRAM range as well as the IED range. However, the SMRAM available * to the handler is 4MiB since the IEDRAM lives TSEGMB + 4MiB. */ - tsegmb = northbridge_get_base_reg(dev, TSEG); - bgsm = northbridge_get_base_reg(dev, BGSM); - tseg_size = bgsm - tsegmb; - - params->smram_base = tsegmb; - params->smram_size = 4 << 20; - params->ied_base = tsegmb + params->smram_size; - params->ied_size = tseg_size - params->smram_size; - - /* Adjust available SMM handler memory size. */ - params->smram_size -= CONFIG_SMM_RESERVED_SIZE; + smm_region(&tseg_base, &tseg_size); /* SMRR has 32-bits of valid address aligned to 4KiB. */ - params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK; + params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK; params->smrr_base.hi = 0; - params->smrr_mask.lo = (~(tseg_size - 1) & rmask) - | MTRR_PHYS_MASK_VALID; + params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; params->smrr_mask.hi = 0; + smm_subregion(SMM_SUBREGION_HANDLER, &params->smram_base, &params->smram_size); + smm_subregion(SMM_SUBREGION_IED, &params->ied_base, &params->ied_size); + /* The EMRR and UNCORE_EMRR are at IEDBASE + 2MiB */ emrr_base = (params->ied_base + (2 << 20)) & rmask; emrr_size = params->ied_size - (2 << 20); -- To view, visit https://review.coreboot.org/c/coreboot/+/34738 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95f1685f9b74f68fd6cb681a614e52b8e0748216 Gerrit-Change-Number: 34738 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: intel/haswell: Use smm_subregion()
by Kyösti Mälkki (Code Review) 29 Aug '19

29 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34737 ) Change subject: intel/haswell: Use smm_subregion() ...................................................................... intel/haswell: Use smm_subregion() Change-Id: Idfb13ab03d4d4ae764bdda62a29848db9d8dcd81 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/haswell/Kconfig M src/cpu/intel/haswell/haswell.h M src/cpu/intel/haswell/smmrelocate.c M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/memmap.c 5 files changed, 61 insertions(+), 55 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/34737/1 diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 8f91b60..90ac679 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -28,10 +28,6 @@ hex default 0x800000 -config IED_REGION_SIZE - hex - default 0x400000 - config SMM_RESERVED_SIZE hex default 0x100000 diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index cfd9d45..bdfce8d 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -118,19 +118,12 @@ /* Data is passed through bits 31:0 of the data register. */ #define BIOS_MAILBOX_DATA 0x5da0 -/* Sanity check config options. */ -#if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE)) -# error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE)" -#endif #if (CONFIG_SMM_TSEG_SIZE < 0x800000) # error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB" #endif #if ((CONFIG_SMM_TSEG_SIZE & (CONFIG_SMM_TSEG_SIZE - 1)) != 0) # error "CONFIG_SMM_TSEG_SIZE is not a power of 2" #endif -#if ((CONFIG_IED_REGION_SIZE & (CONFIG_IED_REGION_SIZE - 1)) != 0) -# error "CONFIG_IED_REGION_SIZE is not a power of 2" -#endif #if !defined(__ROMCC__) // FIXME romcc should handle below constructs diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 3a4a0a7..ca2c68f 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -46,10 +46,10 @@ #define EMRR_SUPPORTED (1 << 12) struct smm_relocation_params { - u32 smram_base; - u32 smram_size; - u32 ied_base; - u32 ied_size; + uintptr_t smram_base; + size_t smram_size; + uintptr_t ied_base; + size_t ied_size; msr_t smrr_base; msr_t smrr_mask; msr_t emrr_base; @@ -210,22 +210,12 @@ } } -static u32 northbridge_get_base_reg(struct device *dev, int reg) -{ - u32 value; - - value = pci_read_config32(dev, reg); - /* Base registers are at 1MiB granularity. */ - value &= ~((1 << 20) - 1); - return value; -} - static void fill_in_relocation_params(struct device *dev, struct smm_relocation_params *params) { - u32 tseg_size; - u32 tsegmb; - u32 bgsm; + uintptr_t tseg_base; + size_t tseg_size; + u32 emrr_base; u32 emrr_size; int phys_bits; @@ -240,25 +230,17 @@ * SMRAM range as well as the IED range. However, the SMRAM available * to the handler is 4MiB since the IEDRAM lives TSEGMB + 4MiB. */ - tsegmb = northbridge_get_base_reg(dev, TSEG); - bgsm = northbridge_get_base_reg(dev, BGSM); - tseg_size = bgsm - tsegmb; - - params->smram_base = tsegmb; - params->smram_size = 4 << 20; - params->ied_base = tsegmb + params->smram_size; - params->ied_size = tseg_size - params->smram_size; - - /* Adjust available SMM handler memory size. */ - params->smram_size -= CONFIG_SMM_RESERVED_SIZE; + smm_region(&tseg_base, &tseg_size); /* SMRR has 32-bits of valid address aligned to 4KiB. */ - params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK; + params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK; params->smrr_base.hi = 0; - params->smrr_mask.lo = (~(tseg_size - 1) & rmask) - | MTRR_PHYS_MASK_VALID; + params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; params->smrr_mask.hi = 0; + smm_subregion(SMM_SUBREGION_HANDLER, &params->smram_base, &params->smram_size); + smm_subregion(SMM_SUBREGION_IED, &params->ied_base, &params->ied_size); + /* The EMRR and UNCORE_EMRR are at IEDBASE + 2MiB */ emrr_base = (params->ied_base + (2 << 20)) & rmask; emrr_size = params->ied_size - (2 << 20); diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index dc0e5db..a4c6934 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -22,9 +22,6 @@ #define HASWELL_DESKTOP 1 #define HASWELL_SERVER 2 -/* Intel Enhanced Debug region */ -#define IED_SIZE CONFIG_IED_REGION_SIZE - /* Northbridge BARs */ #define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ #ifndef __ACPI__ @@ -225,6 +222,14 @@ void report_platform_info(void); #endif /* !__SMM__ */ +/* Intel Enhanced Debug region must be 4MB */ +#define FIXED_IED_REGION_SIZE (4 << 20) + +/* Sanity check config options. */ +#if (CONFIG_SMM_TSEG_SIZE <= (FIXED_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE)) +# error "CONFIG_SMM_TSEG_SIZE <= (FIXED_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE)" +#endif + #if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__) #include <device/device.h> diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c index 3a63afc..02b9572 100644 --- a/src/northbridge/intel/haswell/memmap.c +++ b/src/northbridge/intel/haswell/memmap.c @@ -18,6 +18,7 @@ #include <device/pci_ops.h> #include <cbmem.h> +#include <cpu/x86/smm.h> #include <stage_cache.h> #include "haswell.h" @@ -36,15 +37,44 @@ return (void *)smm_region_start(); } -/* Region of SMM space is reserved for multipurpose use. It falls below - * the IED region and above the SMM handler. */ -#define RESERVED_SMM_OFFSET \ - (CONFIG_SMM_TSEG_SIZE - CONFIG_IED_REGION_SIZE - CONFIG_SMM_RESERVED_SIZE) - -void stage_cache_external_region(void **base, size_t *size) +void smm_region(uintptr_t *start, size_t *size) { - /* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. - * The top of RAM is defined to be the TSEG base address. */ - *size = CONFIG_SMM_RESERVED_SIZE; - *base = (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET); + *start = ALIGN_DOWN(smm_region_start(), 1*MiB); + *size = CONFIG_SMM_TSEG_SIZE; +} + +int smm_subregion(int sub, uintptr_t *start, size_t *size) +{ + uintptr_t sub_base; + size_t sub_size; + const size_t ied_size = FIXED_IED_REGION_SIZE; + const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; + + smm_region(&sub_base, &sub_size); + + switch (sub) { + case SMM_SUBREGION_HANDLER: + /* Handler starts at the base of TSEG. */ + sub_size -= ied_size; + sub_size -= cache_size; + break; + case SMM_SUBREGION_CACHE: + /* External cache is in the middle of TSEG. */ + sub_base += sub_size - (ied_size + cache_size); + sub_size = cache_size; + break; + case SMM_SUBREGION_IED: + /* IED is at the top. */ + sub_base += sub_size - ied_size; + sub_size = ied_size; + break; + default: + *start = 0; + *size = 0; + return -1; + } + + *start = sub_base; + *size = sub_size; + return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/34737 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idfb13ab03d4d4ae764bdda62a29848db9d8dcd81 Gerrit-Change-Number: 34737 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 13

Change in coreboot[master]: intel/haswell,broadwell: Rename EMRR to PRMRR
by Kyösti Mälkki (Code Review) 29 Aug '19

29 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34825 ) Change subject: intel/haswell,broadwell: Rename EMRR to PRMRR ...................................................................... intel/haswell,broadwell: Rename EMRR to PRMRR The MSRs were already named as PRMRR in broadwell, just mismatching with the rest of the code. All later devices use the names PRMRR and UNCORE_PRMRR for these MSRs. Reflect the name change in structures and local variables. Change-Id: Id825ba2c083d0def641dd9bf02d3b671d85b1e35 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/haswell/smmrelocate.c M src/soc/intel/broadwell/include/soc/msr.h M src/soc/intel/broadwell/smmrelocate.c 3 files changed, 73 insertions(+), 73 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/34825/1 diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 1575542..5cda618 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -30,10 +30,10 @@ #include <southbridge/intel/lynxpoint/pch.h> #include "haswell.h" -#define EMRRphysBase_MSR 0x1f4 -#define EMRRphysMask_MSR 0x1f5 -#define UNCORE_EMRRphysBase_MSR 0x2f4 -#define UNCORE_EMRRphysMask_MSR 0x2f5 +#define MSR_PRMRR_PHYS_BASE 0x1f4 +#define MSR_PRMRR_PHYS_MASK 0x1f5 +#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4 +#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5 #define SMM_MCA_CAP_MSR 0x17d #define SMM_CPU_SVRSTR_BIT 57 #define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) @@ -44,17 +44,17 @@ #define IEDBASE_MSR 0xc22 #define SMRR_SUPPORTED (1 << 11) -#define EMRR_SUPPORTED (1 << 12) +#define PRMRR_SUPPORTED (1 << 12) struct smm_relocation_params { uintptr_t ied_base; size_t ied_size; msr_t smrr_base; msr_t smrr_mask; - msr_t emrr_base; - msr_t emrr_mask; - msr_t uncore_emrr_base; - msr_t uncore_emrr_mask; + msr_t prmrr_base; + msr_t prmrr_mask; + msr_t uncore_prmrr_base; + msr_t uncore_prmrr_mask; /* The smm_save_state_in_msrs field indicates if SMM save state * locations live in MSRs. This indicates to the CPUs how to adjust * the SMMBASE and IEDBASE */ @@ -72,22 +72,22 @@ wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); } -static inline void write_emrr(struct smm_relocation_params *relo_params) +static inline void write_prmrr(struct smm_relocation_params *relo_params) { - printk(BIOS_DEBUG, "Writing EMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->emrr_base.lo, relo_params->emrr_mask.lo); - wrmsr(EMRRphysBase_MSR, relo_params->emrr_base); - wrmsr(EMRRphysMask_MSR, relo_params->emrr_mask); + printk(BIOS_DEBUG, "Writing PRMRR. base = 0x%08x, mask=0x%08x\n", + relo_params->prmrr_base.lo, relo_params->prmrr_mask.lo); + wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->prmrr_base); + wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->prmrr_mask); } -static inline void write_uncore_emrr(struct smm_relocation_params *relo_params) +static inline void write_uncore_prmrr(struct smm_relocation_params *relo_params) { printk(BIOS_DEBUG, - "Writing UNCORE_EMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->uncore_emrr_base.lo, - relo_params->uncore_emrr_mask.lo); - wrmsr(UNCORE_EMRRphysBase_MSR, relo_params->uncore_emrr_base); - wrmsr(UNCORE_EMRRphysMask_MSR, relo_params->uncore_emrr_mask); + "Writing UNCORE_PRMRR. base = 0x%08x, mask=0x%08x\n", + relo_params->uncore_prmrr_base.lo, + relo_params->uncore_prmrr_mask.lo); + wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_prmrr_base); + wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_prmrr_mask); } static void update_save_state(int cpu, uintptr_t curr_smbase, @@ -195,17 +195,17 @@ /* Make appropriate changes to the save state map. */ update_save_state(cpu, curr_smbase, staggered_smbase, relo_params); - /* Write EMRR and SMRR MSRs based on indicated support. */ + /* Write PRMRR and SMRR MSRs based on indicated support. */ mtrr_cap = rdmsr(MTRR_CAP_MSR); if (mtrr_cap.lo & SMRR_SUPPORTED) write_smrr(relo_params); - if (mtrr_cap.lo & EMRR_SUPPORTED) { - write_emrr(relo_params); - /* UNCORE_EMRR msrs are package level. Therefore, only + if (mtrr_cap.lo & PRMRR_SUPPORTED) { + write_prmrr(relo_params); + /* UNCORE_PRMRR msrs are package level. Therefore, only * configure these MSRs on the BSP. */ if (cpu == 0) - write_uncore_emrr(relo_params); + write_uncore_prmrr(relo_params); } } @@ -214,8 +214,8 @@ uintptr_t tseg_base; size_t tseg_size; - u32 emrr_base; - u32 emrr_size; + u32 prmrr_base; + u32 prmrr_size; int phys_bits; /* All range registers are aligned to 4KiB */ const u32 rmask = ~((1 << 12) - 1); @@ -238,24 +238,24 @@ smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size); - /* The EMRR and UNCORE_EMRR are at IEDBASE + 2MiB */ - emrr_base = (params->ied_base + (2 << 20)) & rmask; - emrr_size = params->ied_size - (2 << 20); + /* The PRMRR and UNCORE_PRMRR are at IEDBASE + 2MiB */ + prmrr_base = (params->ied_base + (2 << 20)) & rmask; + prmrr_size = params->ied_size - (2 << 20); - /* EMRR has 46 bits of valid address aligned to 4KiB. It's dependent + /* PRMRR has 46 bits of valid address aligned to 4KiB. It's dependent * on the number of physical address bits supported. */ - params->emrr_base.lo = emrr_base | MTRR_TYPE_WRBACK; - params->emrr_base.hi = 0; - params->emrr_mask.lo = (~(emrr_size - 1) & rmask) + params->prmrr_base.lo = prmrr_base | MTRR_TYPE_WRBACK; + params->prmrr_base.hi = 0; + params->prmrr_mask.lo = (~(prmrr_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; - params->emrr_mask.hi = (1 << (phys_bits - 32)) - 1; + params->prmrr_mask.hi = (1 << (phys_bits - 32)) - 1; - /* UNCORE_EMRR has 39 bits of valid address aligned to 4KiB. */ - params->uncore_emrr_base.lo = emrr_base; - params->uncore_emrr_base.hi = 0; - params->uncore_emrr_mask.lo = (~(emrr_size - 1) & rmask) | + /* UNCORE_PRMRR has 39 bits of valid address aligned to 4KiB. */ + params->uncore_prmrr_base.lo = prmrr_base; + params->uncore_prmrr_base.hi = 0; + params->uncore_prmrr_mask.lo = (~(prmrr_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; - params->uncore_emrr_mask.hi = (1 << (39 - 32)) - 1; + params->uncore_prmrr_mask.hi = (1 << (39 - 32)) - 1; } static void setup_ied_area(struct smm_relocation_params *params) @@ -278,7 +278,7 @@ /* According to the BWG MP init section 2MiB of memory at IEDBASE + * 2MiB should be zeroed as well. However, I suspect what is intended - * is to clear the memory covered by EMRR. TODO(adurbin): figure out if + * is to clear the memory covered by PRMRR. TODO(adurbin): figure out if * this is really required. */ //memset(ied_base + (2 << 20), 0, (2 << 20)); diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h index e8e3aa2..9e196c1 100644 --- a/src/soc/intel/broadwell/include/soc/msr.h +++ b/src/soc/intel/broadwell/include/soc/msr.h @@ -87,6 +87,6 @@ /* MTRR_CAP_MSR bits */ #define SMRR_SUPPORTED (1<<11) -#define EMRR_SUPPORTED (1<<12) +#define PRMRR_SUPPORTED (1<<12) #endif diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c index 0602928..2cf97e3 100644 --- a/src/soc/intel/broadwell/smmrelocate.c +++ b/src/soc/intel/broadwell/smmrelocate.c @@ -43,22 +43,22 @@ wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); } -static inline void write_emrr(struct smm_relocation_params *relo_params) +static inline void write_prmrr(struct smm_relocation_params *relo_params) { - printk(BIOS_DEBUG, "Writing EMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->emrr_base.lo, relo_params->emrr_mask.lo); - wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->emrr_base); - wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->emrr_mask); + printk(BIOS_DEBUG, "Writing PRMRR. base = 0x%08x, mask=0x%08x\n", + relo_params->prmrr_base.lo, relo_params->prmrr_mask.lo); + wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->prmrr_base); + wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->prmrr_mask); } -static inline void write_uncore_emrr(struct smm_relocation_params *relo_params) +static inline void write_uncore_prmrr(struct smm_relocation_params *relo_params) { printk(BIOS_DEBUG, - "Writing UNCORE_EMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->uncore_emrr_base.lo, - relo_params->uncore_emrr_mask.lo); - wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_emrr_base); - wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_emrr_mask); + "Writing UNCORE_PRMRR. base = 0x%08x, mask=0x%08x\n", + relo_params->uncore_prmrr_base.lo, + relo_params->uncore_prmrr_mask.lo); + wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_prmrr_base); + wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_prmrr_mask); } static void update_save_state(int cpu, uintptr_t curr_smbase, @@ -166,17 +166,17 @@ /* Make appropriate changes to the save state map. */ update_save_state(cpu, curr_smbase, staggered_smbase, relo_params); - /* Write EMRR and SMRR MSRs based on indicated support. */ + /* Write PRMRR and SMRR MSRs based on indicated support. */ mtrr_cap = rdmsr(MTRR_CAP_MSR); if (mtrr_cap.lo & SMRR_SUPPORTED) write_smrr(relo_params); - if (mtrr_cap.lo & EMRR_SUPPORTED) { - write_emrr(relo_params); - /* UNCORE_EMRR msrs are package level. Therefore, only + if (mtrr_cap.lo & PRMRR_SUPPORTED) { + write_prmrr(relo_params); + /* UNCORE_PRMRR msrs are package level. Therefore, only * configure these MSRs on the BSP. */ if (cpu == 0) - write_uncore_emrr(relo_params); + write_uncore_prmrr(relo_params); } } @@ -184,8 +184,8 @@ { uintptr_t tseg_base; size_t tseg_size; - u32 emrr_base; - u32 emrr_size; + u32 prmrr_base; + u32 prmrr_size; int phys_bits; /* All range registers are aligned to 4KiB */ const u32 rmask = ~((1 << 12) - 1); @@ -208,24 +208,24 @@ smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size); - /* The EMRR and UNCORE_EMRR are at IEDBASE + 2MiB */ - emrr_base = (params->ied_base + (2 << 20)) & rmask; - emrr_size = params->ied_size - (2 << 20); + /* The PRMRR and UNCORE_PRMRR are at IEDBASE + 2MiB */ + prmrr_base = (params->ied_base + (2 << 20)) & rmask; + prmrr_size = params->ied_size - (2 << 20); - /* EMRR has 46 bits of valid address aligned to 4KiB. It's dependent + /* PRMRR has 46 bits of valid address aligned to 4KiB. It's dependent * on the number of physical address bits supported. */ - params->emrr_base.lo = emrr_base | MTRR_TYPE_WRBACK; - params->emrr_base.hi = 0; - params->emrr_mask.lo = (~(emrr_size - 1) & rmask) + params->prmrr_base.lo = prmrr_base | MTRR_TYPE_WRBACK; + params->prmrr_base.hi = 0; + params->prmrr_mask.lo = (~(prmrr_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; - params->emrr_mask.hi = (1 << (phys_bits - 32)) - 1; + params->prmrr_mask.hi = (1 << (phys_bits - 32)) - 1; - /* UNCORE_EMRR has 39 bits of valid address aligned to 4KiB. */ - params->uncore_emrr_base.lo = emrr_base; - params->uncore_emrr_base.hi = 0; - params->uncore_emrr_mask.lo = (~(emrr_size - 1) & rmask) | + /* UNCORE_PRMRR has 39 bits of valid address aligned to 4KiB. */ + params->uncore_prmrr_base.lo = prmrr_base; + params->uncore_prmrr_base.hi = 0; + params->uncore_prmrr_mask.lo = (~(prmrr_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; - params->uncore_emrr_mask.hi = (1 << (39 - 32)) - 1; + params->uncore_prmrr_mask.hi = (1 << (39 - 32)) - 1; } static void setup_ied_area(struct smm_relocation_params *params) -- To view, visit https://review.coreboot.org/c/coreboot/+/34825 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id825ba2c083d0def641dd9bf02d3b671d85b1e35 Gerrit-Change-Number: 34825 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: intel/braswell: Use smm_subregion()
by Kyösti Mälkki (Code Review) 29 Aug '19

29 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34758 ) Change subject: intel/braswell: Use smm_subregion() ...................................................................... intel/braswell: Use smm_subregion() Change-Id: I4af661f68c158cbed591fe017d4bc25239bddd37 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/braswell/cpu.c 1 file changed, 28 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/34758/1 diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index 1cee4b9..dfb6b84d 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -95,13 +95,12 @@ * MP and SMM loading initialization. */ -struct smm_relocation_attrs { - uint32_t smbase; - uint32_t smrr_base; - uint32_t smrr_mask; +struct smm_relocation_params { + msr_t smrr_base; + msr_t smrr_mask; }; -static struct smm_relocation_attrs relo_attrs; +static struct smm_relocation_params smm_reloc_params; /* Package level MSRs */ static const struct reg_script package_msr_script[] = { @@ -147,25 +146,33 @@ return pattrs->num_cpus; } +static void fill_in_relocation_params(struct smm_relocation_params *params) +{ + uintptr_t tseg_base; + size_t tseg_size; + + /* All range registers are aligned to 4KiB */ + const u32 rmask = ~((1 << 12) - 1); + + smm_region(&tseg_base, &tseg_size); + + /* SMRR has 32-bits of valid address aligned to 4KiB. */ + params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK; + params->smrr_base.hi = 0; + params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; + params->smrr_mask.hi = 0; +} + static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { - uintptr_t smm_base; - size_t smm_size; + printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - /* All range registers are aligned to 4KiB */ - const uint32_t rmask = ~((1 << 12) - 1); + fill_in_relocation_params(&smm_reloc_params); - /* Initialize global tracking state. */ - smm_region(&smm_base, &smm_size); - relo_attrs.smbase = smm_base; - relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK; - relo_attrs.smrr_mask = ~(smm_size - 1) & rmask; - relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID; + smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); - *perm_smbase = relo_attrs.smbase; - *perm_smsize = smm_size - CONFIG_SMM_RESERVED_SIZE; - *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t); + *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t); } static void get_microcode_info(const void **microcode, int *parallel) @@ -196,16 +203,12 @@ static void relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase) { - msr_t smrr; + struct smm_relocation_params *relo_params = &smm_reloc_params; em64t100_smm_state_save_area_t *smm_state; /* Set up SMRR. */ - smrr.lo = relo_attrs.smrr_base; - smrr.hi = 0; - wrmsr(IA32_SMRR_PHYS_BASE, smrr); - smrr.lo = relo_attrs.smrr_mask; - smrr.hi = 0; - wrmsr(IA32_SMRR_PHYS_MASK, smrr); + wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); + wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase); smm_state->smbase = staggered_smbase; -- To view, visit https://review.coreboot.org/c/coreboot/+/34758 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4af661f68c158cbed591fe017d4bc25239bddd37 Gerrit-Change-Number: 34758 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: intel/fsp_baytrail: Use smm_subregion()
by Kyösti Mälkki (Code Review) 29 Aug '19

29 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34757 ) Change subject: intel/fsp_baytrail: Use smm_subregion() ...................................................................... intel/fsp_baytrail: Use smm_subregion() Change-Id: I4e9de9c7f5decd784d881e5a733e995522be5226 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/fsp_baytrail/cpu.c M src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c M src/soc/intel/fsp_baytrail/include/soc/smm.h M src/soc/intel/fsp_baytrail/memmap.c 4 files changed, 74 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/34757/1 diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c index 15dc851..0339bae 100644 --- a/src/soc/intel/fsp_baytrail/cpu.c +++ b/src/soc/intel/fsp_baytrail/cpu.c @@ -82,13 +82,12 @@ * MP and SMM loading initialization. */ -struct smm_relocation_attrs { - uint32_t smbase; - uint32_t smrr_base; - uint32_t smrr_mask; +struct smm_relocation_params { + msr_t smrr_base; + msr_t smrr_mask; }; -static struct smm_relocation_attrs relo_attrs; +static struct smm_relocation_params smm_reloc_params; static void pre_mp_init(void) { @@ -105,20 +104,32 @@ return pattrs->num_cpus; } -static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size) +static void fill_in_relocation_params(struct smm_relocation_params *params) { + uintptr_t tseg_base; + size_t tseg_size; + /* All range registers are aligned to 4KiB */ - const uint32_t rmask = ~((1 << 12) - 1); + const u32 rmask = ~(4 * KiB - 1); - /* Initialize global tracking state. */ - relo_attrs.smbase = (uint32_t)smm_region_start(); - relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK; - relo_attrs.smrr_mask = ~(smm_region_size() - 1) & rmask; - relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID; + smm_region(&tseg_base, &tseg_size); - *perm_smbase = relo_attrs.smbase; - *perm_smsize = smm_region_size() - CONFIG_SMM_RESERVED_SIZE; + /* SMRR has 32-bits of valid address aligned to 4KiB. */ + params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK; + params->smrr_base.hi = 0; + params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; + params->smrr_mask.hi = 0; +} + +static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, + size_t *smm_save_state_size) +{ + printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); + + fill_in_relocation_params(&smm_reloc_params); + + smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); + *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t); } @@ -133,16 +144,12 @@ static void relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase) { - msr_t smrr; + struct smm_relocation_params *relo_params = &smm_reloc_params; em64t100_smm_state_save_area_t *smm_state; /* Set up SMRR. */ - smrr.lo = relo_attrs.smrr_base; - smrr.hi = 0; - wrmsr(IA32_SMRR_PHYS_BASE, smrr); - smrr.lo = relo_attrs.smrr_mask; - smrr.hi = 0; - wrmsr(IA32_SMRR_PHYS_MASK, smrr); + wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); + wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase); smm_state->smbase = staggered_smbase; diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c index f11b206..65f1705 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -121,7 +121,7 @@ else if ((config->PcdeMMCBootMode != EMMC_USE_DEFAULT)) UpdData->PcdeMMCBootMode = config->PcdeMMCBootMode - EMMC_DISABLED; - UpdData->PcdMrcInitTsegSize = smm_region_size() >> 20; + UpdData->PcdMrcInitTsegSize = CONFIG_SMM_TSEG_SIZE >> 20; printk(FSP_INFO_LEVEL, "GTT Size:\t\t%d MB\n", UpdData->PcdGttSize); printk(FSP_INFO_LEVEL, "Tseg Size:\t\t%d MB\n", UpdData->PcdMrcInitTsegSize); diff --git a/src/soc/intel/fsp_baytrail/include/soc/smm.h b/src/soc/intel/fsp_baytrail/include/soc/smm.h index c929572..eb3158e 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/smm.h +++ b/src/soc/intel/fsp_baytrail/include/soc/smm.h @@ -17,19 +17,6 @@ #ifndef _BAYTRAIL_SMM_H_ #define _BAYTRAIL_SMM_H_ -/* There is a bug in the order of Kconfig includes in that arch/x86/Kconfig - * is included after chipset code. This causes the chipset's Kconfig to be - * clobbered by the arch/x86/Kconfig if they have the same name. */ -static inline int smm_region_size(void) -{ - /* Make it 8MiB by default. */ - if (CONFIG_SMM_TSEG_SIZE == 0) - return (8 << 20); - return CONFIG_SMM_TSEG_SIZE; -} - -uintptr_t smm_region_start(void); - #if !defined(__PRE_RAM__) && !defined(__SMM___) #include <stdint.h> void southcluster_smm_clear_state(void); diff --git a/src/soc/intel/fsp_baytrail/memmap.c b/src/soc/intel/fsp_baytrail/memmap.c index 77ba406..5e70e4e 100644 --- a/src/soc/intel/fsp_baytrail/memmap.c +++ b/src/soc/intel/fsp_baytrail/memmap.c @@ -15,13 +15,20 @@ */ #include <cbmem.h> +#include <cpu/x86/smm.h> #include <soc/iosf.h> #include <soc/smm.h> #include <drivers/intel/fsp1_0/fsp_util.h> +#include <types.h> -uintptr_t smm_region_start(void) +static uintptr_t smm_region_start(void) { - return (iosf_bunit_read(BUNIT_SMRRL) << 20); + return (iosf_bunit_read(BUNIT_SMRRL) & 0xFFFF) << 20; +} + +static size_t smm_region_size(void) +{ + return CONFIG_SMM_TSEG_SIZE; } /** @brief get the top of usable low memory from the FSP's HOB list @@ -38,3 +45,38 @@ { return find_fsp_reserved_mem(*(void **)CBMEM_FSP_HOB_PTR); } + +void smm_region(uintptr_t *start, size_t *size) +{ + *start = smm_region_start(); + *size = smm_region_size(); +} + +int smm_subregion(int sub, uintptr_t *start, size_t *size) +{ + uintptr_t sub_base; + size_t sub_size; + const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; + + smm_region(&sub_base, &sub_size); + + switch (sub) { + case SMM_SUBREGION_HANDLER: + /* Handler starts at the base of TSEG. */ + sub_size -= cache_size; + break; + case SMM_SUBREGION_CACHE: + /* External cache is in the middle of TSEG. */ + sub_base += sub_size - cache_size; + sub_size = cache_size; + break; + default: + *start = 0; + *size = 0; + return -1; + } + + *start = sub_base; + *size = sub_size; + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/34757 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e9de9c7f5decd784d881e5a733e995522be5226 Gerrit-Change-Number: 34757 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: google/rambi,intel/baytrail: Simplified romstage flow
by Kyösti Mälkki (Code Review) 29 Aug '19

29 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34964 ) Change subject: google/rambi,intel/baytrail: Simplified romstage flow ...................................................................... google/rambi,intel/baytrail: Simplified romstage flow Change-Id: I99440539d7b7586df66395776dcd0b4f72f66818 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/rambi/romstage.c M src/soc/intel/baytrail/include/soc/romstage.h M src/soc/intel/baytrail/romstage/Makefile.inc M src/soc/intel/baytrail/romstage/romstage.c 4 files changed, 19 insertions(+), 71 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/34964/1 diff --git a/src/mainboard/google/rambi/romstage.c b/src/mainboard/google/rambi/romstage.c index 9fbe1ca..f74d77d 100644 --- a/src/mainboard/google/rambi/romstage.c +++ b/src/mainboard/google/rambi/romstage.c @@ -55,21 +55,13 @@ return &spd_file_content[SPD_SIZE * ram_id]; } -void mainboard_romstage_entry_rp(struct romstage_params *rp) +void mainboard_fill_mrc_params(struct mrc_params *mp) { void *spd_content; int dual_channel = 0; void *spd_file; size_t spd_fsize; - struct mrc_params mp = { - .mainboard = { - .dram_type = DRAM_DDR3L, - .dram_info_location = DRAM_INFO_SPD_MEM, - .weaker_odt_settings = 1, - }, - }; - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, &spd_fsize); if (!spd_file) @@ -77,10 +69,12 @@ spd_content = get_spd_pointer(spd_file, spd_fsize / SPD_SIZE, &dual_channel); - mp.mainboard.dram_data[0] = spd_content; - if (dual_channel) - mp.mainboard.dram_data[1] = spd_content; - rp->mrc_params = &mp; - romstage_common(rp); + mp->mainboard.dram_type = DRAM_DDR3L; + mp->mainboard.dram_info_location = DRAM_INFO_SPD_MEM, + mp->mainboard.weaker_odt_settings = 1, + + mp->mainboard.dram_data[0] = spd_content; + if (dual_channel) + mp->mainboard.dram_data[1] = spd_content; } diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h index 305cf27..ea7a2a5 100644 --- a/src/soc/intel/baytrail/include/soc/romstage.h +++ b/src/soc/intel/baytrail/include/soc/romstage.h @@ -24,12 +24,7 @@ #include <arch/cpu.h> #include <soc/mrc_wrapper.h> -struct romstage_params { - struct mrc_params *mrc_params; -}; - -void mainboard_romstage_entry_rp(struct romstage_params *params); -void romstage_common(struct romstage_params *params); +void mainboard_fill_mrc_params(struct mrc_params *mp); void raminit(struct mrc_params *mp, int prev_sleep_state); void gfx_init(void); diff --git a/src/soc/intel/baytrail/romstage/Makefile.inc b/src/soc/intel/baytrail/romstage/Makefile.inc index d43a6fb..2effbb0 100644 --- a/src/soc/intel/baytrail/romstage/Makefile.inc +++ b/src/soc/intel/baytrail/romstage/Makefile.inc @@ -1,5 +1,7 @@ cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S cpu_incs-y += $(obj)/fmap_config.h + +romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += romstage.c romstage-y += raminit.c romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += uart.c diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 151956e..27ed58f 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -14,21 +14,16 @@ */ #include <stddef.h> -#include <arch/cpu.h> #include <arch/io.h> #include <arch/romstage.h> #include <device/mmio.h> #include <device/pci_ops.h> -#include <bootblock_common.h> #include <console/console.h> #include <cbmem.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/smm.h> #if CONFIG(EC_GOOGLE_CHROMEEC) #include <ec/google/chromeec/ec.h> #endif #include <elog.h> -#include <program_loading.h> #include <romstage_handoff.h> #include <string.h> #include <timestamp.h> @@ -155,28 +150,12 @@ return prev_sleep_state; } -/* The cache-as-ram assembly file calls romstage_main() after setting up - * cache-as-ram. romstage_main() will then call the mainboards's - * mainboard_romstage_entry() function. That function then calls - * romstage_common() below. The reason for the back and forth is to provide - * common entry point from cache-as-ram while still allowing for code sharing. - * Because we can't use global variables the stack is used for allocations -- - * thus the need to call back and forth. */ - -static struct postcar_frame early_mtrrs; - -/* Entry from cache-as-ram.inc. */ -static void romstage_main(uint64_t tsc) +/* Entry from cpu/intel/car/romstage.c */ +void mainboard_romstage_entry(void) { - struct romstage_params rp = { - .mrc_params = NULL, - }; - - /* Save initial timestamp from bootblock. */ - timestamp_init(tsc); - - /* Save romstage begin */ - timestamp_add_now(TS_START_ROMSTAGE); + struct chipset_power_state *ps; + int prev_sleep_state; + struct mrc_params mp; program_base_addresses(); @@ -194,21 +173,8 @@ gfx_init(); - /* Call into mainboard. */ - mainboard_romstage_entry_rp(&rp); - - if (CONFIG(SMM_TSEG)) - smm_list_regions(); - - prepare_and_run_postcar(&early_mtrrs); - /* We do not return here. */ -} - -/* Entry from the mainboard. */ -void romstage_common(struct romstage_params *params) -{ - struct chipset_power_state *ps; - int prev_sleep_state; + memset(&mp, 0, sizeof(mp)); + mainboard_fill_mrc_params(&mp); timestamp_add_now(TS_BEFORE_INITRAM); @@ -222,19 +188,10 @@ boot_count_increment(); #endif - /* Initialize RAM */ - raminit(params->mrc_params, prev_sleep_state); + raminit(&mp, prev_sleep_state); timestamp_add_now(TS_AFTER_INITRAM); romstage_handoff_init(prev_sleep_state == ACPI_S3); } - -/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK, - * keeping changes in cache_as_ram.S easy to manage. - */ -asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) -{ - romstage_main(base_timestamp); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/34964 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I99440539d7b7586df66395776dcd0b4f72f66818 Gerrit-Change-Number: 34964 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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