coreboot-gerrit August 2019

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Change in coreboot[master]: mb/google/hatch: Override DLL values for Kindred
by Jamie Chen (Code Review) 28 Aug '19

28 Aug '19

Jamie Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35041 ) Change subject: mb/google/hatch: Override DLL values for Kindred ...................................................................... mb/google/hatch: Override DLL values for Kindred New emmc DLL values for Kindred BUG=b:136784418 BRANCH=none TEST=Boot to OS 100 times on Kindred proto 1 board. Change-Id: I52acb445c47fcdb9b60512dd501d810b1ae4dc10 Signed-off-by: Jamie Chen <jamie.chen(a)intel.com> --- M src/mainboard/google/hatch/variants/kindred/variant.c 1 file changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35041/1 diff --git a/src/mainboard/google/hatch/variants/kindred/variant.c b/src/mainboard/google/hatch/variants/kindred/variant.c index 6cd017b..619d5fc 100644 --- a/src/mainboard/google/hatch/variants/kindred/variant.c +++ b/src/mainboard/google/hatch/variants/kindred/variant.c @@ -17,6 +17,7 @@ #include <chip.h> #include <soc/pci_devs.h> #include <ec/google/chromeec/ec.h> +#include <intelblocks/early_mmc.h> void variant_devtree_update(void) { @@ -47,3 +48,14 @@ cfg->satapwroptimize = 0; } } + +int mainboard_get_mmc_dll(struct mmc_dll_params *params) +{ + params->emmc_tx_data_cntl1 = 0x0F10; + params->emmc_tx_data_cntl2 = 0x1C2F2D2D; + params->emmc_rx_cmd_data_cntl1 = 0x1C121936; + params->emmc_rx_cmd_data_cntl2 = 0x1182D; + params->emmc_rx_strobe_cntl = 0x1414; ; + params->emmc_tx_cmd_cntl = 0x0505; + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/35041 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52acb445c47fcdb9b60512dd501d810b1ae4dc10 Gerrit-Change-Number: 35041 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Chen <jamie.chen(a)intel.com> Gerrit-MessageType: newchange

7 16

Change in coreboot[master]: Makefile: Move the .xcompile rule out of the if !NOCOMPILE block
by Raul Rangel (Code Review) 28 Aug '19

28 Aug '19

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34242 ) Change subject: Makefile: Move the .xcompile rule out of the if !NOCOMPILE block ...................................................................... Makefile: Move the .xcompile rule out of the if !NOCOMPILE block Generating the .xcompile file should be possible even without a config. BUG=b:112267918 TEST=Ran make and verified .xcompile was created Change-Id: I8075f71e6e3e2c150378818eeff2858c36b35843 Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> --- M Makefile 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/34242/1 diff --git a/Makefile b/Makefile index 45b0bc5..aaf43b4 100644 --- a/Makefile +++ b/Makefile @@ -129,6 +129,12 @@ endif endif +.xcompile: util/xcompile/xcompile + rm -f $@ + $< $(XGCCPATH) > $@.tmp + \mv -f $@.tmp $@ 2> /dev/null + rm -f $@.tmp + ifeq ($(NOCOMPILE),1) include $(TOPLEVEL)/Makefile.inc include $(TOPLEVEL)/payloads/Makefile.inc @@ -147,12 +153,6 @@ # to silence stupid warnings about a file that would be generated anyway. $(if $(wildcard .xcompile)$(NOCOMPILE),,$(eval $(shell util/xcompile/xcompile $(XGCCPATH) > .xcompile || rm -f .xcompile))) -.xcompile: util/xcompile/xcompile - rm -f $@ - $< $(XGCCPATH) > $@.tmp - \mv -f $@.tmp $@ 2> /dev/null - rm -f $@.tmp - -include .xcompile ifneq ($(XCOMPILE_COMPLETE),1) -- To view, visit https://review.coreboot.org/c/coreboot/+/34242 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8075f71e6e3e2c150378818eeff2858c36b35843 Gerrit-Change-Number: 34242 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: AUTHORS: Move src/arch/ppc64 copyrights into AUTHORS file
by Patrick Georgi (Code Review) 28 Aug '19

28 Aug '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34637 ) Change subject: AUTHORS: Move src/arch/ppc64 copyrights into AUTHORS file ...................................................................... AUTHORS: Move src/arch/ppc64 copyrights into AUTHORS file As discussed on the mailing list and voted upon, the coreboot project is going to move the majority of copyrights out of the headers and into an AUTHORS file. This will happen a bit at a time, as we'll be unifying license headers at the same time. Additional changes in this patch: - Move descriptions below the license header Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I51d5b1f01ff47ed752761116e3f32cb9e168584f Reviewed-on: https://review.coreboot.org/c/coreboot/+/34637 Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M AUTHORS M src/arch/ppc64/Makefile.inc M src/arch/ppc64/boot.c M src/arch/ppc64/bootblock.S M src/arch/ppc64/include/arch/cbconfig.h M src/arch/ppc64/include/arch/cpu.h M src/arch/ppc64/include/arch/early_variables.h M src/arch/ppc64/include/arch/header.ld M src/arch/ppc64/include/arch/memlayout.h M src/arch/ppc64/include/arch/stages.h M src/arch/ppc64/prologue.inc M src/arch/ppc64/rom_media.c M src/arch/ppc64/stages.c M src/arch/ppc64/tables.c 14 files changed, 6 insertions(+), 32 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Werner Zeh: Looks good to me, approved diff --git a/AUTHORS b/AUTHORS index 0881639..81f503a 100644 --- a/AUTHORS +++ b/AUTHORS @@ -25,7 +25,7 @@ MontaVista Software, Inc. Nick Barker Per Odlund -Raptor Engineering +Raptor Engineering, LLC. Richard Woodruff Ronald G. Minnich Russell King @@ -45,3 +45,5 @@ src/arch/arm src/arch/arm64 src/arch/mips +src/arch/ppc64 + diff --git a/src/arch/ppc64/Makefile.inc b/src/arch/ppc64/Makefile.inc index 99d8634..ac993d7 100644 --- a/src/arch/ppc64/Makefile.inc +++ b/src/arch/ppc64/Makefile.inc @@ -2,9 +2,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2016 Raptor Engineering, LLC -## Copyright (C) 2014 The ChromiumOS Authors -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. diff --git a/src/arch/ppc64/boot.c b/src/arch/ppc64/boot.c index 4da60b4..6c13761 100644 --- a/src/arch/ppc64/boot.c +++ b/src/arch/ppc64/boot.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/ppc64/bootblock.S b/src/arch/ppc64/bootblock.S index 77289a1..2628e0d 100644 --- a/src/arch/ppc64/bootblock.S +++ b/src/arch/ppc64/bootblock.S @@ -1,8 +1,5 @@ /* - * Early initialization code for POWER8. - * - * Copyright 2016 Raptor Engineering, LLC - * Copyright 2013 Google Inc. + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -13,6 +10,8 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the * GNU General Public License for more details. + * + * Early initialization code for POWER8. */ .section ".text._start", "ax", %progbits diff --git a/src/arch/ppc64/include/arch/cbconfig.h b/src/arch/ppc64/include/arch/cbconfig.h index 9467f52..35c1387 100644 --- a/src/arch/ppc64/include/arch/cbconfig.h +++ b/src/arch/ppc64/include/arch/cbconfig.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/ppc64/include/arch/cpu.h b/src/arch/ppc64/include/arch/cpu.h index 23bc9a1..8981690 100644 --- a/src/arch/ppc64/include/arch/cpu.h +++ b/src/arch/ppc64/include/arch/cpu.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2012 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/ppc64/include/arch/early_variables.h b/src/arch/ppc64/include/arch/early_variables.h index 99fc06b..22c3750 100644 --- a/src/arch/ppc64/include/arch/early_variables.h +++ b/src/arch/ppc64/include/arch/early_variables.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/ppc64/include/arch/header.ld b/src/arch/ppc64/include/arch/header.ld index 7fdc155..349fd51 100644 --- a/src/arch/ppc64/include/arch/header.ld +++ b/src/arch/ppc64/include/arch/header.ld @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/ppc64/include/arch/memlayout.h b/src/arch/ppc64/include/arch/memlayout.h index 4d2af59..09e87c9 100644 --- a/src/arch/ppc64/include/arch/memlayout.h +++ b/src/arch/ppc64/include/arch/memlayout.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/ppc64/include/arch/stages.h b/src/arch/ppc64/include/arch/stages.h index 90bd60b..a4939b1 100644 --- a/src/arch/ppc64/include/arch/stages.h +++ b/src/arch/ppc64/include/arch/stages.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 The ChromiumOS Authors - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/ppc64/prologue.inc b/src/arch/ppc64/prologue.inc index a349cf9..9e22eb3 100644 --- a/src/arch/ppc64/prologue.inc +++ b/src/arch/ppc64/prologue.inc @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2002 Eric Biederman - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/ppc64/rom_media.c b/src/arch/ppc64/rom_media.c index c171307..0fc8be2 100644 --- a/src/arch/ppc64/rom_media.c +++ b/src/arch/ppc64/rom_media.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/arch/ppc64/stages.c b/src/arch/ppc64/stages.c index 053fd76..3cc9371 100644 --- a/src/arch/ppc64/stages.c +++ b/src/arch/ppc64/stages.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/ppc64/tables.c b/src/arch/ppc64/tables.c index eef6bf2..e9de4bf 100644 --- a/src/arch/ppc64/tables.c +++ b/src/arch/ppc64/tables.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2003 Eric Biederman - * Copyright (C) 2005 Steve Magnani - * Copyright (C) 2008-2009 coresystems GmbH - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. -- To view, visit https://review.coreboot.org/c/coreboot/+/34637 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51d5b1f01ff47ed752761116e3f32cb9e168584f Gerrit-Change-Number: 34637 Gerrit-PatchSet: 3 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/drallion: remove GBE file
by EricR Lai (Code Review) 28 Aug '19

28 Aug '19

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35114 ) Change subject: mb/google/drallion: remove GBE file ...................................................................... mb/google/drallion: remove GBE file Drallion doesn't have on board LAN, remove GBE bin file config. BUG=b:139906731 TEST=emerge-drallion coreboot chromeos-bootimage and check image-drallion.bin not include GBE region Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ifbc295afd8d875b5098b0ce75252b51523a5c76e --- M src/mainboard/google/drallion/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/35114/1 diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig index 2484ce7..ffadd0c 100644 --- a/src/mainboard/google/drallion/Kconfig +++ b/src/mainboard/google/drallion/Kconfig @@ -21,7 +21,6 @@ select SYSTEM_TYPE_LAPTOP select TPM2 select MAINBOARD_USES_IFD_EC_REGION - select MAINBOARD_USES_IFD_GBE_REGION select USE_SAR select SAR_ENABLE -- To view, visit https://review.coreboot.org/c/coreboot/+/35114 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbc295afd8d875b5098b0ce75252b51523a5c76e Gerrit-Change-Number: 35114 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: mb/google/drallion: add dummy SPD file
by EricR Lai (Code Review) 28 Aug '19

28 Aug '19

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35113 ) Change subject: mb/google/drallion: add dummy SPD file ...................................................................... mb/google/drallion: add dummy SPD file Drallion will use solder down memory. Add dummy spd file. BUG=b:139397313 BRANCH=N/A TEST=Build and check cbfs has the dummy spd.bin Change-Id: Ife59c2dd689d72b117f30e832a3ce7eed4fa4220 Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> --- M src/mainboard/google/drallion/Kconfig M src/mainboard/google/drallion/Makefile.inc A src/mainboard/google/drallion/spd/Makefile.inc A src/mainboard/google/drallion/spd/empty_ddr4.spd.hex M src/mainboard/google/drallion/variants/arcada_cml/Makefile.inc M src/mainboard/google/drallion/variants/drallion/Makefile.inc M src/mainboard/google/drallion/variants/sarien_cml/Makefile.inc 7 files changed, 77 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/35113/1 diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig index cff56a4..2484ce7 100644 --- a/src/mainboard/google/drallion/Kconfig +++ b/src/mainboard/google/drallion/Kconfig @@ -8,7 +8,6 @@ select DRIVERS_SPI_ACPI select DRIVERS_USB_ACPI select EC_GOOGLE_WILCO - select GENERIC_SPD_BIN select GOOGLE_SMBIOS_MAINBOARD_VERSION select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES @@ -19,7 +18,6 @@ select SOC_INTEL_COMETLAKE select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SOC_INTEL_COMMON_BLOCK_SMM_ESPI_DISABLE - select SPD_READ_BY_WORD select SYSTEM_TYPE_LAPTOP select TPM2 select MAINBOARD_USES_IFD_EC_REGION diff --git a/src/mainboard/google/drallion/Makefile.inc b/src/mainboard/google/drallion/Makefile.inc index c16e7d2..e7c90bb 100644 --- a/src/mainboard/google/drallion/Makefile.inc +++ b/src/mainboard/google/drallion/Makefile.inc @@ -36,3 +36,5 @@ subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include + +subdirs-y += spd diff --git a/src/mainboard/google/drallion/spd/Makefile.inc b/src/mainboard/google/drallion/spd/Makefile.inc new file mode 100644 index 0000000..e35544b --- /dev/null +++ b/src/mainboard/google/drallion/spd/Makefile.inc @@ -0,0 +1,34 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_BIN = $(obj)/spd.bin + +ifeq ($(SPD_SOURCES),) + SPD_DEPS := $(error SPD_SOURCES is not set. Variant must provide this) +else + SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) +endif + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/drallion/spd/empty_ddr4.spd.hex b/src/mainboard/google/drallion/spd/empty_ddr4.spd.hex new file mode 100644 index 0000000..67b46cd --- /dev/null +++ b/src/mainboard/google/drallion/spd/empty_ddr4.spd.hex @@ -0,0 +1,32 @@ +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/drallion/variants/arcada_cml/Makefile.inc b/src/mainboard/google/drallion/variants/arcada_cml/Makefile.inc index 2bf028e..1cc010c 100644 --- a/src/mainboard/google/drallion/variants/arcada_cml/Makefile.inc +++ b/src/mainboard/google/drallion/variants/arcada_cml/Makefile.inc @@ -13,6 +13,9 @@ ## GNU General Public License for more details. ## +## GPP_F12-F16 indicates mem_id to match specific spd file +SPD_SOURCES = empty_ddr4 # 0b00000 + bootblock-y += gpio.c ramstage-y += gpio.c romstage-y += gpio.c diff --git a/src/mainboard/google/drallion/variants/drallion/Makefile.inc b/src/mainboard/google/drallion/variants/drallion/Makefile.inc index 2bf028e..0400d33 100644 --- a/src/mainboard/google/drallion/variants/drallion/Makefile.inc +++ b/src/mainboard/google/drallion/variants/drallion/Makefile.inc @@ -13,6 +13,9 @@ ## GNU General Public License for more details. ## +## GPP_F12-F16 indicates mem_id to match specific spd file +SPD_SOURCES = empty_ddr4 # 0b00000 + bootblock-y += gpio.c ramstage-y += gpio.c romstage-y += gpio.c diff --git a/src/mainboard/google/drallion/variants/sarien_cml/Makefile.inc b/src/mainboard/google/drallion/variants/sarien_cml/Makefile.inc index 2bf028e..1cc010c 100644 --- a/src/mainboard/google/drallion/variants/sarien_cml/Makefile.inc +++ b/src/mainboard/google/drallion/variants/sarien_cml/Makefile.inc @@ -13,6 +13,9 @@ ## GNU General Public License for more details. ## +## GPP_F12-F16 indicates mem_id to match specific spd file +SPD_SOURCES = empty_ddr4 # 0b00000 + bootblock-y += gpio.c ramstage-y += gpio.c romstage-y += gpio.c -- To view, visit https://review.coreboot.org/c/coreboot/+/35113 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife59c2dd689d72b117f30e832a3ce7eed4fa4220 Gerrit-Change-Number: 35113 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

5 11

Change in coreboot[master]: mb/google/poppy/variant/nami: add sku ids of bard/ekko
by Ren Kuo (Code Review) 28 Aug '19

28 Aug '19

Ren Kuo has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35115 ) Change subject: mb/google/poppy/variant/nami: add sku ids of bard/ekko ...................................................................... mb/google/poppy/variant/nami: add sku ids of bard/ekko add sku ids of bard/ekko BUG=b:139886622 TEST=emerge-nami coreboot Change-Id: Iabc3d587c3839e4a3121cea8504c50e2dc4f9699 Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> --- M 3rdparty/blobs M src/mainboard/google/poppy/variants/nami/gpio.c M src/mainboard/google/poppy/variants/nami/include/variant/sku.h M src/mainboard/google/poppy/variants/nami/mainboard.c 4 files changed, 31 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/35115/1 diff --git a/3rdparty/blobs b/3rdparty/blobs index 62aa0e0..402aa63 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit 62aa0e0c54295bbb7b1a3e5e73f960bafdb59d04 +Subproject commit 402aa63d4164a8580c7be7e0da445f4005e093ac diff --git a/src/mainboard/google/poppy/variants/nami/gpio.c b/src/mainboard/google/poppy/variants/nami/gpio.c index d0f6074..42f84f5 100644 --- a/src/mainboard/google/poppy/variants/nami/gpio.c +++ b/src/mainboard/google/poppy/variants/nami/gpio.c @@ -466,12 +466,18 @@ case SKU_1_EKKO: case SKU_2_EKKO: case SKU_3_EKKO: + case SKU_4_EKKO: + case SKU_5_EKKO: + case SKU_6_EKKO: + case SKU_7_EKKO: case SKU_0_BARD: case SKU_1_BARD: case SKU_2_BARD: case SKU_3_BARD: case SKU_4_BARD: case SKU_5_BARD: + case SKU_6_BARD: + case SKU_7_BARD: *num = ARRAY_SIZE(fpmcu_gpio_table); board_gpio_tables = fpmcu_gpio_table; break; diff --git a/src/mainboard/google/poppy/variants/nami/include/variant/sku.h b/src/mainboard/google/poppy/variants/nami/include/variant/sku.h index 63c8928..7ff3cc7 100644 --- a/src/mainboard/google/poppy/variants/nami/include/variant/sku.h +++ b/src/mainboard/google/poppy/variants/nami/include/variant/sku.h @@ -40,15 +40,21 @@ #define SKU_5_SYNDRA 0X6BC62 #define SKU_6_SYNDRA 0X6BC61 #define SKU_7_SYNDRA 0X6BC60 -#define SKU_0_EKKO 0x10118E3 -#define SKU_1_EKKO 0x10018E3 -#define SKU_2_EKKO 0x10118E1 -#define SKU_3_EKKO 0X10018E1 -#define SKU_0_BARD 0x1019CE3 -#define SKU_1_BARD 0x1009CE3 -#define SKU_2_BARD 0x1019CE1 -#define SKU_3_BARD 0X1009CE1 -#define SKU_4_BARD 0X1009CE0 -#define SKU_5_BARD 0X1009CE2 +#define SKU_0_EKKO 0x10118E3 +#define SKU_1_EKKO 0x10018E3 +#define SKU_2_EKKO 0x10118E1 +#define SKU_3_EKKO 0X10018E1 +#define SKU_4_EKKO 0x10118E2 +#define SKU_5_EKKO 0x10018E2 +#define SKU_6_EKKO 0x10118E0 +#define SKU_7_EKKO 0x10018E0 +#define SKU_0_BARD 0x1019CE3 +#define SKU_1_BARD 0x1009CE3 +#define SKU_2_BARD 0x1019CE1 +#define SKU_3_BARD 0X1009CE1 +#define SKU_4_BARD 0X1009CE0 +#define SKU_5_BARD 0X1009CE2 +#define SKU_6_BARD 0x1019CE0 +#define SKU_7_BARD 0x1019CE2 #endif /* __MAINBOARD_SKU_H__ */ diff --git a/src/mainboard/google/poppy/variants/nami/mainboard.c b/src/mainboard/google/poppy/variants/nami/mainboard.c index f63c520..e48a952 100644 --- a/src/mainboard/google/poppy/variants/nami/mainboard.c +++ b/src/mainboard/google/poppy/variants/nami/mainboard.c @@ -214,6 +214,8 @@ case SKU_3_BARD: case SKU_4_BARD: case SKU_5_BARD: + case SKU_6_BARD: + case SKU_7_BARD: return "vbt-bard.bin"; default: return "vbt.bin"; @@ -271,10 +273,16 @@ case SKU_3_BARD: case SKU_4_BARD: case SKU_5_BARD: + case SKU_6_BARD: + case SKU_7_BARD: case SKU_0_EKKO: case SKU_1_EKKO: case SKU_2_EKKO: case SKU_3_EKKO: + case SKU_4_EKKO: + case SKU_5_EKKO: + case SKU_6_EKKO: + case SKU_7_EKKO: pl2_id = PL2_ID_BARD_EKKO; cfg->usb2_ports[5].enable = 0; cfg->usb2_ports[7].enable = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/35115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabc3d587c3839e4a3121cea8504c50e2dc4f9699 Gerrit-Change-Number: 35115 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

5 6

Change in coreboot[master]: libpayload/usb: add USB 3.1 GEN2 support
by EricR Lai (Code Review) 28 Aug '19

28 Aug '19

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35023 ) Change subject: libpayload/usb: add USB 3.1 GEN2 support ...................................................................... libpayload/usb: add USB 3.1 GEN2 support USB 3.1 GEN2 report speed type 4, add into speed enum. BUG=b:139787920 BRANCH=N/A TEST=Build libpayload and depthcharge on sarien and boot with USB GEN2 HUB with USB disk. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ia0ef12b2f0d91bf0d0db766bbc9019de1614a4f4 --- M payloads/libpayload/drivers/usb/usb.c M payloads/libpayload/drivers/usb/usbhub.c M payloads/libpayload/drivers/usb/xhci_devconf.c M payloads/libpayload/include/usb/usb.h 4 files changed, 9 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35023/1 diff --git a/payloads/libpayload/drivers/usb/usb.c b/payloads/libpayload/drivers/usb/usb.c index 9c9854d..51b84f1 100644 --- a/payloads/libpayload/drivers/usb/usb.c +++ b/payloads/libpayload/drivers/usb/usb.c @@ -265,6 +265,7 @@ } return bMaxPacketSize0; case SUPER_SPEED: + case SUPER_SPEED_PLUS: if (bMaxPacketSize0 != 9) { usb_debug("Invalid MPS0: 0x%02x\n", bMaxPacketSize0); bMaxPacketSize0 = 9; @@ -284,6 +285,7 @@ case HIGH_SPEED: return 64; case SUPER_SPEED: + case SUPER_SPEED_PLUS: default: return 512; } @@ -319,6 +321,7 @@ return LOG2(bInterval); } case SUPER_SPEED: + case SUPER_SPEED_PLUS: switch (type) { case ISOCHRONOUS: case INTERRUPT: return bInterval - 1; diff --git a/payloads/libpayload/drivers/usb/usbhub.c b/payloads/libpayload/drivers/usb/usbhub.c index 340e47a..0482da8 100644 --- a/payloads/libpayload/drivers/usb/usbhub.c +++ b/payloads/libpayload/drivers/usb/usbhub.c @@ -98,6 +98,8 @@ /* SuperSpeed hubs can only have SuperSpeed devices. */ if (dev->speed == SUPER_SPEED) return SUPER_SPEED; + if (dev->speed == SUPER_SPEED_PLUS) + return SUPER_SPEED_PLUS; /*[bit] 10 9 (USB 2.0 port status word) * 0 0 full speed @@ -176,7 +178,7 @@ void usb_hub_init(usbdev_t *const dev) { - int type = dev->speed == SUPER_SPEED ? 0x2a : 0x29; /* similar enough */ + int type = dev->speed > SUPER_SPEED ? 0x2a : 0x29; /* similar enough */ hub_descriptor_t desc; /* won't fit the whole thing, we don't care */ if (get_descriptor(dev, gen_bmRequestType(device_to_host, class_type, dev_recp), type, 0, &desc, sizeof(desc)) != sizeof(desc)) { @@ -185,7 +187,7 @@ return; } - if (dev->speed == SUPER_SPEED) + if (dev->speed > SUPER_SPEED) usb_hub_set_hub_depth(dev); if (generic_hub_init(dev, desc.bNbrPorts, &usb_hub_ops) < 0) return; diff --git a/payloads/libpayload/drivers/usb/xhci_devconf.c b/payloads/libpayload/drivers/usb/xhci_devconf.c index 99e3037..b53c8ef 100644 --- a/payloads/libpayload/drivers/usb/xhci_devconf.c +++ b/payloads/libpayload/drivers/usb/xhci_devconf.c @@ -267,7 +267,7 @@ static int xhci_finish_hub_config(usbdev_t *const dev, inputctx_t *const ic) { - int type = dev->speed == SUPER_SPEED ? 0x2a : 0x29; /* similar enough */ + int type = dev->speed > SUPER_SPEED ? 0x2a : 0x29; /* similar enough */ hub_descriptor_t desc; if (get_descriptor(dev, gen_bmRequestType(device_to_host, class_type, diff --git a/payloads/libpayload/include/usb/usb.h b/payloads/libpayload/include/usb/usb.h index db7ec57..ee767ad 100644 --- a/payloads/libpayload/include/usb/usb.h +++ b/payloads/libpayload/include/usb/usb.h @@ -210,6 +210,7 @@ LOW_SPEED = 1, HIGH_SPEED = 2, SUPER_SPEED = 3, + SUPER_SPEED_PLUS = 4, } usb_speed; struct usbdev { -- To view, visit https://review.coreboot.org/c/coreboot/+/35023 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0ef12b2f0d91bf0d0db766bbc9019de1614a4f4 Gerrit-Change-Number: 35023 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

7 34

Change in coreboot[master]: nb/intel/x4x/raminit: Move dummy reads after JEDEC init
by Felix Held (Code Review) 28 Aug '19

28 Aug '19

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/20979 ) Change subject: nb/intel/x4x/raminit: Move dummy reads after JEDEC init ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/c/coreboot/+/20979/8/src/northbridge/intel/x4x/… File src/northbridge/intel/x4x/raminit_ddr23.c: https://review.coreboot.org/c/coreboot/+/20979/8/src/northbridge/intel/x4x/… PS8, Line 2163: (ch << 29) | (r * 0x08000000) > I wonder why this was lost when moving the code. […] FYI: I'm waiting for this to be addressed before I'll give this patch a +2 -- To view, visit https://review.coreboot.org/c/coreboot/+/20979 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8069f9c08ad5e5268ddbe3711d58bc42522f938c Gerrit-Change-Number: 20979 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 28 Aug 2019 01:17:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: util/sconfig: Expose usable PCI and PNP device names
by Felix Held (Code Review) 28 Aug '19

28 Aug '19

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31933 ) Change subject: util/sconfig: Expose usable PCI and PNP device names ...................................................................... Patch Set 6: Code-Review+1 (4 comments) looks good to me, but haven't looked closely enough into this to +2 it https://review.coreboot.org/c/coreboot/+/31933/3/util/sconfig/main.c File util/sconfig/main.c: https://review.coreboot.org/c/coreboot/+/31933/3/util/sconfig/main.c@847 PS3, Line 847: pass2 > maybe use a more descriptive name for the pass? Done https://review.coreboot.org/c/coreboot/+/31933/3/util/sconfig/main.c@852 PS3, Line 852: ptr->path_a, ptr->path_b > not related to this patch, but i find the struct element path_a and path_b very undescriptive this is out of the scope of this patch , but would imho still be a good idea https://review.coreboot.org/c/coreboot/+/31933/4/util/sconfig/main.c File util/sconfig/main.c: https://review.coreboot.org/c/coreboot/+/31933/4/util/sconfig/main.c@847 PS4, Line 847: pass2 > expose_device_names or something like that? Done https://review.coreboot.org/c/coreboot/+/31933/4/util/sconfig/main.c@1357 PS4, Line 1357: pass 2 > ditto? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/31933 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I711058f5c809fa9bc7ea4333aaebad6847ebdfd4 Gerrit-Change-Number: 31933 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 27 Aug 2019 22:22:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/hatch/variants/helios: Update DPTF parameters and TDP PL1/PL2
by Sumeet R Pawnikar (Code Review) 27 Aug '19

27 Aug '19

Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34743 ) Change subject: mb/google/hatch/variants/helios: Update DPTF parameters and TDP PL1/PL2 ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/34743/1/src/mainboard/google/hatch… File src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl: https://review.coreboot.org/c/coreboot/+/34743/1/src/mainboard/google/hatch… PS1, Line 37: 13000 How did you arrive to 13W for PowerLimitMaximum ? Shouldn't this to 15W ? -- To view, visit https://review.coreboot.org/c/coreboot/+/34743 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7a96c33ce710c32b57e2ad8066830ff83398c57 Gerrit-Change-Number: 34743 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 27 Aug 2019 17:48:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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