coreboot-gerrit August 2019

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Change in coreboot[master]: emulation/qemu-x86: Use common romstage code
by Kyösti Mälkki (Code Review) 26 Aug '19

26 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34973 ) Change subject: emulation/qemu-x86: Use common romstage code ...................................................................... emulation/qemu-x86: Use common romstage code This provides stack guards with checking and common entry into postcar. Change-Id: If0729721f0165187946107eb98e8bc754f28e517 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/qemu-x86/Makefile.inc M src/mainboard/emulation/qemu-i440fx/memory.c M src/mainboard/emulation/qemu-i440fx/romstage.c M src/mainboard/emulation/qemu-q35/romstage.c 4 files changed, 12 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/34973/1 diff --git a/src/cpu/qemu-x86/Makefile.inc b/src/cpu/qemu-x86/Makefile.inc index 8ddaa81..6278f1b 100644 --- a/src/cpu/qemu-x86/Makefile.inc +++ b/src/cpu/qemu-x86/Makefile.inc @@ -14,7 +14,11 @@ bootblock-y += cache_as_ram_bootblock.S bootblock-y += bootblock.c + +romstage-y += ../intel/car/romstage.c + ramstage-y += qemu.c + subdirs-y += ../x86/mtrr subdirs-y += ../x86/lapic subdirs-y += ../x86/smm diff --git a/src/mainboard/emulation/qemu-i440fx/memory.c b/src/mainboard/emulation/qemu-i440fx/memory.c index aa1ceba..8209379 100644 --- a/src/mainboard/emulation/qemu-i440fx/memory.c +++ b/src/mainboard/emulation/qemu-i440fx/memory.c @@ -15,6 +15,7 @@ #include <cbmem.h> #include <arch/io.h> +#include <arch/romstage.h> #include "memory.h" #include "fw_cfg.h" @@ -61,3 +62,8 @@ return (void *)top; } + +/* Nothing to do, MTRRs are no-op on QEMU. */ +void fill_postcar_frame(struct postcar_frame *pcf) +{ +} diff --git a/src/mainboard/emulation/qemu-i440fx/romstage.c b/src/mainboard/emulation/qemu-i440fx/romstage.c index 32eab3d..8e5691f 100644 --- a/src/mainboard/emulation/qemu-i440fx/romstage.c +++ b/src/mainboard/emulation/qemu-i440fx/romstage.c @@ -14,31 +14,10 @@ * GNU General Public License for more details. */ -#include <arch/cpu.h> #include <arch/romstage.h> -#include <stdint.h> #include <cbmem.h> -#include <console/console.h> -#include <timestamp.h> -#include <program_loading.h> -asmlinkage void car_stage_entry(void) +void mainboard_romstage_entry(void) { - struct postcar_frame pcf; - - console_init(); - cbmem_recovery(0); - - timestamp_add_now(TS_START_ROMSTAGE); - - if (postcar_frame_init(&pcf, 0)) - die("Unable to initialize postcar frame.\n"); - - /** - * Run postcar to tear down CAR and load relocatable ramstage. - * There's no CAR on qemu, but for educational purposes and - * testing the postcar stage is used on qemu, too. - */ - run_postcar_phase(&pcf); } diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c index 6cd9ee4..b7fdac2 100644 --- a/src/mainboard/emulation/qemu-q35/romstage.c +++ b/src/mainboard/emulation/qemu-q35/romstage.c @@ -14,14 +14,10 @@ * GNU General Public License for more details. */ -#include <arch/cpu.h> #include <arch/romstage.h> -#include <stdint.h> #include <cbmem.h> #include <console/console.h> -#include <timestamp.h> #include <southbridge/intel/i82801ix/i82801ix.h> -#include <program_loading.h> #include <device/pci_ops.h> #define D0F0_PCIEXBAR_LO 0x60 @@ -35,26 +31,11 @@ die("You must run qemu for machine Q35 (-M q35)"); } -asmlinkage void car_stage_entry(void) +void mainboard_romstage_entry(void) { - struct postcar_frame pcf; i82801ix_early_init(); - console_init(); mainboard_machine_check(); cbmem_recovery(0); - - timestamp_add_now(TS_START_ROMSTAGE); - - if (postcar_frame_init(&pcf, 0)) - die("Unable to initialize postcar frame.\n"); - - /** - * Run postcar to tear down CAR and load relocatable ramstage. - * There's no CAR on qemu, but for educational purposes and - * testing the postcar stage is used on qemu, too. - */ - - run_postcar_phase(&pcf); } -- To view, visit https://review.coreboot.org/c/coreboot/+/34973 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0729721f0165187946107eb98e8bc754f28e517 Gerrit-Change-Number: 34973 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: lib/bootblock: Add simplified entry with basetime
by Kyösti Mälkki (Code Review) 26 Aug '19

26 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34972 ) Change subject: lib/bootblock: Add simplified entry with basetime ...................................................................... lib/bootblock: Add simplified entry with basetime This allows for minor optimization as num_timestamps becomes a constant zero for a function with local scope. The loop with calls to timestamp_add() gets removed from bootblock. Change-Id: Id230075c0e76fe377b6ea8c8ddf8318e07d29b91 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/car/bootblock.c M src/cpu/qemu-x86/bootblock.c M src/include/bootblock_common.h M src/lib/bootblock.c M src/soc/intel/apollolake/bootblock/bootblock.c M src/soc/intel/braswell/bootblock/bootblock.c M src/soc/intel/cannonlake/bootblock/bootblock.c M src/soc/intel/denverton_ns/bootblock/bootblock.c M src/soc/intel/icelake/bootblock/bootblock.c M src/soc/intel/quark/bootblock/bootblock.c M src/soc/intel/skylake/bootblock/bootblock.c 11 files changed, 19 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/34972/1 diff --git a/src/cpu/intel/car/bootblock.c b/src/cpu/intel/car/bootblock.c index d751d86..664c2b5 100644 --- a/src/cpu/intel/car/bootblock.c +++ b/src/cpu/intel/car/bootblock.c @@ -21,7 +21,7 @@ { saved_bist = bist; /* Call lib/bootblock.c main */ - bootblock_main_with_timestamp(base_timestamp, NULL, 0); + bootblock_main_with_basetime(base_timestamp); } void __weak bootblock_early_northbridge_init(void) { } diff --git a/src/cpu/qemu-x86/bootblock.c b/src/cpu/qemu-x86/bootblock.c index 8dcf576..6459beb 100644 --- a/src/cpu/qemu-x86/bootblock.c +++ b/src/cpu/qemu-x86/bootblock.c @@ -29,5 +29,5 @@ } /* Call lib/bootblock.c main */ - bootblock_main_with_timestamp(base_timestamp, NULL, 0); + bootblock_main_with_basetime(base_timestamp); } diff --git a/src/include/bootblock_common.h b/src/include/bootblock_common.h index 08b2b7a..da10307 100644 --- a/src/include/bootblock_common.h +++ b/src/include/bootblock_common.h @@ -46,8 +46,12 @@ * entered from C code. This function assumes that the timer has already been * initialized, so it does not call init_timer(). */ +#if 0 asmlinkage void bootblock_main_with_timestamp(uint64_t base_timestamp, struct timestamp_entry *timestamps, size_t num_timestamps); +#endif + +void bootblock_main_with_basetime(uint64_t base_timestamp); /* This is the argument structure passed from decompressor to bootblock. */ struct bootblock_arg { diff --git a/src/lib/bootblock.c b/src/lib/bootblock.c index 3925e90a..7fd70f2 100644 --- a/src/lib/bootblock.c +++ b/src/lib/bootblock.c @@ -30,7 +30,7 @@ __weak void bootblock_soc_init(void) { /* do nothing */ } __weak void bootblock_mainboard_init(void) { /* do nothing */ } -asmlinkage void bootblock_main_with_timestamp(uint64_t base_timestamp, +static void bootblock_main_with_timestamp(uint64_t base_timestamp, struct timestamp_entry *timestamps, size_t num_timestamps) { /* Initialize timestamps if we have TIMESTAMP region in memlayout.ld. */ @@ -60,6 +60,11 @@ run_romstage(); } +void bootblock_main_with_basetime(uint64_t base_timestamp) +{ + bootblock_main_with_timestamp(base_timestamp, NULL, 0); +} + void main(void) { uint64_t base_timestamp = 0; diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index f86c18e..a07c462 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -69,7 +69,7 @@ enable_rtc_upper_bank(); /* Call lib/bootblock.c main */ - bootblock_main_with_timestamp(base_timestamp, NULL, 0); + bootblock_main_with_basetime(base_timestamp); } static void enable_pmcbar(void) diff --git a/src/soc/intel/braswell/bootblock/bootblock.c b/src/soc/intel/braswell/bootblock/bootblock.c index 2d1a3e8..d8d953c 100644 --- a/src/soc/intel/braswell/bootblock/bootblock.c +++ b/src/soc/intel/braswell/bootblock/bootblock.c @@ -31,7 +31,7 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { /* Call lib/bootblock.c main */ - bootblock_main_with_timestamp(base_timestamp, NULL, 0); + bootblock_main_with_basetime(base_timestamp); } static void program_base_addresses(void) diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c index 30c2266..653ba30 100644 --- a/src/soc/intel/cannonlake/bootblock/bootblock.c +++ b/src/soc/intel/cannonlake/bootblock/bootblock.c @@ -44,7 +44,7 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { /* Call lib/bootblock.c main */ - bootblock_main_with_timestamp(base_timestamp, NULL, 0); + bootblock_main_with_basetime(base_timestamp); } void bootblock_soc_early_init(void) diff --git a/src/soc/intel/denverton_ns/bootblock/bootblock.c b/src/soc/intel/denverton_ns/bootblock/bootblock.c index e9800c8..f75de1f 100644 --- a/src/soc/intel/denverton_ns/bootblock/bootblock.c +++ b/src/soc/intel/denverton_ns/bootblock/bootblock.c @@ -51,7 +51,7 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { /* Call lib/bootblock.c main */ - bootblock_main_with_timestamp(base_timestamp, NULL, 0); + bootblock_main_with_basetime(base_timestamp); }; void bootblock_soc_early_init(void) diff --git a/src/soc/intel/icelake/bootblock/bootblock.c b/src/soc/intel/icelake/bootblock/bootblock.c index b76dc4b..db43e50 100644 --- a/src/soc/intel/icelake/bootblock/bootblock.c +++ b/src/soc/intel/icelake/bootblock/bootblock.c @@ -23,7 +23,7 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { /* Call lib/bootblock.c main */ - bootblock_main_with_timestamp(base_timestamp, NULL, 0); + bootblock_main_with_basetime(base_timestamp); } void bootblock_soc_early_init(void) diff --git a/src/soc/intel/quark/bootblock/bootblock.c b/src/soc/intel/quark/bootblock/bootblock.c index ff5b9b2..2b2fc29 100644 --- a/src/soc/intel/quark/bootblock/bootblock.c +++ b/src/soc/intel/quark/bootblock/bootblock.c @@ -82,7 +82,7 @@ if (CONFIG(ENABLE_DEBUG_LED_BOOTBLOCK_ENTRY)) light_sd_led(); - bootblock_main_with_timestamp(base_timestamp, NULL, 0); + bootblock_main_with_basetime(base_timestamp); } void bootblock_soc_early_init(void) diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c index 4358fba..e9ca2d8 100644 --- a/src/soc/intel/skylake/bootblock/bootblock.c +++ b/src/soc/intel/skylake/bootblock/bootblock.c @@ -22,7 +22,7 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { /* Call lib/bootblock.c main */ - bootblock_main_with_timestamp(base_timestamp, NULL, 0); + bootblock_main_with_basetime(base_timestamp); } void bootblock_soc_early_init(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/34972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id230075c0e76fe377b6ea8c8ddf8318e07d29b91 Gerrit-Change-Number: 34972 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

2 9

Change in coreboot[master]: samusung/exynos: Use ENV_BEFORE_RAMSTAGE
by Kyösti Mälkki (Code Review) 26 Aug '19

26 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34982 ) Change subject: samusung/exynos: Use ENV_BEFORE_RAMSTAGE ...................................................................... samusung/exynos: Use ENV_BEFORE_RAMSTAGE Change-Id: I9dbf0fc14516f766fd164c7308906456f2865e89 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/samsung/exynos5250/alternate_cbfs.c M src/soc/samsung/exynos5420/alternate_cbfs.c 2 files changed, 16 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/34982/1 diff --git a/src/soc/samsung/exynos5250/alternate_cbfs.c b/src/soc/samsung/exynos5250/alternate_cbfs.c index e431672..90b1a7d 100644 --- a/src/soc/samsung/exynos5250/alternate_cbfs.c +++ b/src/soc/samsung/exynos5250/alternate_cbfs.c @@ -35,12 +35,14 @@ * should contain all available stages/payloads/etc. It is loaded when this * function is called a second time at the end of the romstage, and copied to * the romstage/ramstage CBFS cache in DRAM. It will reside there for the - * rest of the firmware's lifetime and all subsequent stages (which will not - * have __PRE_RAM__ defined) can just directly reference it there. + * rest of the firmware's lifetime and all subsequent stages can just directly + * reference it there. */ static int usb_cbfs_open(void) { -#ifdef __PRE_RAM__ + if (!ENV_BEFORE_RAMSTAGE) + return 0; + static int first_run = 1; int (*irom_load_usb)(void) = *irom_load_image_from_usb_ptr; @@ -61,7 +63,6 @@ printk(BIOS_DEBUG, "USB A-A transfer successful, CBFS image should now" " be at %p\n", _cbfs_cache); first_run = 0; -#endif return 0; } @@ -75,7 +76,9 @@ */ static int sdmmc_cbfs_open(void) { -#ifdef __PRE_RAM__ + if (!ENV_BEFORE_RAMSTAGE) + return 0; + /* * In the bootblock, we just copy the small part that fits in the buffer * and hope that it's enough (since the romstage is currently always the @@ -100,7 +103,6 @@ printk(BIOS_DEBUG, "SDMMC read successful, CBFS image should now be" " at %p\n", _cbfs_cache); first_run = 0; -#endif return 0; } diff --git a/src/soc/samsung/exynos5420/alternate_cbfs.c b/src/soc/samsung/exynos5420/alternate_cbfs.c index ba3f9a3..90d7756 100644 --- a/src/soc/samsung/exynos5420/alternate_cbfs.c +++ b/src/soc/samsung/exynos5420/alternate_cbfs.c @@ -36,12 +36,14 @@ * should contain all available stages/payloads/etc. It is loaded when this * function is called a second time at the end of the romstage, and copied to * the romstage/ramstage CBFS cache in DRAM. It will reside there for the - * rest of the firmware's lifetime and all subsequent stages (which will not - * have __PRE_RAM__ defined) can just directly reference it there. + * rest of the firmware's lifetime and all subsequent stages can just directly + * reference it there. */ static int usb_cbfs_open(void) { -#ifdef __PRE_RAM__ + if (!ENV_BEFORE_RAMSTAGE) + return 0; + static int first_run = 1; int (*irom_load_usb)(void) = *irom_load_image_from_usb_ptr; @@ -65,7 +67,6 @@ printk(BIOS_DEBUG, "USB A-A transfer successful, CBFS image should now" " be at %p\n", _cbfs_cache); first_run = 0; -#endif return 0; } @@ -79,7 +80,9 @@ */ static int sdmmc_cbfs_open(void) { -#ifdef __PRE_RAM__ + if (!ENV_BEFORE_RAMSTAGE) + return 0; + /* * In the bootblock, we just copy the small part that fits in the buffer * and hope that it's enough (since the romstage is currently always the @@ -107,7 +110,6 @@ printk(BIOS_DEBUG, "SDMMC read successful, CBFS image should now be" " at %p\n", _cbfs_cache); first_run = 0; -#endif return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/34982 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9dbf0fc14516f766fd164c7308906456f2865e89 Gerrit-Change-Number: 34982 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: Add ENV_BEFORE_RAMSTAGE
by Kyösti Mälkki (Code Review) 26 Aug '19

26 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34939 ) Change subject: Add ENV_BEFORE_RAMSTAGE ...................................................................... Add ENV_BEFORE_RAMSTAGE Change-Id: Ibd2292f922ccb9e79d10ca9bc35797048d174287 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/riscv/include/arch/memlayout.h M src/include/rules.h M src/soc/samsung/exynos5250/alternate_cbfs.c M src/soc/samsung/exynos5420/alternate_cbfs.c 4 files changed, 11 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/34939/1 diff --git a/src/arch/riscv/include/arch/memlayout.h b/src/arch/riscv/include/arch/memlayout.h index 7baab76..ebedb2d 100644 --- a/src/arch/riscv/include/arch/memlayout.h +++ b/src/arch/riscv/include/arch/memlayout.h @@ -20,7 +20,7 @@ #define STACK(addr, size) REGION(stack, addr, size, 4096) -#if defined(__PRE_RAM__) +#if ENV_BEFORE_RAMSTAGE #define CAR_STACK(addr, size) \ REGION(car_stack, addr, size, 4K) \ ALIAS_REGION(car_stack, stack) diff --git a/src/include/rules.h b/src/include/rules.h index 10cd715..530404d 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -266,6 +266,8 @@ #define ENV_PAYLOAD_LOADER ENV_RAMSTAGE #endif +#define ENV_BEFORE_RAMSTAGE (ENV_BOOTBLOCK || ENV_VERSTAGE || ENV_ROMSTAGE || ENV_POSTCAR) + /** * For pre-DRAM stages and post-CAR always build with simple device model, ie. * PCI, PNP and CPU functions operate without use of devicetree. The reason diff --git a/src/soc/samsung/exynos5250/alternate_cbfs.c b/src/soc/samsung/exynos5250/alternate_cbfs.c index e431672..a012837 100644 --- a/src/soc/samsung/exynos5250/alternate_cbfs.c +++ b/src/soc/samsung/exynos5250/alternate_cbfs.c @@ -35,12 +35,12 @@ * should contain all available stages/payloads/etc. It is loaded when this * function is called a second time at the end of the romstage, and copied to * the romstage/ramstage CBFS cache in DRAM. It will reside there for the - * rest of the firmware's lifetime and all subsequent stages (which will not - * have __PRE_RAM__ defined) can just directly reference it there. + * rest of the firmware's lifetime and all subsequent stages can just directly + * reference it there. */ static int usb_cbfs_open(void) { -#ifdef __PRE_RAM__ +#if ENV_BEFORE_RAMSTAGE static int first_run = 1; int (*irom_load_usb)(void) = *irom_load_image_from_usb_ptr; @@ -75,7 +75,7 @@ */ static int sdmmc_cbfs_open(void) { -#ifdef __PRE_RAM__ +#if ENV_BEFORE_RAMSTAGE /* * In the bootblock, we just copy the small part that fits in the buffer * and hope that it's enough (since the romstage is currently always the diff --git a/src/soc/samsung/exynos5420/alternate_cbfs.c b/src/soc/samsung/exynos5420/alternate_cbfs.c index ba3f9a3..b8f3e04 100644 --- a/src/soc/samsung/exynos5420/alternate_cbfs.c +++ b/src/soc/samsung/exynos5420/alternate_cbfs.c @@ -36,12 +36,12 @@ * should contain all available stages/payloads/etc. It is loaded when this * function is called a second time at the end of the romstage, and copied to * the romstage/ramstage CBFS cache in DRAM. It will reside there for the - * rest of the firmware's lifetime and all subsequent stages (which will not - * have __PRE_RAM__ defined) can just directly reference it there. + * rest of the firmware's lifetime and all subsequent stages can just directly + * reference it there. */ static int usb_cbfs_open(void) { -#ifdef __PRE_RAM__ +#if ENV_BEFORE_RAMSTAGE static int first_run = 1; int (*irom_load_usb)(void) = *irom_load_image_from_usb_ptr; @@ -79,7 +79,7 @@ */ static int sdmmc_cbfs_open(void) { -#ifdef __PRE_RAM__ +#if ENV_BEFORE_RAMSTAGE /* * In the bootblock, we just copy the small part that fits in the buffer * and hope that it's enough (since the romstage is currently always the -- To view, visit https://review.coreboot.org/c/coreboot/+/34939 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd2292f922ccb9e79d10ca9bc35797048d174287 Gerrit-Change-Number: 34939 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newchange

4 31

Change in coreboot[master]: Split MAYBE_STATIC to _BSS and _NONZERO variants
by Kyösti Mälkki (Code Review) 26 Aug '19

26 Aug '19

Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/35003 ) Change subject: Split MAYBE_STATIC to _BSS and _NONZERO variants ...................................................................... Split MAYBE_STATIC to _BSS and _NONZERO variants These are required to cover the absensce of .data and .bss sections in some programs, most notably ARCH_X86 in execute-in-place with cache-as-ram. Change-Id: I80485ebac94b88c5864a949b17ad1dccdfda6a40 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35003 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/device/device_const.c M src/ec/google/chromeec/ec_boardid.c M src/ec/google/chromeec/ec_lpc.c M src/ec/google/wilco/boardid.c M src/include/stddef.h M src/lib/lzma.c M src/lib/timestamp.c M src/mainboard/google/stout/chromeos.c M src/mainboard/intel/glkrvp/boardid.c M src/mainboard/intel/glkrvp/variants/baseboard/boardid.c M src/mainboard/intel/icelake_rvp/board_id.c M src/mainboard/intel/kblrvp/board_id.c M src/security/tpm/tspi/log.c M src/soc/intel/baytrail/northcluster.c M src/soc/intel/braswell/northcluster.c M toolchain.inc 16 files changed, 26 insertions(+), 21 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/device/device_const.c b/src/device/device_const.c index c472aea..0712d0c 100644 --- a/src/device/device_const.c +++ b/src/device/device_const.c @@ -204,7 +204,7 @@ DEVTREE_CONST struct bus *pci_root_bus(void) { DEVTREE_CONST struct device *pci_domain; - MAYBE_STATIC DEVTREE_CONST struct bus *pci_root = NULL; + MAYBE_STATIC_BSS DEVTREE_CONST struct bus *pci_root = NULL; if (pci_root) return pci_root; diff --git a/src/ec/google/chromeec/ec_boardid.c b/src/ec/google/chromeec/ec_boardid.c index 01e3c90..1307ce1 100644 --- a/src/ec/google/chromeec/ec_boardid.c +++ b/src/ec/google/chromeec/ec_boardid.c @@ -18,7 +18,7 @@ uint32_t board_id(void) { - MAYBE_STATIC uint32_t id = BOARD_ID_INIT; + MAYBE_STATIC_NONZERO uint32_t id = BOARD_ID_INIT; if (id == BOARD_ID_INIT) { if (google_chromeec_get_board_version(&id)) diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index feea9dd..1d7e7ee 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -401,7 +401,7 @@ int google_chromeec_command(struct chromeec_command *cec_command) { - MAYBE_STATIC int command_version = 0; + MAYBE_STATIC_BSS int command_version = 0; if (command_version <= 0) command_version = google_chromeec_command_version(); diff --git a/src/ec/google/wilco/boardid.c b/src/ec/google/wilco/boardid.c index e602e6e..2a7e575 100644 --- a/src/ec/google/wilco/boardid.c +++ b/src/ec/google/wilco/boardid.c @@ -18,7 +18,7 @@ uint32_t board_id(void) { - MAYBE_STATIC uint32_t id = BOARD_ID_INIT; + MAYBE_STATIC_NONZERO uint32_t id = BOARD_ID_INIT; if (id == BOARD_ID_INIT) { uint8_t ec_id; diff --git a/src/include/stddef.h b/src/include/stddef.h index 7cae2e6..a2c9c50 100644 --- a/src/include/stddef.h +++ b/src/include/stddef.h @@ -35,11 +35,16 @@ #define DEVTREE_CONST #endif -/* Work around non-writable data segment in execute-in-place romstage on x86. */ -#if defined(__PRE_RAM__) && CONFIG(ARCH_X86) -#define MAYBE_STATIC +#if ENV_STAGE_HAS_DATA_SECTION +#define MAYBE_STATIC_NONZERO static #else -#define MAYBE_STATIC static +#define MAYBE_STATIC_NONZERO +#endif + +#if ENV_STAGE_HAS_BSS_SECTION +#define MAYBE_STATIC_BSS static +#else +#define MAYBE_STATIC_BSS #endif #ifndef __ROMCC__ diff --git a/src/lib/lzma.c b/src/lib/lzma.c index eecbb26..71c016e 100644 --- a/src/lib/lzma.c +++ b/src/lib/lzma.c @@ -26,7 +26,7 @@ int res; CLzmaDecoderState state; SizeT mallocneeds; - MAYBE_STATIC unsigned char scratchpad[15980]; + MAYBE_STATIC_BSS unsigned char scratchpad[15980]; const unsigned char *cp; memcpy(properties, src, LZMA_PROPERTIES_SIZE); diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index 1319b86..89152fd 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -128,7 +128,7 @@ static struct timestamp_table *timestamp_table_get(void) { - MAYBE_STATIC struct timestamp_table *ts_table = NULL; + MAYBE_STATIC_BSS struct timestamp_table *ts_table = NULL; struct timestamp_cache *ts_cache; if (ts_table != NULL) diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index 44784b4..0914450 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -71,8 +71,8 @@ */ int get_recovery_mode_switch(void) { - MAYBE_STATIC int ec_in_rec_mode = 0; - MAYBE_STATIC int ec_rec_flag_good = 0; + MAYBE_STATIC_BSS int ec_in_rec_mode = 0; + MAYBE_STATIC_BSS int ec_rec_flag_good = 0; if (ec_rec_flag_good) return ec_in_rec_mode; diff --git a/src/mainboard/intel/glkrvp/boardid.c b/src/mainboard/intel/glkrvp/boardid.c index 0676eac..1a7b3e3 100644 --- a/src/mainboard/intel/glkrvp/boardid.c +++ b/src/mainboard/intel/glkrvp/boardid.c @@ -25,7 +25,7 @@ uint32_t board_id(void) { - MAYBE_STATIC int id = -1; + MAYBE_STATIC_NONZERO int id = -1; if (id < 0) { if (CONFIG(EC_GOOGLE_CHROMEEC)) id = variant_board_id(); diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c b/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c index 69a0a91..89a736f 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c +++ b/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c @@ -19,7 +19,7 @@ int variant_board_id(void) { - MAYBE_STATIC uint32_t id = BOARD_ID_INIT; + MAYBE_STATIC_NONZERO uint32_t id = BOARD_ID_INIT; if (CONFIG(EC_GOOGLE_CHROMEEC)) { if (id == BOARD_ID_INIT) { diff --git a/src/mainboard/intel/icelake_rvp/board_id.c b/src/mainboard/intel/icelake_rvp/board_id.c index b56f047..c0def22 100644 --- a/src/mainboard/intel/icelake_rvp/board_id.c +++ b/src/mainboard/intel/icelake_rvp/board_id.c @@ -31,7 +31,7 @@ /* Get Board ID via EC I/O port write/read */ int get_board_id(void) { - MAYBE_STATIC int id = -1; + MAYBE_STATIC_NONZERO int id = -1; if (id < 0) { if (CONFIG(EC_GOOGLE_CHROMEEC)) diff --git a/src/mainboard/intel/kblrvp/board_id.c b/src/mainboard/intel/kblrvp/board_id.c index a978e0f..dc5afcf 100644 --- a/src/mainboard/intel/kblrvp/board_id.c +++ b/src/mainboard/intel/kblrvp/board_id.c @@ -22,7 +22,7 @@ */ int get_ec_boardinfo(void) { - MAYBE_STATIC int ec_info = -1; + MAYBE_STATIC_NONZERO int ec_info = -1; if (ec_info < 0) { uint8_t buffer[2]; uint8_t index; diff --git a/src/security/tpm/tspi/log.c b/src/security/tpm/tspi/log.c index 4019962..99e6a43 100644 --- a/src/security/tpm/tspi/log.c +++ b/src/security/tpm/tspi/log.c @@ -26,7 +26,7 @@ static struct tcpa_table *tcpa_cbmem_init(void) { - MAYBE_STATIC struct tcpa_table *tclt = NULL; + MAYBE_STATIC_BSS struct tcpa_table *tclt = NULL; if (tclt) return tclt; @@ -47,7 +47,7 @@ static struct tcpa_table *tcpa_log_init(void) { - MAYBE_STATIC struct tcpa_table *tclt = NULL; + MAYBE_STATIC_BSS struct tcpa_table *tclt = NULL; /* We are dealing here with pre CBMEM environment. * If cbmem isn't available use CAR or SRAM */ diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c index 5f33c86..654d237 100644 --- a/src/soc/intel/baytrail/northcluster.c +++ b/src/soc/intel/baytrail/northcluster.c @@ -64,7 +64,7 @@ uint32_t nc_read_top_of_low_memory(void) { - MAYBE_STATIC uint32_t tolm = 0; + MAYBE_STATIC_BSS uint32_t tolm = 0; if (tolm) return tolm; diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c index 8a5f02e..e3e3aa7 100644 --- a/src/soc/intel/braswell/northcluster.c +++ b/src/soc/intel/braswell/northcluster.c @@ -71,7 +71,7 @@ uint32_t nc_read_top_of_low_memory(void) { - MAYBE_STATIC uint32_t tolm = 0; + MAYBE_STATIC_BSS uint32_t tolm = 0; if (tolm) return tolm; diff --git a/toolchain.inc b/toolchain.inc index 875cb20..4c0408c 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -72,7 +72,7 @@ # stack use, we use 1.5K as heuristic, assuming that we typically have lots # of tiny stack frames and the odd large one. # -# Store larger buffers in BSS, use MAYBE_STATIC to share code with __PRE_RAM__ +# Store larger buffers in BSS, use MAYBE_STATIC_BSS to share code with __PRE_RAM__ # on x86. # Since GCCs detection of dynamic array bounds unfortunately seems to be # very basic, you'll sometimes have to use a static upper bound for the -- To view, visit https://review.coreboot.org/c/coreboot/+/35003 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80485ebac94b88c5864a949b17ad1dccdfda6a40 Gerrit-Change-Number: 35003 Gerrit-PatchSet: 8 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: Move and rename ARCH_STAGE_HAS_xxx_SECTION rules
by Kyösti Mälkki (Code Review) 26 Aug '19

26 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35014 ) Change subject: Move and rename ARCH_STAGE_HAS_xxx_SECTION rules ...................................................................... Move and rename ARCH_STAGE_HAS_xxx_SECTION rules Currently only x86 requires special handling here, for simplicity avoid introducing <arch/rules.h> and deal with this directly in <rules.h>. For consistency prefixes are changed from ARCH_ to ENV_. The new definition of ENV_STAGE_HAS_HEAP_SECTION is changed to reflect whether our build for the stage includes implementation of malloc(). Change-Id: I95a56dbad3482202f6cc03043589bebfb13c39af Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/include/arch/memlayout.h M src/include/memlayout.h M src/include/rules.h M src/lib/program.ld 4 files changed, 16 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/35014/1 diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h index de80f42..7dcdd98 100644 --- a/src/arch/x86/include/arch/memlayout.h +++ b/src/arch/x86/include/arch/memlayout.h @@ -16,13 +16,6 @@ #ifndef __ARCH_MEMLAYOUT_H #define __ARCH_MEMLAYOUT_H - -#if ENV_BOOTBLOCK || ENV_ROMSTAGE || ENV_VERSTAGE -/* No .data or .bss sections. Cache as RAM is handled separately. */ -#define ARCH_STAGE_HAS_DATA_SECTION 0 -#define ARCH_STAGE_HAS_BSS_SECTION 0 -#endif - #if (CONFIG_RAMTOP == 0) # error "CONFIG_RAMTOP not configured" #endif diff --git a/src/include/memlayout.h b/src/include/memlayout.h index 1ed87b6..505ccc1 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -30,24 +30,6 @@ #define ARCH_CACHELINE_ALIGN_SIZE 64 #endif -/* Default to data as well as bss. */ -#ifndef ARCH_STAGE_HAS_DATA_SECTION -#define ARCH_STAGE_HAS_DATA_SECTION 1 -#endif - -#ifndef ARCH_STAGE_HAS_BSS_SECTION -#define ARCH_STAGE_HAS_BSS_SECTION 1 -#endif - -/* - * Default is that currently ENV_PAYLOAD_LOADER enable stage, smm, - * and rmodules have a heap. - */ -#ifndef ARCH_STAGE_HAS_HEAP_SECTION -#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_PAYLOAD_LOADER || ENV_SMM || \ - ENV_RMODULE) -#endif - #define STR(x) #x #define ALIGN_COUNTER(align) \ diff --git a/src/include/rules.h b/src/include/rules.h index 10cd715..3412e01 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -266,6 +266,19 @@ #define ENV_PAYLOAD_LOADER ENV_RAMSTAGE #endif +#if CONFIG(ARCH_X86) && (ENV_BOOTBLOCK || ENV_ROMSTAGE || ENV_VERSTAGE) +/* No .data or .bss sections. Cache as RAM is handled separately. */ +#define ENV_STAGE_HAS_DATA_SECTION 0 +#define ENV_STAGE_HAS_BSS_SECTION 0 +#else +/* Both .data nnd .bss, sometimes SRAM not DRAM. */ +#define ENV_STAGE_HAS_DATA_SECTION 1 +#define ENV_STAGE_HAS_BSS_SECTION 1 +#endif + +/* Currently ramstage and smm build with malloc().*/ +#define ENV_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM) + /** * For pre-DRAM stages and post-CAR always build with simple device model, ie. * PCI, PNP and CPU functions operate without use of devicetree. The reason diff --git a/src/lib/program.ld b/src/lib/program.ld index 851aa75..1b30c0e 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -85,7 +85,7 @@ #endif /* Include data, bss, and heap in that order. Not defined for all stages. */ -#if ARCH_STAGE_HAS_DATA_SECTION +#if ENV_STAGE_HAS_DATA_SECTION .data . : { . = ALIGN(ARCH_CACHELINE_ALIGN_SIZE); _data = .; @@ -125,7 +125,7 @@ } #endif -#if ARCH_STAGE_HAS_BSS_SECTION +#if ENV_STAGE_HAS_BSS_SECTION .bss . : { . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _bss = .; @@ -138,7 +138,7 @@ } #endif -#if ARCH_STAGE_HAS_HEAP_SECTION +#if ENV_STAGE_HAS_HEAP_SECTION .heap . : { . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _heap = .; -- To view, visit https://review.coreboot.org/c/coreboot/+/35014 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95a56dbad3482202f6cc03043589bebfb13c39af Gerrit-Change-Number: 35014 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 18

Change in coreboot[master]: mb/scaleway/tagada: Remove use of car_get_var()
by Kyösti Mälkki (Code Review) 26 Aug '19

26 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35085 ) Change subject: mb/scaleway/tagada: Remove use of car_get_var() ...................................................................... mb/scaleway/tagada: Remove use of car_get_var() Board has CAR_GLOBAL_MIGRATION=n and can use .bss for a variable that was previously declared with CAR_GLOBAL. Test for !defined(__PRE_RAM__) can be transformed into ENV_RAMSTAGE here as the warnings about invalid bmcinfo structure do not need to be repeated in SMM console, which is generally disabled anyways due to DEBUG_SMI=n. Change-Id: I6b63213484107fa0eeb0d952d8766916b44a3c4e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/scaleway/tagada/bmcinfo.c 1 file changed, 10 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/35085/1 diff --git a/src/mainboard/scaleway/tagada/bmcinfo.c b/src/mainboard/scaleway/tagada/bmcinfo.c index 237d551..93b4539 100644 --- a/src/mainboard/scaleway/tagada/bmcinfo.c +++ b/src/mainboard/scaleway/tagada/bmcinfo.c @@ -16,7 +16,6 @@ #include <stdint.h> #include <stdlib.h> -#include <arch/early_variables.h> #include <console/console.h> #include <console/uart.h> @@ -52,15 +51,12 @@ BMCINFO_VALID_NEED_WARN, BMCINFO_VALID, }; - -static enum biosBmcInfoValidFlag_e CAR_GLOBAL biosBmcInfoValidFlag; - static bool bmcinfo_is_valid(size_t minsize) { + static enum biosBmcInfoValidFlag_e biosBmcInfoValidFlag; const biosBmcInfo_t *bmc_info = BMC_INFO; - int flag = car_get_var(biosBmcInfoValidFlag); - if (flag == BMCINFO_UNTESTED) { - flag = BMCINFO_INVALID; + if (biosBmcInfoValidFlag == BMCINFO_UNTESTED) { + biosBmcInfoValidFlag = BMCINFO_INVALID; if ((bmc_info->magic0 == BIOSBMCINFO_MAGIC0) && (bmc_info->magic1 == BIOSBMCINFO_MAGIC1) && (bmc_info->length >= offsetof(biosBmcInfo_t, hwRev)) @@ -73,20 +69,17 @@ if (bmc_info->chksum == chksum) { if (bmc_info->length >= offsetof(biosBmcInfo_t, endMarker)) - flag = BMCINFO_VALID; + biosBmcInfoValidFlag = BMCINFO_VALID; else - flag = BMCINFO_VALID_NEED_WARN; + biosBmcInfoValidFlag = BMCINFO_VALID_NEED_WARN; } } - car_set_var(biosBmcInfoValidFlag, flag); } -#if !defined(__PRE_RAM__) - if (flag == BMCINFO_INVALID) { + if (ENV_RAMSTAGE && biosBmcInfoValidFlag == BMCINFO_INVALID) { int length = offsetof(biosBmcInfo_t, endMarker); printk(BIOS_CRIT, "WARNING bmcInfo struct" "is not available please update your BMC.\n"); - flag = BMCINFO_INVALID_WARNED; - car_set_var(biosBmcInfoValidFlag, flag); + biosBmcInfoValidFlag = BMCINFO_INVALID_WARNED; printk(BIOS_CRIT, "bmcInfo magic = \"%x-%x\"\n", bmc_info->magic0, bmc_info->magic1); printk(BIOS_CRIT, "bmcInfo length = %d expected = %d\"\n", @@ -99,15 +92,13 @@ printk(BIOS_CRIT, "bmcInfo chksum = 0x%x expected = 0x%x\"\n", bmc_info->chksum, chksum); } - if (flag == BMCINFO_VALID_NEED_WARN) { + if (ENV_RAMSTAGE && biosBmcInfoValidFlag == BMCINFO_VALID_NEED_WARN) { printk(BIOS_CRIT, "WARNING bmcInfo struct" " is incomplete please update your BMC.\n"); - flag = BMCINFO_VALID; - car_set_var(biosBmcInfoValidFlag, flag); + biosBmcInfoValidFlag = BMCINFO_VALID; } -#endif - if (flag < BMCINFO_VALID_NEED_WARN) + if (biosBmcInfoValidFlag < BMCINFO_VALID_NEED_WARN) return false; return (bmc_info->length >= minsize); } -- To view, visit https://review.coreboot.org/c/coreboot/+/35085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b63213484107fa0eeb0d952d8766916b44a3c4e Gerrit-Change-Number: 35085 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: x86: Introduce RESET_VECTOR_IN_RAM option
by Kyösti Mälkki (Code Review) 26 Aug '19

26 Aug '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35004 ) Change subject: x86: Introduce RESET_VECTOR_IN_RAM option ...................................................................... Patch Set 10: (2 comments) https://review.coreboot.org/c/coreboot/+/35004/10/src/Kconfig File src/Kconfig: https://review.coreboot.org/c/coreboot/+/35004/10/src/Kconfig@155 PS10, Line 155: config RESET_VECTOR_IN_RAM > Can't this go in src/arch/x86/Kconfig? It can, if we feel no other arch would soon use it. Do you want it named _RAM or _DRAM? I had suggested the former, Marshall chose the latter. https://review.coreboot.org/c/coreboot/+/35004/10/src/arch/x86/memlayout.ld File src/arch/x86/memlayout.ld: https://review.coreboot.org/c/coreboot/+/35004/10/src/arch/x86/memlayout.ld… PS10, Line 20: #if ENV_ROMSTAGE_OR_BEFORE > Why not &&? I would hit #error below for every !ENV_ROMSTAGE_OR_BEFORE ? -- To view, visit https://review.coreboot.org/c/coreboot/+/35004 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I098ecf8bf200550db1e15f178f7661c1ac516dc5 Gerrit-Change-Number: 35004 Gerrit-PatchSet: 10 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 26 Aug 2019 20:49:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: x86: Introduce RESET_VECTOR_IN_RAM option
by Julius Werner (Code Review) 26 Aug '19

26 Aug '19

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35004 ) Change subject: x86: Introduce RESET_VECTOR_IN_RAM option ...................................................................... Patch Set 10: (2 comments) https://review.coreboot.org/c/coreboot/+/35004/10/src/Kconfig File src/Kconfig: https://review.coreboot.org/c/coreboot/+/35004/10/src/Kconfig@155 PS10, Line 155: config RESET_VECTOR_IN_RAM Can't this go in src/arch/x86/Kconfig? https://review.coreboot.org/c/coreboot/+/35004/10/src/arch/x86/memlayout.ld File src/arch/x86/memlayout.ld: https://review.coreboot.org/c/coreboot/+/35004/10/src/arch/x86/memlayout.ld… PS10, Line 20: #if ENV_ROMSTAGE_OR_BEFORE Why not &&? -- To view, visit https://review.coreboot.org/c/coreboot/+/35004 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I098ecf8bf200550db1e15f178f7661c1ac516dc5 Gerrit-Change-Number: 35004 Gerrit-PatchSet: 10 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 26 Aug 2019 20:37:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: Split MAYBE_STATIC to _BSS and _NONZERO variants
by Julius Werner (Code Review) 26 Aug '19

26 Aug '19

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35003 ) Change subject: Split MAYBE_STATIC to _BSS and _NONZERO variants ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/35003 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80485ebac94b88c5864a949b17ad1dccdfda6a40 Gerrit-Change-Number: 35003 Gerrit-PatchSet: 7 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 26 Aug 2019 20:31:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit August 2019