coreboot-gerrit August 2019

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Change in coreboot[master]: nb/intel/gm45: Call ddr3_calibrate_zq() only for DDR3 :)
by Nico Huber (Code Review) 26 Aug '19

26 Aug '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34828 ) Change subject: nb/intel/gm45: Call ddr3_calibrate_zq() only for DDR3 :) ...................................................................... nb/intel/gm45: Call ddr3_calibrate_zq() only for DDR3 :) Change-Id: I7d00ddf727e7250b767a1c4b58bf11b17e900fc1 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/northbridge/intel/gm45/raminit.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/34828/1 diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index 80e5f02..1af50f5 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -2011,7 +2011,8 @@ /* Perform ZQ calibration for DDR3. */ - ddr3_calibrate_zq(); + if (sysinfo->spd_type == DDR3) + ddr3_calibrate_zq(); /* Perform receive-enable calibration. */ raminit_receive_enable_calibration(timings, dimms); -- To view, visit https://review.coreboot.org/c/coreboot/+/34828 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d00ddf727e7250b767a1c4b58bf11b17e900fc1 Gerrit-Change-Number: 34828 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/soc/intel: Add ACPI HPET table
by Patrick Rudolph (Code Review) 26 Aug '19

26 Aug '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35027 ) Change subject: src/soc/intel: Add ACPI HPET table ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Tested on OCP Wedge100s: The HPET is now exposed to the OS. https://review.coreboot.org/c/coreboot/+/35027/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/35027/2//COMMIT_MSG@7 PS2, Line 7: src/soc/intel: Add ACPI HPET table soc/intel/fsp_broadwell_de: -- To view, visit https://review.coreboot.org/c/coreboot/+/35027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idae9a7d3d4233037214d6203996bf44fe5f3a845 Gerrit-Change-Number: 35027 Gerrit-PatchSet: 2 Gerrit-Owner: Johnny Lin Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: David Hendricks <dhendrix.sync(a)gmail.com> Gerrit-Reviewer: Johnny Lin Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Name of user not set #1002539 Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: Łukasz Siudut Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Comment-Date: Mon, 26 Aug 2019 06:49:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/octopus: Re-assign sku number for vortininja
by Chen Wisley (Code Review) 26 Aug '19

26 Aug '19

Chen Wisley has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35065 ) Change subject: mb/google/octopus: Re-assign sku number for vortininja ...................................................................... mb/google/octopus: Re-assign sku number for vortininja Re-assign sku number for vortininja. BuG=b:138177049 BRANCH=octopus TEST=emerge-octopus coreboot Change-Id: I3166a635151fcc7b2e3c0122fa05925cfa5df7d0 Signed-off-by: Wisley Chen <wisley.chen(a)quantatw.com> --- M src/mainboard/google/octopus/variants/meep/include/variant/sku.h M src/mainboard/google/octopus/variants/meep/variant.c 2 files changed, 9 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/35065/1 diff --git a/src/mainboard/google/octopus/variants/meep/include/variant/sku.h b/src/mainboard/google/octopus/variants/meep/include/variant/sku.h index 16a4eab..5656d37 100644 --- a/src/mainboard/google/octopus/variants/meep/include/variant/sku.h +++ b/src/mainboard/google/octopus/variants/meep/include/variant/sku.h @@ -17,14 +17,15 @@ #define __MAINBOARD_SKU_H__ enum { - SKU_4_VORTININJA = 4, /* Stylus + rear camera */ - SKU_5_VORTININJA = 5, /* Stylus + no rear camera */ - SKU_6_VORTININJA = 6, /* no Stylus + rear camera */ - SKU_7_VORTININJA = 7, /* no Stylus + no rear camera */ SKU_33_DORP = 33, /* HDMI */ SKU_34_DORP = 34, /* HDMI+Kblight */ SKU_35_DORP = 35, /* HDMI+TS */ SKU_36_DORP = 36, /* HDMI+TS+KBlight */ + SKU_49_VORTININJA = 49, /* Stylus + rear camera */ + SKU_50_VORTININJA = 50, /* Stylus + no rear camera */ + SKU_51_VORTININJA = 51, /* no Stylus + rear camera */ + SKU_52_VORTININJA = 52, /* no Stylus + no rear camera */ + }; #endif /* __MAINBOARD_SKU_H__ */ diff --git a/src/mainboard/google/octopus/variants/meep/variant.c b/src/mainboard/google/octopus/variants/meep/variant.c index ece8ff9..fc34888 100644 --- a/src/mainboard/google/octopus/variants/meep/variant.c +++ b/src/mainboard/google/octopus/variants/meep/variant.c @@ -25,10 +25,10 @@ uint32_t sku_id = get_board_sku(); switch (sku_id) { - case SKU_4_VORTININJA: - case SKU_5_VORTININJA: - case SKU_6_VORTININJA: - case SKU_7_VORTININJA: + case SKU_49_VORTININJA: + case SKU_50_VORTININJA: + case SKU_51_VORTININJA: + case SKU_52_VORTININJA: filename = "wifi_sar-vortininja.hex"; break; } -- To view, visit https://review.coreboot.org/c/coreboot/+/35065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3166a635151fcc7b2e3c0122fa05925cfa5df7d0 Gerrit-Change-Number: 35065 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/soc/intel: Add ACPI HPET table
by David Hendricks (Code Review) 26 Aug '19

26 Aug '19

David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35027 ) Change subject: src/soc/intel: Add ACPI HPET table ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/35027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idae9a7d3d4233037214d6203996bf44fe5f3a845 Gerrit-Change-Number: 35027 Gerrit-PatchSet: 2 Gerrit-Owner: Johnny Lin Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: David Hendricks <dhendrix.sync(a)gmail.com> Gerrit-Reviewer: Johnny Lin Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Name of user not set #1002539 Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: Łukasz Siudut Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Comment-Date: Mon, 26 Aug 2019 04:51:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src/soc/intel: Add ACPI HPET table
by Johnny Lin (Code Review) 26 Aug '19

26 Aug '19

Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35027 ) Change subject: src/soc/intel: Add ACPI HPET table ...................................................................... Patch Set 2: (2 comments) > Patch Set 1: > > (2 comments) https://review.coreboot.org/c/coreboot/+/35027/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/35027/1//COMMIT_MSG@10 PS1, Line 10: > please add this was tested, i. […] Done https://review.coreboot.org/c/coreboot/+/35027/1/src/mainboard/ocp/monolake… File src/mainboard/ocp/monolake/mainboard.c: https://review.coreboot.org/c/coreboot/+/35027/1/src/mainboard/ocp/monolake… PS1, Line 85: /* Enable access to the BMC IPMI via KCS */ > There's acpi_write_hpet() which seems to do the same as the code in acpi_create_intel_hpet(), please […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/35027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idae9a7d3d4233037214d6203996bf44fe5f3a845 Gerrit-Change-Number: 35027 Gerrit-PatchSet: 2 Gerrit-Owner: Johnny Lin Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: David Hendricks <dhendrix.sync(a)gmail.com> Gerrit-Reviewer: Johnny Lin Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Name of user not set #1002539 Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Łukasz Siudut Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Comment-Date: Mon, 26 Aug 2019 03:23:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Comment-In-Reply-To: Andrey Petrov <anpetrov(a)fb.com> Gerrit-MessageType: comment

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Change in coreboot[master]: src/soc/intel: Add ACPI HPET table
by Johnny Lin (Code Review) 26 Aug '19

26 Aug '19

Hello Andrey Petrov, David Hendricks, Name of user not set #1002539, Łukasz Siudut, Patrick Rudolph, Jonathan Zhang, Philipp Deppenwiese, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35027 to look at the new patch set (#2). Change subject: src/soc/intel: Add ACPI HPET table ...................................................................... src/soc/intel: Add ACPI HPET table Tested on Mono Lake TEST=Note the kernel log: hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0, 0, 0, 0, 0 hpet0: 8 comparators, 64-bit 14.318180 MHz counter Change-Id: Idae9a7d3d4233037214d6203996bf44fe5f3a845 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/soc/intel/fsp_broadwell_de/Kconfig M src/soc/intel/fsp_broadwell_de/acpi.c M src/soc/intel/fsp_broadwell_de/include/soc/acpi.h M src/soc/intel/fsp_broadwell_de/southcluster.c 4 files changed, 20 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/35027/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/35027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idae9a7d3d4233037214d6203996bf44fe5f3a845 Gerrit-Change-Number: 35027 Gerrit-PatchSet: 2 Gerrit-Owner: Johnny Lin Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: David Hendricks <dhendrix.sync(a)gmail.com> Gerrit-Reviewer: Johnny Lin Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Name of user not set #1002539 Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Łukasz Siudut Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: amdfam10: Drop spurious #ifdef __PRE_RAM__
by Kyösti Mälkki (Code Review) 26 Aug '19

26 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34930 ) Change subject: amdfam10: Drop spurious #ifdef __PRE_RAM__ ...................................................................... amdfam10: Drop spurious #ifdef __PRE_RAM__ Change-Id: I4215b27332034a3c07052db92e4abae55c3fe967 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/northbridge/amd/amdfam10/amdfam10.h M src/northbridge/amd/amdfam10/amdfam10_util.c M src/northbridge/amd/amdfam10/util.c M src/southbridge/amd/cimx/sb800/fan.h M src/southbridge/amd/cimx/sb900/cfg.c M src/southbridge/broadcom/bcm5785/bcm5785.h M src/southbridge/nvidia/ck804/ck804.h M src/southbridge/nvidia/ck804/smbus.h M src/southbridge/nvidia/mcp55/mcp55.h 9 files changed, 10 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/34930/1 diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index 321e87d..96938b2 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -922,13 +922,11 @@ #include "nums.h" -#ifdef __PRE_RAM__ #if NODE_NUMS == 64 #define NODE_PCI(x, fn) ((x < 32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) #else #define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) #endif -#endif /* Include wrapper for MCT (works for DDR2 or DDR3) */ #include <northbridge/amd/amdmct/wrappers/mcti.h> @@ -989,11 +987,8 @@ struct DCTStatStruc DCTstatA[NODE_NUMS]; } __packed; -#ifndef __PRE_RAM__ struct device *get_node_pci(u32 nodeid, u32 fn); -#endif -#ifdef __PRE_RAM__ void showallroutes(int level, pci_devfn_t dev); void setup_resource_map_offset(const u32 *register_values, u32 max, u32 @@ -1017,8 +1012,6 @@ u8 get_sbbusn(u8 sblk); void set_bios_reset(void); -#endif - #include "northbridge/amd/amdht/porting.h" BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, const u8 **List); diff --git a/src/northbridge/amd/amdfam10/amdfam10_util.c b/src/northbridge/amd/amdfam10/amdfam10_util.c index 292049e..3e8c2fb 100644 --- a/src/northbridge/amd/amdfam10/amdfam10_util.c +++ b/src/northbridge/amd/amdfam10/amdfam10_util.c @@ -14,15 +14,14 @@ * GNU General Public License for more details. */ -#include <console/console.h> - #include <arch/cpu.h> +#include <console/console.h> +#include <device/pci_ops.h> +#include <device/pci_def.h> #include "raminit.h" #include <northbridge/amd/amdmct/amddefs.h> -#ifndef __PRE_RAM__ -#include <include/device/pci_ops.h> -#include <include/device/pci_def.h> +#ifndef __SIMPLE_DEVICE__ u32 Get_NB32(u32 dev, u32 reg) { return pci_read_config32(pcidev_path_on_root(PCI_DEV2DEVFN(dev)), reg); diff --git a/src/northbridge/amd/amdfam10/util.c b/src/northbridge/amd/amdfam10/util.c index 39c2bfb..ed5556f 100644 --- a/src/northbridge/amd/amdfam10/util.c +++ b/src/northbridge/amd/amdfam10/util.c @@ -21,11 +21,10 @@ * It can be called after RAM is set up by including amdfam10.h and enabling the * compilation of this file in src/northbridge/amd/amdfam10/Makefile.inc. */ -#ifndef __PRE_RAM__ #include <console/console.h> #include <device/pci.h> #include <device/pci_ops.h> -#endif + #include "amdfam10.h" /* Function 1 */ diff --git a/src/southbridge/amd/cimx/sb800/fan.h b/src/southbridge/amd/cimx/sb800/fan.h index f31e486..3734da1 100644 --- a/src/southbridge/amd/cimx/sb800/fan.h +++ b/src/southbridge/amd/cimx/sb800/fan.h @@ -16,10 +16,10 @@ #ifndef _SB800_FAN_H_ #define _SB800_FAN_H_ -#ifndef __PRE_RAM__ +#include <device/device.h> + void init_sb800_IMC_fans(struct device *dev); void init_sb800_MANUAL_fans(struct device *dev); -#endif /* Fan Register Definitions */ #define FAN_0_OFFSET 0x00 diff --git a/src/southbridge/amd/cimx/sb900/cfg.c b/src/southbridge/amd/cimx/sb900/cfg.c index 353d577..2e4173f 100644 --- a/src/southbridge/amd/cimx/sb900/cfg.c +++ b/src/southbridge/amd/cimx/sb900/cfg.c @@ -243,15 +243,13 @@ sb_config->PciClks = SB_PCI_CLOCK_RESERVED; sb_config->hwm.hwmEnable = 0x0; -#ifndef __PRE_RAM__ /* ramstage cimx config here */ - if (!sb_config->StdHeader.CALLBACK.CalloutPtr) { + if (ENV_RAMSTAGE && !sb_config->StdHeader.CALLBACK.CalloutPtr) { sb_config->StdHeader.CALLBACK.CalloutPtr = sb900_callout_entry; } //sb_config-> -#endif //!__PRE_RAM__ - printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - End.\n"); + printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - End.\n"); } void SbPowerOnInit_Config(AMDSBCFG *sb_config) diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.h b/src/southbridge/broadcom/bcm5785/bcm5785.h index 4517dda..e1c6f66 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785.h +++ b/src/southbridge/broadcom/bcm5785/bcm5785.h @@ -20,11 +20,8 @@ #include <device/device.h> #include "chip.h" -#ifndef __PRE_RAM__ void bcm5785_enable(struct device *dev); -#else void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); -#endif void bcm5785_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device); diff --git a/src/southbridge/nvidia/ck804/ck804.h b/src/southbridge/nvidia/ck804/ck804.h index 5505691..6812b5b 100644 --- a/src/southbridge/nvidia/ck804/ck804.h +++ b/src/southbridge/nvidia/ck804/ck804.h @@ -26,8 +26,6 @@ #define CK804B_BUSN 0x80 #define CK804B_DEVN_BASE (!CONFIG(SB_HT_CHAIN_UNITID_OFFSET_ONLY) ? CK804_DEVN_BASE : 1) -#ifdef __PRE_RAM__ void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); -#endif #endif diff --git a/src/southbridge/nvidia/ck804/smbus.h b/src/southbridge/nvidia/ck804/smbus.h index cec62b3..618e177 100644 --- a/src/southbridge/nvidia/ck804/smbus.h +++ b/src/southbridge/nvidia/ck804/smbus.h @@ -49,7 +49,6 @@ return -3; } -#ifndef __PRE_RAM__ static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device) { unsigned char global_status_register, byte; @@ -114,7 +113,6 @@ return 0; } -#endif static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address) diff --git a/src/southbridge/nvidia/mcp55/mcp55.h b/src/southbridge/nvidia/mcp55/mcp55.h index 8d595c9..944d35a 100644 --- a/src/southbridge/nvidia/mcp55/mcp55.h +++ b/src/southbridge/nvidia/mcp55/mcp55.h @@ -24,11 +24,10 @@ #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE #endif -#ifndef __PRE_RAM__ #include "chip.h" void mcp55_enable(struct device *dev); extern struct pci_operations mcp55_pci_ops; -#else + void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); void enable_smbus(void); int smbus_recv_byte(unsigned device); @@ -40,6 +39,5 @@ int smbusx_read_byte(unsigned smb_index, unsigned device, unsigned address); int smbusx_write_byte(unsigned smb_index, unsigned device, unsigned address, unsigned char val); -#endif #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/34930 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4215b27332034a3c07052db92e4abae55c3fe967 Gerrit-Change-Number: 34930 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: coreboot.rom: add ffs headers
by Marty E. Plummer (Code Review) 25 Aug '19

25 Aug '19

Marty E. Plummer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35010 ) Change subject: coreboot.rom: add ffs headers ...................................................................... coreboot.rom: add ffs headers Change-Id: I95b4169d1f89a403d3ec4f293479c81c3d34f602 Signed-off-by: Marty E. Plummer <hanetzer(a)startmail.com> --- M Makefile.inc 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/35010/1 diff --git a/Makefile.inc b/Makefile.inc index 722e180..f2b3734 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -1177,6 +1177,14 @@ endif endif +ifeq ($(CONFIG_FFS_HEADER),y) + $(FPART) -C -t $@.tmp -s $(CONFIG_ROM_SIZE) -b 4k -p 0 + $(FPART) -C -t $@.tmp -s $(CONFIG_ROM_SIZE) -b 4k -p $(FMAP_FFS_HDR_2_BASE) + $(FPART) -A -t $@.tmp --size 128kb --offset $(FMAP_FFS_HDR_SIZE) --flags 0 --name HBB -p 0,$(FMAP_FFS_HDR_2_BASE) + $(FPART) -A -t $@.tmp --size $(FMAP_CBFS_SIZE) --offset $(FMAP_CBFS_BASE) --flags 0 --name COREBOOT -p 0,$(FMAP_FFS_HDR_2_BASE) + $(FPART) -A -t $@.tmp --size $(FMAP_FFS_HDR_SIZE) --offset $(FMAP_FFS_HDR_2_BASE) --flags 1 --name BACKUP_PART -p 0 + $(FPART) -A -t $@.tmp --size $(FMAP_FFS_HDR_SIZE) --offset 0 --flags 1 --name BACKUP_PART -p $(FMAP_FFS_HDR_2_BASE) +endif # ($(CONFIG_FFS_HEADER),y) mv $@.tmp $@ @printf " CBFSLAYOUT $(subst $(obj)/,,$(@))\n\n" $(CBFSTOOL) $@ layout -- To view, visit https://review.coreboot.org/c/coreboot/+/35010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95b4169d1f89a403d3ec4f293479c81c3d34f602 Gerrit-Change-Number: 35010 Gerrit-PatchSet: 1 Gerrit-Owner: Marty E. Plummer <hanetzer(a)startmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Marty E. Plummer <hanetzer(a)startmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/ppc64: add -mregnames to assembler directives
by Marty E. Plummer (Code Review) 25 Aug '19

25 Aug '19

Marty E. Plummer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35083 ) Change subject: arch/ppc64: add -mregnames to assembler directives ...................................................................... arch/ppc64: add -mregnames to assembler directives I order to avoid spurious errors `Error: unsupported relocation against rN` without a massive asm.h header #define'ing rN to N add these flags. Change-Id: Ib3bef76c4449a2edc7b5874c6bda7df9007afd37 Signed-off-by: Marty E. Plummer <hanetzer(a)startmail.com> --- M src/arch/ppc64/Makefile.inc 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/35083/1 diff --git a/src/arch/ppc64/Makefile.inc b/src/arch/ppc64/Makefile.inc index bb9c63dd..e9997f7 100644 --- a/src/arch/ppc64/Makefile.inc +++ b/src/arch/ppc64/Makefile.inc @@ -16,8 +16,8 @@ ## ################################################################################ -ppc64_flags = -I$(src)/arch/ppc64/ -mbig-endian -ppc64_asm_flags = +ppc64_flags = -I$(src)/arch/ppc64/ -mbig-endian -Wa,-mregnames +ppc64_asm_flags = -mregnames ################################################################################ ## Take care of subdirectories -- To view, visit https://review.coreboot.org/c/coreboot/+/35083 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3bef76c4449a2edc7b5874c6bda7df9007afd37 Gerrit-Change-Number: 35083 Gerrit-PatchSet: 1 Gerrit-Owner: Marty E. Plummer <hanetzer(a)startmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/ocp/monolake: Add ACPI HPET table
by Patrick Rudolph (Code Review) 25 Aug '19

25 Aug '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35027 ) Change subject: mb/ocp/monolake: Add ACPI HPET table ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/c/coreboot/+/35027/1/src/mainboard/ocp/monolake… File src/mainboard/ocp/monolake/mainboard.c: https://review.coreboot.org/c/coreboot/+/35027/1/src/mainboard/ocp/monolake… PS1, Line 85: /* Enable access to the BMC IPMI via KCS */ > this code is not mainboard-specific and should go to SoC. […] There's acpi_write_hpet() which seems to do the same as the code in acpi_create_intel_hpet(), please use that instead and drop acpi_create_intel_hpet(). -- To view, visit https://review.coreboot.org/c/coreboot/+/35027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idae9a7d3d4233037214d6203996bf44fe5f3a845 Gerrit-Change-Number: 35027 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: David Hendricks <dhendrix.sync(a)gmail.com> Gerrit-Reviewer: Johnny Lin Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Name of user not set #1002539 Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Łukasz Siudut Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 25 Aug 2019 08:28:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Andrey Petrov <anpetrov(a)fb.com> Gerrit-MessageType: comment

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coreboot-gerrit August 2019