coreboot-gerrit August 2019

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Change in coreboot[master]: mb/facebook/fbg1701: Correct EFP1 configuration
by Frans Hendriks (Code Review) 26 Aug '19

26 Aug '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35043 ) Change subject: mb/facebook/fbg1701: Correct EFP1 configuration ...................................................................... mb/facebook/fbg1701: Correct EFP1 configuration EFP1 is configured as 'DisplayPort with HDMI/DVI compatibility'. Using this setting 4K monitor is configured into lower resolution. . Change EFP1 setting to 'HDMI/DVI' The next addtional small changes are made in VBT: UEFI GOP Driver Child Device 2 = LFP Child Device 3 = EFP1/LFP LFP Panel configuration Y-Res of Panel #10 = 1920 BUG=N/A TEST=LCD and HDMI on Facebook FBG1701 Change-Id: Idc694b15ff94b83291a8c8252e269b7e6d96f87b Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/mainboard/facebook/fbg1701/data.vbt 1 file changed, 0 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/35043/1 diff --git a/src/mainboard/facebook/fbg1701/data.vbt b/src/mainboard/facebook/fbg1701/data.vbt index 39eba56..356c087 100644 --- a/src/mainboard/facebook/fbg1701/data.vbt +++ b/src/mainboard/facebook/fbg1701/data.vbt Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/35043 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc694b15ff94b83291a8c8252e269b7e6d96f87b Gerrit-Change-Number: 35043 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: vendorcode/eltan/security/lib: Always enable include cb_sha.c for boo...
by Frans Hendriks (Code Review) 26 Aug '19

26 Aug '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34667 ) Change subject: vendorcode/eltan/security/lib: Always enable include cb_sha.c for bootblock ...................................................................... vendorcode/eltan/security/lib: Always enable include cb_sha.c for bootblock cb_sha.c depends on C_ENVIRONMENT_BOOTBLOCK. Include cb_sha.c unconditional since C_ENVIRONMENT_BOOTBLOCK is default for projects. BUG=N/A TEST=Boot Linux 4.20 and verify logging on Facebook FBG-1701 Change-Id: If93195596efe7d8f298430e67eb1cf79804b96fc Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/vendorcode/eltan/security/lib/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/34667/1 diff --git a/src/vendorcode/eltan/security/lib/Makefile.inc b/src/vendorcode/eltan/security/lib/Makefile.inc index 5ef1bca..2c98aca 100644 --- a/src/vendorcode/eltan/security/lib/Makefile.inc +++ b/src/vendorcode/eltan/security/lib/Makefile.inc @@ -40,7 +40,7 @@ ifneq ($(filter y,$(CONFIG_VENDORCODE_ELTAN_VBOOT) $(CONFIG_VENDORCODE_ELTAN_MBOOT)),) -bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += cb_sha.c +bootblock-y += cb_sha.c $(eval $(call vendor-security-lib,bootblock)) bootblock-srcs += $(obj)/external/ven_sec_lib-bootblock/vboot_fw21.a -- To view, visit https://review.coreboot.org/c/coreboot/+/34667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If93195596efe7d8f298430e67eb1cf79804b96fc Gerrit-Change-Number: 34667 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: google/link: fix detection of dimm on channel 1
by Matt DeVillier (Code Review) 26 Aug '19

26 Aug '19

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35084 ) Change subject: google/link: fix detection of dimm on channel 1 ...................................................................... google/link: fix detection of dimm on channel 1 Changes to the sandybridge memory init code (both MRC and native) now require SPD data on all populated channels in order for dimms to be detected properly, so copy spd_data[0] to spd_data[2], as LINK always has 2 channels of memory down. Test: boot google/link, observe onboard RAM correctly detected on both channels Change-Id: Id01d57d5e5f928dfc1cd9063ab1625c440ef2bbe Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/link/romstage.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/35084/1 diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 2f3f07c..1fe71ea 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -156,8 +156,12 @@ }, }; *pei_data = pei_data_template; + /* LINK has 2 channels of memory down, so spd_data[0] and [2] + both need to be populated */ memcpy(pei_data->spd_data[0], locate_spd(), sizeof(pei_data->spd_data[0])); + memcpy(pei_data->spd_data[2], pei_data->spd_data[0], + sizeof(pei_data->spd_data[0])); } const struct southbridge_usb_port mainboard_usb_ports[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/35084 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id01d57d5e5f928dfc1cd9063ab1625c440ef2bbe Gerrit-Change-Number: 35084 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP]mainboard/lenovo/t410: Add new port
by build bot (Jenkins) (Code Review) 26 Aug '19

26 Aug '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/11791 ) Change subject: [WIP]mainboard/lenovo/t410: Add new port ...................................................................... Patch Set 14: (5 comments) https://review.coreboot.org/c/coreboot/+/11791/14/src/mainboard/lenovo/t410… File src/mainboard/lenovo/t410/romstage.c: https://review.coreboot.org/c/coreboot/+/11791/14/src/mainboard/lenovo/t410… PS14, Line 140: unsigned i; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/c/coreboot/+/11791/14/src/mainboard/lenovo/t410… File src/mainboard/lenovo/t410/smihandler.c: https://review.coreboot.org/c/coreboot/+/11791/14/src/mainboard/lenovo/t410… PS14, Line 35: switch (smif) { switch and case should be at the same indent https://review.coreboot.org/c/coreboot/+/11791/14/src/mainboard/lenovo/t410… PS14, Line 38: udelay(250000); long udelay - prefer mdelay; see arch/arm/include/asm/delay.h https://review.coreboot.org/c/coreboot/+/11791/14/src/mainboard/lenovo/t410… PS14, Line 71: switch (event) { switch and case should be at the same indent https://review.coreboot.org/c/coreboot/+/11791/14/src/mainboard/lenovo/t410… PS14, Line 98: switch (data) { switch and case should be at the same indent -- To view, visit https://review.coreboot.org/c/coreboot/+/11791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9d872e643dd242e925bfb46d18076e6ad100995 Gerrit-Change-Number: 11791 Gerrit-PatchSet: 14 Gerrit-Owner: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eloy Degen Gerrit-CC: Matt Parnell <mparnell(a)gmail.com> Gerrit-CC: Okashi Odayakana <okashi(a)okashi.me> Gerrit-CC: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Comment-Date: Mon, 26 Aug 2019 08:46:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP]mainboard/lenovo/t410: Add new port
by Patrick Rudolph (Code Review) 26 Aug '19

26 Aug '19

Patrick Rudolph has uploaded a new patch set (#14) to the change originally created by Nicolas Reinecke. ( https://review.coreboot.org/c/coreboot/+/11791 ) Change subject: [WIP]mainboard/lenovo/t410: Add new port ...................................................................... [WIP]mainboard/lenovo/t410: Add new port The port is based on the x201 / t410s. 2537-vg5 / i5, no discrete gpu Tested and working: * Native raminit * Native gfxinit * Booting Seabios 1.11.1 * Booting from EHCI * Running GNU/Linux 4.13.5 * No errors in dmesg * EHCI debug on the devices left side, bottom-right * Keyboard * Fn keys (Mute, Volume, Mic) * Touchpad * TPM * Ethernet * Wifi * Sound * USB Testing in progress. Untested: * VGA * Displayport * Ethernet Bugs: * Linux hangs in 2 out of 3 attempts when booting from USB * S3 resume is broken. TODOs: * Hide internal PCI devices Depends on: 1. Change-Id: Idd4986f39f21cb53cb019d0893d40fed94c6505b Details for flashing externally: 1. Disconnect all power 2. Connect the external flasher 3. Connect the power cord (This fixes internal power control) 4. Remove the power cord Change-Id: Id9d872e643dd242e925bfb46d18076e6ad100995 Signed-off-by: Nicolas Reinecke <nr(a)das-labor.org> --- A src/mainboard/lenovo/t410/Kconfig A src/mainboard/lenovo/t410/Kconfig.name A src/mainboard/lenovo/t410/Makefile.inc A src/mainboard/lenovo/t410/acpi/dock.asl A src/mainboard/lenovo/t410/acpi/ec.asl A src/mainboard/lenovo/t410/acpi/gpe.asl A src/mainboard/lenovo/t410/acpi/platform.asl A src/mainboard/lenovo/t410/acpi/superio.asl A src/mainboard/lenovo/t410/acpi_tables.c A src/mainboard/lenovo/t410/board_info.txt A src/mainboard/lenovo/t410/cmos.default A src/mainboard/lenovo/t410/cmos.layout A src/mainboard/lenovo/t410/devicetree.cb A src/mainboard/lenovo/t410/dock.c A src/mainboard/lenovo/t410/dock.h A src/mainboard/lenovo/t410/dsdt.asl A src/mainboard/lenovo/t410/gma-mainboard.ads A src/mainboard/lenovo/t410/gpio.c A src/mainboard/lenovo/t410/hda_verb.c A src/mainboard/lenovo/t410/mainboard.c A src/mainboard/lenovo/t410/romstage.c A src/mainboard/lenovo/t410/smi.h A src/mainboard/lenovo/t410/smihandler.c A src/mainboard/lenovo/t410/thermal.h 24 files changed, 1,915 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/11791/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/11791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9d872e643dd242e925bfb46d18076e6ad100995 Gerrit-Change-Number: 11791 Gerrit-PatchSet: 14 Gerrit-Owner: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eloy Degen Gerrit-CC: Matt Parnell <mparnell(a)gmail.com> Gerrit-CC: Okashi Odayakana <okashi(a)okashi.me> Gerrit-CC: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mainboard/emulation/qemu-aarch64: Update DRAM_SIZE_MB
by Asami Doi (Code Review) 26 Aug '19

26 Aug '19

Asami Doi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35024 ) Change subject: mainboard/emulation/qemu-aarch64: Update DRAM_SIZE_MB ...................................................................... mainboard/emulation/qemu-aarch64: Update DRAM_SIZE_MB DRAM_SIZE_MB should be the maximum size (255GiB / -m 261120M) that’s possible with QEMU on AArch64 virt because it tries to search the DRAM_SIZE_MB range to find the true memory size. Signed-off-by: Asami Doi <d0iasm.pub(a)gmail.com> Change-Id: Id479c0b18d1e1adceecdcca13e36119b95617e6d --- M Documentation/mainboard/emulation/qemu-aarch64.md M src/mainboard/emulation/qemu-aarch64/Kconfig 2 files changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/35024/1 diff --git a/Documentation/mainboard/emulation/qemu-aarch64.md b/Documentation/mainboard/emulation/qemu-aarch64.md index ee4c9e7..4df36a9 100644 --- a/Documentation/mainboard/emulation/qemu-aarch64.md +++ b/Documentation/mainboard/emulation/qemu-aarch64.md @@ -7,7 +7,7 @@ ```bash qemu-system-aarch64 -bios ./build/coreboot.rom \ -M virt,secure=on,virtualization=on -cpu cortex-a53 \ - -nographic -m 8912M + -nographic -m 8192M ``` - The default CPU in QEMU for AArch64 is a cortex-a15 which is 32-bit @@ -17,6 +17,7 @@ via `-machine secure=on,virtualization=on`. - You need to specify the size of memory more than 544 MiB because 512 MiB is reserved for the kernel. +- The maximum size of memory is 255GiB (-m 261120). ## Building coreboot with an arbitrary FIT payload There are 3 steps to make coreboot.rom for QEMU/AArch64. If you select @@ -30,7 +31,7 @@ ``` $ qemu-system-aarch64 \ -M virt,dumpdtb=virt.dtb,secure=on,virtualization=on \ - -cpu cortex-a53 -nographic -m 2048M + -cpu cortex-a53 -nographic -m 8192M ``` ### 2. Build a FIT image with a DTB diff --git a/src/mainboard/emulation/qemu-aarch64/Kconfig b/src/mainboard/emulation/qemu-aarch64/Kconfig index 7d8d7b2..ebdbf16 100644 --- a/src/mainboard/emulation/qemu-aarch64/Kconfig +++ b/src/mainboard/emulation/qemu-aarch64/Kconfig @@ -46,6 +46,6 @@ config DRAM_SIZE_MB int - default 1024 + default 261120 # The maximum dram size is 255GiB. endif # BOARD_EMULATION_QEMU_AARCH64 -- To view, visit https://review.coreboot.org/c/coreboot/+/35024 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id479c0b18d1e1adceecdcca13e36119b95617e6d Gerrit-Change-Number: 35024 Gerrit-PatchSet: 1 Gerrit-Owner: Asami Doi <d0iasm.pub(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/fsp_broadwell_de: Add ACPI HPET table
by Johnny Lin (Code Review) 26 Aug '19

26 Aug '19

Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35027 ) Change subject: soc/intel/fsp_broadwell_de: Add ACPI HPET table ...................................................................... Patch Set 3: Code-Review+1 (1 comment) > Patch Set 2: Code-Review+1 > > (1 comment) > > Tested on OCP Wedge100s: > The HPET is now exposed to the OS. https://review.coreboot.org/c/coreboot/+/35027/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/35027/2//COMMIT_MSG@7 PS2, Line 7: src/soc/intel: Add ACPI HPET table > soc/intel/fsp_broadwell_de: Done -- To view, visit https://review.coreboot.org/c/coreboot/+/35027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idae9a7d3d4233037214d6203996bf44fe5f3a845 Gerrit-Change-Number: 35027 Gerrit-PatchSet: 3 Gerrit-Owner: Johnny Lin Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: David Hendricks <dhendrix.sync(a)gmail.com> Gerrit-Reviewer: Johnny Lin Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Name of user not set #1002539 Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: Łukasz Siudut Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Comment-Date: Mon, 26 Aug 2019 07:15:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/fsp_broadwell_de: Add ACPI HPET table
by Johnny Lin (Code Review) 26 Aug '19

26 Aug '19

Hello Andrey Petrov, Patrick Rudolph, David Hendricks, Name of user not set #1002539, Łukasz Siudut, Patrick Rudolph, Jonathan Zhang, David Hendricks, Philipp Deppenwiese, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35027 to look at the new patch set (#3). Change subject: soc/intel/fsp_broadwell_de: Add ACPI HPET table ...................................................................... soc/intel/fsp_broadwell_de: Add ACPI HPET table Tested on Mono Lake TEST=Note the kernel log: hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0, 0, 0, 0, 0 hpet0: 8 comparators, 64-bit 14.318180 MHz counter Change-Id: Idae9a7d3d4233037214d6203996bf44fe5f3a845 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/soc/intel/fsp_broadwell_de/Kconfig M src/soc/intel/fsp_broadwell_de/acpi.c M src/soc/intel/fsp_broadwell_de/include/soc/acpi.h M src/soc/intel/fsp_broadwell_de/southcluster.c 4 files changed, 20 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/35027/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/35027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idae9a7d3d4233037214d6203996bf44fe5f3a845 Gerrit-Change-Number: 35027 Gerrit-PatchSet: 3 Gerrit-Owner: Johnny Lin Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: David Hendricks <dhendrix.sync(a)gmail.com> Gerrit-Reviewer: Johnny Lin Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Name of user not set #1002539 Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: Łukasz Siudut Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: lib: Register exception handlers for ARMv8
by Asami Doi (Code Review) 26 Aug '19

26 Aug '19

Asami Doi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34774 ) Change subject: lib: Register exception handlers for ARMv8 ...................................................................... lib: Register exception handlers for ARMv8 Register exception handlers to avoid a Synchronous External Abort that is raised when you try to access a non-memory address on ARMv8. An exception handler can jump over the faulting instruction. Signed-off-by: Asami Doi <d0iasm.pub(a)gmail.com> Change-Id: I09a306ca307ba4027d9758c3debc2e7c844c66b8 --- M src/lib/ramdetect.c 1 file changed, 54 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/34774/1 diff --git a/src/lib/ramdetect.c b/src/lib/ramdetect.c index 5416a58..7f53b57 100644 --- a/src/lib/ramdetect.c +++ b/src/lib/ramdetect.c @@ -15,24 +15,62 @@ #include <symbols.h> #include <device/mmio.h> #include <ramdetect.h> +#include <arch/exception.h> #include <console/console.h> #define OVERLAP(a, b, s, e) ((b) > (s) && (a) < (e)) +static enum { + ABORT_CHECKER_NOT_REGISTERED, + ABORT_CHECKER_DEACTIVATED, + ABORT_CHECKER_NOT_TRIGGERED, + ABORT_CHECKER_TRIGGERED, +} abort_state = ABORT_CHECKER_NOT_REGISTERED; + +static int abort_checker(struct exc_state *state, uint64_t vector_id) +{ + if (abort_state == ABORT_CHECKER_DEACTIVATED) + return EXC_RET_IGNORED; + + if (raw_read_esr_el3() >> 26 != 0x25) + return EXC_RET_IGNORED; /* Not a data abort. */ + + abort_state = ABORT_CHECKER_TRIGGERED; + state->elx.elr += sizeof(uint32_t); /* Jump over faulting instruction. */ + raw_write_elr_el3(state->elx.elr); + return EXC_RET_HANDLED; +} + +static void register_checker(void) +{ + struct exception_handler sync_elx; + struct exception_handler sync_el0; + + sync_elx.handler = &abort_checker; + sync_el0.handler = &abort_checker; + + exception_handler_register(EXC_VID_CUR_SP_ELX_SYNC, &sync_elx); + exception_handler_register(EXC_VID_CUR_SP_EL0_SYNC, &sync_el0); + + printk(BIOS_DEBUG, "ARM64: Abort checker handlers installed.\n"); +} + static int probe_mb(const uintptr_t dram_start, const uintptr_t size) { uintptr_t addr = dram_start + (size * MiB) - sizeof(uint32_t); - static const uint32_t patterns[] = { - 0x55aa55aa, - 0x12345678 - }; - void *ptr = (void *) addr; + static const uint32_t patterns[] = {0x55aa55aa, 0x12345678}; + void *ptr = (void *)addr; size_t i; /* Don't accidentally clober oneself. */ - if (OVERLAP(addr, addr + sizeof(uint32_t), (uintptr_t)_program, (uintptr_t) _eprogram)) + if (OVERLAP(addr, addr + sizeof(uint32_t), (uintptr_t)_program, (uintptr_t)_eprogram)) return 1; + if (ENV_ARM64) { + read32((void *)addr); + return abort_state == ABORT_CHECKER_NOT_TRIGGERED; + } + uint32_t old = read32(ptr); for (i = 0; i < ARRAY_SIZE(patterns); i++) { write32(ptr, patterns[i]); @@ -50,6 +88,12 @@ /* Probe an area if it's read/writable. */ size_t probe_ramsize(const uintptr_t dram_start, const size_t probe_size) { + if (ENV_ARM64) { + if (abort_state == ABORT_CHECKER_NOT_REGISTERED) + register_checker(); + abort_state = ABORT_CHECKER_NOT_TRIGGERED; + } + ssize_t i; size_t msb = 0; size_t discovered = 0; @@ -74,5 +118,9 @@ saved_result = discovered; printk(BIOS_DEBUG, "RAMDETECT: Found %zu MiB RAM\n", discovered); + + if (ENV_ARM64) + abort_state = ABORT_CHECKER_DEACTIVATED; + return discovered; } -- To view, visit https://review.coreboot.org/c/coreboot/+/34774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09a306ca307ba4027d9758c3debc2e7c844c66b8 Gerrit-Change-Number: 34774 Gerrit-PatchSet: 1 Gerrit-Owner: Asami Doi <d0iasm.pub(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Fix audio failure on drallion with FSP 1263
by Selma Bensaid (Code Review) 26 Aug '19

26 Aug '19

Hello Aamir Bohra, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/35078 to review the following change. Change subject: Fix audio failure on drallion with FSP 1263 ...................................................................... Fix audio failure on drallion with FSP 1263 FSP 1263 looks for UPD configuration of "AudioLinkHda" if false it disables SDI# link for the codec. Change-Id: I8330f47416e580bf6b9ca1faed1de5cd578d0e2e --- M src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/fsp_params.c 5 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/35078/1 diff --git a/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb b/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb index fe3b6c9..8470a2c 100644 --- a/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb +++ b/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb @@ -50,6 +50,12 @@ # Enable DDC for DDI port B register "DdiPortBDdc" = "1" + # HDA a + register "PchHdaDspEnable" = "1" + # Disable iDisplay codec enumeration + register "PchHdaIDispCodecDisconnect" = "1" + register "PchHdaAudioLinkHda" = "1" + # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 575b610..8e54625 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -50,6 +50,12 @@ # Enable DDC for DDI port B register "DdiPortBDdc" = "1" + # HDA a + register "PchHdaDspEnable" = "1" + # Disable iDisplay codec enumeration + register "PchHdaIDispCodecDisconnect" = "1" + register "PchHdaAudioLinkHda" = "1" + # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | diff --git a/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb b/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb index d3aab62..530d6f4 100644 --- a/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb +++ b/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb @@ -56,6 +56,12 @@ register "LanWakeFromDeepSx" = "0" register "WolEnableOverride" = "0" + # HDA a + register "PchHdaDspEnable" = "1" + # Disable iDisplay codec enumeration + register "PchHdaIDispCodecDisconnect" = "1" + register "PchHdaAudioLinkHda" = "1" + # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index fa98cd4..2ebe017 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -154,6 +154,7 @@ /* Enable/Disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1 */ uint8_t PchHdaAudioLinkHda; + uint8_t PchHdaIDispCodecDisconnect; uint8_t PchHdaAudioLinkDmic0; uint8_t PchHdaAudioLinkDmic1; uint8_t PchHdaAudioLinkSsp0; diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 494c1db..5cdddc6 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -205,6 +205,7 @@ /* Audio */ params->PchHdaDspEnable = config->PchHdaDspEnable; + params->PchHdaIDispCodecDisconnect = config->PchHdaIDispCodecDisconnect; params->PchHdaAudioLinkHda = config->PchHdaAudioLinkHda; params->PchHdaAudioLinkDmic0 = config->PchHdaAudioLinkDmic0; params->PchHdaAudioLinkDmic1 = config->PchHdaAudioLinkDmic1; -- To view, visit https://review.coreboot.org/c/coreboot/+/35078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8330f47416e580bf6b9ca1faed1de5cd578d0e2e Gerrit-Change-Number: 35078 Gerrit-PatchSet: 1 Gerrit-Owner: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit August 2019