coreboot-gerrit August 2019

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Change in coreboot[master]: soc/intel/skylake: Fix booting regression issue
by Subrata Banik (Code Review) 27 Aug '19

27 Aug '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35111 ) Change subject: soc/intel/skylake: Fix booting regression issue ...................................................................... soc/intel/skylake: Fix booting regression issue This patch fixes booting issue on soraka introduced by CB:34893 Change-Id: I53ca24cc8c71fe98dbd6abafa69da8f9046e6768 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/skylake/romstage/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/35111/1 diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc index e929eba..7bb9d4b 100644 --- a/src/soc/intel/skylake/romstage/Makefile.inc +++ b/src/soc/intel/skylake/romstage/Makefile.inc @@ -1,4 +1,4 @@ -romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += ../../../../cpu/intel/car/romstage.c +romstage-y += ../../../../cpu/intel/car/romstage.c romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += romstage.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage_fsp20.c romstage-y += systemagent.c -- To view, visit https://review.coreboot.org/c/coreboot/+/35111 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53ca24cc8c71fe98dbd6abafa69da8f9046e6768 Gerrit-Change-Number: 35111 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: build system: add kconfig/toada to tools list
by Patrick Georgi (Code Review) 27 Aug '19

27 Aug '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35107 ) Change subject: build system: add kconfig/toada to tools list ...................................................................... build system: add kconfig/toada to tools list Without this, we're lacking a serialization point in abuild when doing parallel builds. This manifests in parallel attempts to write the toada binary, which fails. Change-Id: Id6ebbb3750284225670608e4927d80c4eea96afb Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/35107/1 diff --git a/Makefile.inc b/Makefile.inc index ffb22d3..e560338 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -646,7 +646,7 @@ include util/crossgcc/Makefile.inc .PHONY: tools -tools: $(objutil)/kconfig/conf $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(ROMCC_BIN) $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL) +tools: $(objutil)/kconfig/conf $(objutil)/kconfig/toada $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(ROMCC_BIN) $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL) ########################################################################### # Common recipes for all stages -- To view, visit https://review.coreboot.org/c/coreboot/+/35107 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6ebbb3750284225670608e4927d80c4eea96afb Gerrit-Change-Number: 35107 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/asus/p2-99: Convert clone to variant
by Branden Waldner (Code Review) 27 Aug '19

27 Aug '19

Branden Waldner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/22977 ) Change subject: mb/asus/p2-99: Convert clone to variant ...................................................................... Patch Set 1: I meant to comment on this before it got abandoned, but didn't get around to it. I got an actual P2B board and I've recently tested both the P2B and P2-99 with this patch set cherry picked and it seems to work properly. Is the patch okay as is then? I wasn't comfortable with claiming the P2-99 was compatible with the P2B without testing it previously, but I can and have tested it now. -- To view, visit https://review.coreboot.org/c/coreboot/+/22977 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3318fb142baaf26bca55dd6917eae6211479f168 Gerrit-Change-Number: 22977 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Branden Waldner <scruffy99(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Aug 2019 00:43:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: intel/car: Use common TS_START_ROMSTAGE
by Kyösti Mälkki (Code Review) 27 Aug '19

27 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34970 ) Change subject: intel/car: Use common TS_START_ROMSTAGE ...................................................................... intel/car: Use common TS_START_ROMSTAGE This timestamp for unintentionally removed from cpu/haswell and cpu/model_1067x platforms with commit. Change-Id: I12be278a674f9a2ea073b170a223c41c7fc01a94 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/car/romstage.c M src/soc/intel/apollolake/romstage.c M src/soc/intel/cannonlake/romstage/romstage.c M src/soc/intel/icelake/romstage/romstage.c M src/soc/intel/skylake/romstage/romstage_fsp20.c 5 files changed, 2 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/34970/1 diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 9298676..5a1a4c4 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -83,6 +83,8 @@ asmlinkage void car_stage_entry(void) { + timestamp_add_now(TS_START_ROMSTAGE); + /* Assumes the hardware was set up during the bootblock */ console_init(); diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 2c28339..7e369f4 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -47,7 +47,6 @@ #include <soc/systemagent.h> #include <spi_flash.h> #include <timer.h> -#include <timestamp.h> #include "chip.h" static const uint8_t hob_variable_guid[16] = { @@ -199,8 +198,6 @@ struct chipset_power_state *ps = pmc_get_power_state(); const void *new_var_data; - timestamp_add_now(TS_START_ROMSTAGE); - soc_early_romstage_init(); s3wake = pmc_fill_power_state(ps) == ACPI_S3; diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index 5711c15..fb5e42b 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -28,7 +28,6 @@ #include <soc/pm.h> #include <soc/romstage.h> #include <string.h> -#include <timestamp.h> #include "../chip.h" @@ -137,7 +136,6 @@ /* initialize Heci interface */ heci_init(HECI1_BASE_ADDRESS); - timestamp_add_now(TS_START_ROMSTAGE); s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); pmc_set_disb(); diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c index 67ef2bb..a96f057 100644 --- a/src/soc/intel/icelake/romstage/romstage.c +++ b/src/soc/intel/icelake/romstage/romstage.c @@ -29,7 +29,6 @@ #include <soc/romstage.h> #include <soc/soc_chip.h> #include <string.h> -#include <timestamp.h> #define FSP_SMBIOS_MEMORY_INFO_GUID \ { \ @@ -121,7 +120,6 @@ /* initialize Heci interface */ heci_init(HECI1_BASE_ADDRESS); - timestamp_add_now(TS_START_ROMSTAGE); s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); pmc_set_disb(); diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 2412f22..5388858 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -32,7 +32,6 @@ #include <soc/pm.h> #include <soc/romstage.h> #include <string.h> -#include <timestamp.h> #include <security/vboot/vboot_common.h> #include "../chip.h" @@ -148,7 +147,6 @@ systemagent_early_init(); ps = pmc_get_power_state(); - timestamp_add_now(TS_START_ROMSTAGE); s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); pmc_set_disb(); -- To view, visit https://review.coreboot.org/c/coreboot/+/34970 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12be278a674f9a2ea073b170a223c41c7fc01a94 Gerrit-Change-Number: 34970 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: x86: Introduce RESET_VECTOR_IN_RAM option
by Kyösti Mälkki (Code Review) 27 Aug '19

27 Aug '19

Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/35004 ) Change subject: x86: Introduce RESET_VECTOR_IN_RAM option ...................................................................... x86: Introduce RESET_VECTOR_IN_RAM option Create a new Kconfig symbol that allows an x86 device to begin execution when its reset vector is in DRAM and not at the traditional 0xfffffff0. The implementation will follow later, this is just to setup various ENV_xxx definitions correctly for the build environment. Change-Id: I098ecf8bf200550db1e15f178f7661c1ac516dc5 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35004 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/arch/x86/Kconfig M src/arch/x86/memlayout.ld M src/include/rules.h M src/include/symbols.h 4 files changed, 21 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 2ace7f7..a7d10fb 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -81,6 +81,13 @@ default n depends on ARCH_X86 && SMP +config RESET_VECTOR_IN_RAM + bool + depends on ARCH_X86 + help + Select this option if the x86 soc implements custom code to handle the + reset vector in RAM instead of the traditional 0xfffffff0 location. + # Aligns 16bit entry code in bootblock so that hyper-threading CPUs # can boot AP CPUs to enable their shared caches. config SIPI_VECTOR_IN_ROM diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index cc72552..1e4ec0d 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -16,6 +16,15 @@ #include <memlayout.h> #include <arch/header.ld> +/* Pull in the either CAR or early DRAM rules. */ +#if ENV_ROMSTAGE_OR_BEFORE +#if ENV_CACHE_AS_RAM +#define EARLY_MEMLAYOUT "car.ld" +#else +#error "Early DRAM environment for x86 is work-in-progress. */ +#endif +#endif + SECTIONS { /* @@ -34,23 +43,20 @@ * Link at 32MiB address and rely on cbfstool to relocate to XIP. */ ROMSTAGE(CONFIG_ROMSTAGE_ADDR, 1M) - /* Pull in the cache-as-ram rules. */ - #include "car.ld" + #include EARLY_MEMLAYOUT #elif ENV_VERSTAGE /* The 1M size is not allocated. It's just for basic size checking. * Link at 32MiB address and rely on cbfstool to relocate to XIP. */ VERSTAGE(CONFIG_VERSTAGE_ADDR, 1M) - /* Pull in the cache-as-ram rules. */ - #include "car.ld" + #include EARLY_MEMLAYOUT #elif ENV_BOOTBLOCK /* This is for C_ENVIRONMENT_BOOTBLOCK. arch/x86/bootblock.ld contains * the logic for the romcc linking. */ BOOTBLOCK(0xffffffff - CONFIG_C_ENV_BOOTBLOCK_SIZE + 1, CONFIG_C_ENV_BOOTBLOCK_SIZE) - /* Pull in the cache-as-ram rules. */ - #include "car.ld" + #include EARLY_MEMLAYOUT #elif ENV_POSTCAR POSTCAR(32M, 1M) diff --git a/src/include/rules.h b/src/include/rules.h index 9fd7dc3..dc4210a 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -271,7 +271,7 @@ #if CONFIG(ARCH_X86) /* Indicates memory layout is determined with arch/x86/car.ld. */ -#define ENV_CACHE_AS_RAM ENV_ROMSTAGE_OR_BEFORE +#define ENV_CACHE_AS_RAM (ENV_ROMSTAGE_OR_BEFORE && !CONFIG(RESET_VECTOR_IN_RAM)) /* No .data sections with execute-in-place from ROM. */ #define ENV_STAGE_HAS_DATA_SECTION !ENV_CACHE_AS_RAM /* No .bss sections for stage with CAR teardown. */ diff --git a/src/include/symbols.h b/src/include/symbols.h index 76c9320..56df8d5 100644 --- a/src/include/symbols.h +++ b/src/include/symbols.h @@ -72,7 +72,7 @@ * (Does not necessarily mean that the memory is accessible.) */ static inline int preram_symbols_available(void) { - return !CONFIG(ARCH_X86) || ENV_CACHE_AS_RAM; + return !CONFIG(ARCH_X86) || ENV_ROMSTAGE_OR_BEFORE; } #endif /* __SYMBOLS_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35004 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I098ecf8bf200550db1e15f178f7661c1ac516dc5 Gerrit-Change-Number: 35004 Gerrit-PatchSet: 12 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: arch/x86: Simplify <arch/early_variables.h>
by Kyösti Mälkki (Code Review) 27 Aug '19

27 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35016 ) Change subject: arch/x86: Simplify <arch/early_variables.h> ...................................................................... arch/x86: Simplify <arch/early_variables.h> This also removes ENV_CACHE_AS_RAM and allows the use of .bss section for ENV_BOOTBLOCK and ENV_VERSTAGE even with CAR_GLOBAL_MIGRATION=y. In practice, boards with CAR_GLOBAL_MIGRATION=y currently build with romcc-bootblock so they will not be using .bss. Change-Id: Ie9dc14f3e528d3e4f48304f4d7de50df448a8af6 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/car.ld M src/arch/x86/include/arch/early_variables.h M src/cpu/x86/pae/pgtbl.c M src/include/rules.h M src/include/symbols.h 5 files changed, 21 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/35016/1 diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 5351fc7..641ae1f 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -76,8 +76,8 @@ * cbmem console. This is useful for clearing this area on a per-stage * basis when more than one stage uses cache-as-ram for CAR_GLOBALs. */ _car_global_start = .; -#if !CONFIG(CAR_GLOBAL_MIGRATION) - /* Allow global unitialized variables when CAR_GLOBALs are not used. */ +#if ENV_STAGE_HAS_BSS_SECTION + /* Allow global uninitialized variables for stages without CAR teardown. */ *(.bss) *(.bss.*) *(.sbss) diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h index 4860e49..e9e2610 100644 --- a/src/arch/x86/include/arch/early_variables.h +++ b/src/arch/x86/include/arch/early_variables.h @@ -20,7 +20,8 @@ #include <commonlib/helpers.h> #include <stdlib.h> -#if ENV_CACHE_AS_RAM && CONFIG(CAR_GLOBAL_MIGRATION) +#if ENV_ROMSTAGE && CONFIG(CAR_GLOBAL_MIGRATION) + asm(".section .car.global_data,\"w\",@nobits"); asm(".previous"); #ifdef __clang__ @@ -29,27 +30,6 @@ #define CAR_GLOBAL __attribute__((used, section(".car.global_data#"))) #endif /* __clang__ */ -/* - * In stages that use CAR (verstage, C bootblock) all CAR_GLOBAL variables are - * accessed unconditionally because cbmem is never initialized until romstage - * when dram comes up. - */ -#if !ENV_ROMSTAGE -static inline void *car_get_var_ptr(void *var) -{ - return var; -} - -static inline void *car_sync_var_ptr(void *var) -{ - return var; -} - -static inline int car_active(void) -{ - return 1; -} -#else /* Get the correct pointer for the CAR global variable. */ void *car_get_var_ptr(void *var); @@ -58,7 +38,6 @@ /* Return 1 when currently running with globals in Cache-as-RAM, 0 otherwise. */ int car_active(void); -#endif /* !ENV_ROMSTAGE */ /* Get and set a primitive type global variable. */ #define car_get_var(var) \ @@ -81,26 +60,25 @@ #else /* - * We might end up here if: - * 1. ENV_CACHE_AS_RAM is not set for the stage or - * 2. ENV_CACHE_AS_RAM is set for the stage but CONFIG_CAR_GLOBAL_MIGRATION - * is not set. In this case, there is no need to migrate CAR global - * variables. But, since we might still be running out of CAR, car_active needs - * to return 1 if ENV_CACHE_AS_RAM is set. + * For all stages other than romstage, all CAR_GLOBAL variables are accessed + * unconditionally as there is no migration of symbols. */ #define CAR_GLOBAL -static inline void *car_get_var_ptr(void *var) { return var; } - -#if ENV_CACHE_AS_RAM -static inline int car_active(void) { return 1; } -#else -static inline int car_active(void) { return 0; } -#endif /* ENV_CACHE_AS_RAM */ - #define car_get_var(var) (var) #define car_sync_var(var) (var) #define car_set_var(var, val) (var) = (val) -#endif /* ENV_CACHE_AS_RAM && CONFIG(CAR_GLOBAL_MIGRATION) */ + +static inline void *car_get_var_ptr(void *var) +{ + return var; +} + +static inline int car_active(void) +{ + return ENV_ROMSTAGE_OR_BEFORE; +} + +#endif #endif /* ARCH_EARLY_VARIABLES_H */ diff --git a/src/cpu/x86/pae/pgtbl.c b/src/cpu/x86/pae/pgtbl.c index f54a1c3..4673de6 100644 --- a/src/cpu/x86/pae/pgtbl.c +++ b/src/cpu/x86/pae/pgtbl.c @@ -363,7 +363,7 @@ int paging_enable_for_car(const char *pdpt_name, const char *pt_name) { - if (!ENV_CACHE_AS_RAM) + if (!preram_symbols_available()) return -1; if (read_from_cbfs(pdpt_name, _pdpt, REGION_SIZE(pdpt))) { @@ -383,7 +383,7 @@ static void *get_pdpt_addr(void) { - if (ENV_CACHE_AS_RAM) + if (preram_symbols_available()) return _pdpt; return (void *)(uintptr_t)read_cr3(); } diff --git a/src/include/rules.h b/src/include/rules.h index aec612e..e7ae05d 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -297,12 +297,4 @@ #define __SIMPLE_DEVICE__ #endif -/* x86 specific. Indicates that the current stage is running with cache-as-ram - * enabled from the beginning of the stage in C code. */ -#if defined(__PRE_RAM__) -#define ENV_CACHE_AS_RAM CONFIG(ARCH_X86) -#else -#define ENV_CACHE_AS_RAM 0 -#endif - #endif /* _RULES_H */ diff --git a/src/include/symbols.h b/src/include/symbols.h index 76c9320..56df8d5 100644 --- a/src/include/symbols.h +++ b/src/include/symbols.h @@ -72,7 +72,7 @@ * (Does not necessarily mean that the memory is accessible.) */ static inline int preram_symbols_available(void) { - return !CONFIG(ARCH_X86) || ENV_CACHE_AS_RAM; + return !CONFIG(ARCH_X86) || ENV_ROMSTAGE_OR_BEFORE; } #endif /* __SYMBOLS_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35016 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9dc14f3e528d3e4f48304f4d7de50df448a8af6 Gerrit-Change-Number: 35016 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: x86: Introduce RESET_VECTOR_IN_RAM option
by Julius Werner (Code Review) 27 Aug '19

27 Aug '19

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35004 ) Change subject: x86: Introduce RESET_VECTOR_IN_RAM option ...................................................................... Patch Set 11: Code-Review+2 (3 comments) https://review.coreboot.org/c/coreboot/+/35004/10/src/Kconfig File src/Kconfig: https://review.coreboot.org/c/coreboot/+/35004/10/src/Kconfig@155 PS10, Line 155: config RESET_VECTOR_IN_RAM > It can, if we feel no other arch would soon use it. […] I think I'd prefer _DRAM, but up to you. https://review.coreboot.org/c/coreboot/+/35004/11/src/arch/x86/Kconfig File src/arch/x86/Kconfig: https://review.coreboot.org/c/coreboot/+/35004/11/src/arch/x86/Kconfig@88 PS11, Line 88: soc nit: SoC or SOC https://review.coreboot.org/c/coreboot/+/35004/10/src/arch/x86/memlayout.ld File src/arch/x86/memlayout.ld: https://review.coreboot.org/c/coreboot/+/35004/10/src/arch/x86/memlayout.ld… PS10, Line 20: #if ENV_ROMSTAGE_OR_BEFORE > I would hit #error below for every !ENV_ROMSTAGE_OR_BEFORE ? Oh, right, okay. Would maybe be nice to indent the inner ones for readability. -- To view, visit https://review.coreboot.org/c/coreboot/+/35004 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I098ecf8bf200550db1e15f178f7661c1ac516dc5 Gerrit-Change-Number: 35004 Gerrit-PatchSet: 11 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 26 Aug 2019 22:43:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: what-jenkins-does: keep essential artifacts arounds
by Patrick Georgi (Code Review) 26 Aug '19

26 Aug '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35099 ) Change subject: what-jenkins-does: keep essential artifacts arounds ...................................................................... what-jenkins-does: keep essential artifacts arounds Keep for every board: coreboot.rom, config.h, config.build That way these can be used in follow-up jobs. Change-Id: I5ca5cb84ab1bcffbc92a972980cd0769ebf02462 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M util/testing/Makefile.inc 1 file changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/35099/1 diff --git a/util/testing/Makefile.inc b/util/testing/Makefile.inc index d84c5a4..99f7922 100644 --- a/util/testing/Makefile.inc +++ b/util/testing/Makefile.inc @@ -80,7 +80,7 @@ lint lint-stable lint-extended: util/lint/lint $@ -ABUILD_OPTIONS=-B -J -c $(CPUS) -z -p $(JENKINS_PAYLOAD) +ABUILD_OPTIONS=-B -J -c $(CPUS) -p $(JENKINS_PAYLOAD) ABUILD_OPTIONS+=$(if $(V),-v,) ABUILD_OPTIONS+=$(if $(JENKINS_NOCCACHE),,-y) ABUILD_OPTIONS+=$(JENKINS_ABUILD_OPT) @@ -88,8 +88,9 @@ what-jenkins-does: util/lint/lint lint-stable --junit util/lint/lint lint-extended --junit - util/abuild/abuild $(ABUILD_OPTIONS) -x -X $(top)/abuild-chromeos.xml - util/abuild/abuild $(ABUILD_OPTIONS) + COREBOOT_BUILD_DIR=coreboot-builds-chromeos util/abuild/abuild $(ABUILD_OPTIONS) -x -X $(top)/abuild-chromeos.xml + COREBOOT_BUILD_DIR=coreboot-builds util/abuild/abuild $(ABUILD_OPTIONS) + -find coreboot-builds{,-chromeos}/[A-Z]*/* \! $ -name coreboot.rom -o -name config.h -o -name config.build $ -type f -exec rm {} +; find coreboot-builds{,-chromeos}/[A-Z]*/* -type d -exec rmdir -p {} + 2>/dev/null $(foreach tool, $(TOOLLIST), $(MAKE) CPUS=$(CPUS) V=$(V) Q=$(Q) BLD_DIR="util/$(tool)" BLD="$(tool)" MFLAGS= MAKEFLAGS= MAKETARGET= junit.xml; ) unset COREBOOT_BUILD_DIR;$(MAKE) CPUS=$(CPUS) V=$(V) Q=$(Q) BLD_DIR=payloads/nvramcui BLD=nvramcui MFLAGS= MAKEFLAGS= MAKETARGET=all junit.xml unset COREBOOT_BUILD_DIR;$(MAKE) CPUS=$(CPUS) V=$(V) Q=$(Q) BLD_DIR=payloads/coreinfo BLD=coreinfo MFLAGS= MAKEFLAGS= MAKETARGET=defaultbuild junit.xml -- To view, visit https://review.coreboot.org/c/coreboot/+/35099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ca5cb84ab1bcffbc92a972980cd0769ebf02462 Gerrit-Change-Number: 35099 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: x86: Introduce RESET_VECTOR_IN_RAM option
by Kyösti Mälkki (Code Review) 26 Aug '19

26 Aug '19

Hello Aaron Durbin, Julius Werner, Marshall Dawson, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35004 to look at the new patch set (#11). Change subject: x86: Introduce RESET_VECTOR_IN_RAM option ...................................................................... x86: Introduce RESET_VECTOR_IN_RAM option Create a new Kconfig symbol that allows an x86 device to begin execution when its reset vector is in DRAM and not at the traditional 0xfffffff0. The implementation will follow later, this is just to setup various ENV_xxx definitions correctly for the build environment. Change-Id: I098ecf8bf200550db1e15f178f7661c1ac516dc5 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/Kconfig M src/arch/x86/memlayout.ld M src/include/rules.h M src/include/symbols.h 4 files changed, 21 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/35004/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/35004 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I098ecf8bf200550db1e15f178f7661c1ac516dc5 Gerrit-Change-Number: 35004 Gerrit-PatchSet: 11 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: emulation/qemu-x86: Rename memory.c to memmap.c
by Kyösti Mälkki (Code Review) 26 Aug '19

26 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34974 ) Change subject: emulation/qemu-x86: Rename memory.c to memmap.c ...................................................................... emulation/qemu-x86: Rename memory.c to memmap.c Change-Id: I311423cb565485236f89bd6043155aaf6296a031 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/emulation/qemu-i440fx/Makefile.inc R src/mainboard/emulation/qemu-i440fx/memmap.c M src/mainboard/emulation/qemu-q35/Makefile.inc 3 files changed, 18 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/34974/1 diff --git a/src/mainboard/emulation/qemu-i440fx/Makefile.inc b/src/mainboard/emulation/qemu-i440fx/Makefile.inc index e3ca300..cac74ee 100644 --- a/src/mainboard/emulation/qemu-i440fx/Makefile.inc +++ b/src/mainboard/emulation/qemu-i440fx/Makefile.inc @@ -1,8 +1,10 @@ -ramstage-y += northbridge.c -ramstage-y += fw_cfg.c romstage-y += fw_cfg.c -romstage-y += memory.c -ramstage-y += memory.c -postcar-y += memory.c +romstage-y += memmap.c + postcar-y += fw_cfg.c +postcar-y += memmap.c postcar-y += exit_car.S + +ramstage-y += fw_cfg.c +ramstage-y += memmap.c +ramstage-y += northbridge.c diff --git a/src/mainboard/emulation/qemu-i440fx/memory.c b/src/mainboard/emulation/qemu-i440fx/memmap.c similarity index 100% rename from src/mainboard/emulation/qemu-i440fx/memory.c rename to src/mainboard/emulation/qemu-i440fx/memmap.c diff --git a/src/mainboard/emulation/qemu-q35/Makefile.inc b/src/mainboard/emulation/qemu-q35/Makefile.inc index b18d2e4..133a213 100644 --- a/src/mainboard/emulation/qemu-q35/Makefile.inc +++ b/src/mainboard/emulation/qemu-q35/Makefile.inc @@ -1,11 +1,12 @@ -ramstage-y += ../qemu-i440fx/northbridge.c -ramstage-y += ../qemu-i440fx/memory.c -ramstage-y += ../qemu-i440fx/fw_cfg.c -romstage-y += ../qemu-i440fx/memory.c -romstage-y += ../qemu-i440fx/fw_cfg.c - -postcar-y += ../qemu-i440fx/memory.c -postcar-y += ../qemu-i440fx/exit_car.S -postcar-y += ../qemu-i440fx/fw_cfg.c - bootblock-y += bootblock.c + +romstage-y += ../qemu-i440fx/fw_cfg.c +romstage-y += ../qemu-i440fx/memmap.c + +postcar-y += ../qemu-i440fx/fw_cfg.c +postcar-y += ../qemu-i440fx/memmap.c +postcar-y += ../qemu-i440fx/exit_car.S + +ramstage-y += ../qemu-i440fx/fw_cfg.c +ramstage-y += ../qemu-i440fx/memmap.c +ramstage-y += ../qemu-i440fx/northbridge.c -- To view, visit https://review.coreboot.org/c/coreboot/+/34974 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I311423cb565485236f89bd6043155aaf6296a031 Gerrit-Change-Number: 34974 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit August 2019