coreboot-gerrit August 2019

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Change in coreboot[master]: arch/x86: Simplified postcar WB MTRR setup
by Kyösti Mälkki (Code Review) 27 Aug '19

27 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34897 ) Change subject: arch/x86: Simplified postcar WB MTRR setup ...................................................................... arch/x86: Simplified postcar WB MTRR setup Change-Id: I8822c4dcdced872a19ac183b993e8885aadd0a2c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/skylake/memmap.c 1 file changed, 25 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/34897/1 diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index e3590fd..3d8f989 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -290,11 +290,10 @@ return (void *)(uintptr_t)ebda_cfg.tolum_base; } -void fill_postcar_frame(struct postcar_frame *pcf) +static void postcar_wb_region(uintptr_t *start, size_t *size) { - uintptr_t top_of_ram; - uintptr_t smm_base; - size_t smm_size; + uintptr_t wb_start, wb_end; + size_t wb_size; /* * We need to make sure ramstage will be run cached. At this @@ -302,10 +301,8 @@ * Instruct postcar to cache 16 megs under cbmem top which is * a safe bet to cover ramstage. */ - top_of_ram = (uintptr_t) cbmem_top(); - printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); - top_of_ram -= 16*MiB; - postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); + wb_start = (uintptr_t) cbmem_top(); + wb_start -= 16 * MiB; /* * Cache the TSEG region at the top of ram. This region is @@ -314,6 +311,24 @@ * when relocating the SMM handler as well as using the TSEG * region for other purposes. */ - smm_region(&smm_base, &smm_size); - postcar_frame_add_mtrr(pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); + smm_region(&wb_end, &wb_size); + wb_end += wb_size; + + /* Do some magic alignments */ + wb_start = ALIGN_DOWN(wb_start, x); + wb_end = ALIGN_UP(wb_end, x); + wb_size = wb_end - wb_start; + + /* Return one continuos region allowed for WB. */ + *start = wb_start; + *size = wb_size; +} + +void fill_postcar_frame(struct postcar_frame *pcf) +{ + uintptr_t wb_start; + size_t wb_size; + + postcar_wb_region(&wb_start, &wb_size); + postcar_frame_add_mtrr(pcf, wb_start, wb_size, MTRR_TYPE_WRBACK); } -- To view, visit https://review.coreboot.org/c/coreboot/+/34897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8822c4dcdced872a19ac183b993e8885aadd0a2c Gerrit-Change-Number: 34897 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 13

Change in coreboot[master]: intel/baytrail: Use smm_subregion()
by Kyösti Mälkki (Code Review) 27 Aug '19

27 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34739 ) Change subject: intel/baytrail: Use smm_subregion() ...................................................................... intel/baytrail: Use smm_subregion() Change-Id: Ic2677bcf9f2f79c4db725ebcf342a8575ee7bc38 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/baytrail/cpu.c M src/soc/intel/baytrail/memmap.c 2 files changed, 61 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/34739/1 diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index 9526932..2e14270 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -86,13 +86,12 @@ * MP and SMM loading initialization. */ -struct smm_relocation_attrs { - uint32_t smbase; - uint32_t smrr_base; - uint32_t smrr_mask; +struct smm_relocation_params { + msr_t smrr_base; + msr_t smrr_mask; }; -static struct smm_relocation_attrs relo_attrs; +static struct smm_relocation_params smm_reloc_params; /* Package level MSRs */ static const struct reg_script package_msr_script[] = { @@ -138,21 +137,33 @@ return pattrs->num_cpus; } +static void fill_in_relocation_params(struct smm_relocation_params *params) +{ + uintptr_t tseg_base; + size_t tseg_size; + + /* All range registers are aligned to 4KiB */ + const u32 rmask = ~((1 << 12) - 1); + + smm_region(&tseg_base, &tseg_size); + + /* SMRR has 32-bits of valid address aligned to 4KiB. */ + params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK; + params->smrr_base.hi = 0; + params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; + params->smrr_mask.hi = 0; +} + static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { - /* All range registers are aligned to 4KiB */ - const uint32_t rmask = ~((1 << 12) - 1); + printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - /* Initialize global tracking state. */ - relo_attrs.smbase = (uint32_t)smm_region_start(); - relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK; - relo_attrs.smrr_mask = ~(smm_region_size() - 1) & rmask; - relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID; + fill_in_relocation_params(&smm_reloc_params); - *perm_smbase = relo_attrs.smbase; - *perm_smsize = smm_region_size() - CONFIG_SMM_RESERVED_SIZE; - *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t); + smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); + + *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t); } static void get_microcode_info(const void **microcode, int *parallel) @@ -177,16 +188,12 @@ static void relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase) { - msr_t smrr; + struct smm_relocation_params *relo_params = &smm_reloc_params; em64t100_smm_state_save_area_t *smm_state; /* Set up SMRR. */ - smrr.lo = relo_attrs.smrr_base; - smrr.hi = 0; - wrmsr(IA32_SMRR_PHYS_BASE, smrr); - smrr.lo = relo_attrs.smrr_mask; - smrr.hi = 0; - wrmsr(IA32_SMRR_PHYS_MASK, smrr); + wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); + wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase); smm_state->smbase = staggered_smbase; diff --git a/src/soc/intel/baytrail/memmap.c b/src/soc/intel/baytrail/memmap.c index 94e91ca..c502270 100644 --- a/src/soc/intel/baytrail/memmap.c +++ b/src/soc/intel/baytrail/memmap.c @@ -14,7 +14,7 @@ */ #include <cbmem.h> -#include <stage_cache.h> +#include <cpu/x86/smm.h> #include <soc/iosf.h> #include <soc/smm.h> @@ -28,15 +28,37 @@ return (void *) smm_region_start(); } -void stage_cache_external_region(void **base, size_t *size) +void smm_region(uintptr_t *start, size_t *size) { - char *smm_base; - /* 1MiB cache size */ - const long cache_size = CONFIG_SMM_RESERVED_SIZE; + *start = (iosf_bunit_read(BUNIT_SMRRL) & 0xFFFF) << 20; + *size = smm_region_size(); +} - /* Ramstage cache lives in TSEG region which is the definition of - * cbmem_top(). */ - smm_base = cbmem_top(); - *size = cache_size; - *base = &smm_base[smm_region_size() - cache_size]; +int smm_subregion(int sub, uintptr_t *start, size_t *size) +{ + uintptr_t sub_base; + size_t sub_size; + const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; + + smm_region(&sub_base, &sub_size); + + switch (sub) { + case SMM_SUBREGION_HANDLER: + /* Handler starts at the base of TSEG. */ + sub_size -= cache_size; + break; + case SMM_SUBREGION_CACHE: + /* External cache is in the middle of TSEG. */ + sub_base += sub_size - cache_size; + sub_size = cache_size; + break; + default: + *start = 0; + *size = 0; + return -1; + } + + *start = sub_base; + *size = sub_size; + return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/34739 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2677bcf9f2f79c4db725ebcf342a8575ee7bc38 Gerrit-Change-Number: 34739 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: intel/baytrail: Reorganize romstage.c
by Kyösti Mälkki (Code Review) 27 Aug '19

27 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34910 ) Change subject: intel/baytrail: Reorganize romstage.c ...................................................................... intel/baytrail: Reorganize romstage.c Done just for future review convenience. Change-Id: I9cfb0a8177c8ca18947ef0109550a36aa4333383 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/baytrail/romstage/romstage.c 1 file changed, 74 insertions(+), 74 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/34910/1 diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index d3ea84e..834a8bc 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -40,33 +40,6 @@ #include <soc/romstage.h> #include <soc/spi.h> -/* The cache-as-ram assembly file calls romstage_main() after setting up - * cache-as-ram. romstage_main() will then call the mainboards's - * mainboard_romstage_entry() function. That function then calls - * romstage_common() below. The reason for the back and forth is to provide - * common entry point from cache-as-ram while still allowing for code sharing. - * Because we can't use global variables the stack is used for allocations -- - * thus the need to call back and forth. */ - -static struct postcar_frame early_mtrrs; - -static void fill_postcar_frame(struct postcar_frame *pcf); - -/* prepare_and_run_postcar() determines the stack to use after - * cache-as-ram is torn down as well as the MTRR settings to use. */ -static void prepare_and_run_postcar(struct postcar_frame *pcf) -{ - if (postcar_frame_init(pcf, 0)) - die("Unable to initialize postcar frame.\n"); - - fill_postcar_frame(pcf); - - postcar_frame_common_mtrrs(pcf); - - run_postcar_phase(pcf); - /* We do not return here. */ -} - static void program_base_addresses(void) { uint32_t reg; @@ -112,53 +85,6 @@ write32(bcr, reg); } -/* Entry from cache-as-ram.inc. */ -static void romstage_main(uint64_t tsc) -{ - struct romstage_params rp = { - .mrc_params = NULL, - }; - - /* Save initial timestamp from bootblock. */ - timestamp_init(tsc); - - /* Save romstage begin */ - timestamp_add_now(TS_START_ROMSTAGE); - - program_base_addresses(); - - tco_disable(); - - byt_config_com1_and_enable(); - - console_init(); - - spi_init(); - - set_max_freq(); - - punit_init(); - - gfx_init(); - - /* Call into mainboard. */ - mainboard_romstage_entry_rp(&rp); - - if (CONFIG(SMM_TSEG)) - smm_list_regions(); - - prepare_and_run_postcar(&early_mtrrs); - /* We do not return here. */ -} - -/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK, - * keeping changes in cache_as_ram.S easy to manage. - */ -asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) -{ - romstage_main(base_timestamp); -} - static struct chipset_power_state power_state; static void migrate_power_state(int is_recovery) @@ -228,6 +154,72 @@ return prev_sleep_state; } +/* The cache-as-ram assembly file calls romstage_main() after setting up + * cache-as-ram. romstage_main() will then call the mainboards's + * mainboard_romstage_entry() function. That function then calls + * romstage_common() below. The reason for the back and forth is to provide + * common entry point from cache-as-ram while still allowing for code sharing. + * Because we can't use global variables the stack is used for allocations -- + * thus the need to call back and forth. */ + +static struct postcar_frame early_mtrrs; + +static void fill_postcar_frame(struct postcar_frame *pcf); + +/* prepare_and_run_postcar() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use. */ +static void prepare_and_run_postcar(struct postcar_frame *pcf) +{ + if (postcar_frame_init(pcf, 0)) + die("Unable to initialize postcar frame.\n"); + + fill_postcar_frame(pcf); + + postcar_frame_common_mtrrs(pcf); + + run_postcar_phase(pcf); + /* We do not return here. */ +} + +/* Entry from cache-as-ram.inc. */ +static void romstage_main(uint64_t tsc) +{ + struct romstage_params rp = { + .mrc_params = NULL, + }; + + /* Save initial timestamp from bootblock. */ + timestamp_init(tsc); + + /* Save romstage begin */ + timestamp_add_now(TS_START_ROMSTAGE); + + program_base_addresses(); + + tco_disable(); + + byt_config_com1_and_enable(); + + console_init(); + + spi_init(); + + set_max_freq(); + + punit_init(); + + gfx_init(); + + /* Call into mainboard. */ + mainboard_romstage_entry_rp(&rp); + + if (CONFIG(SMM_TSEG)) + smm_list_regions(); + + prepare_and_run_postcar(&early_mtrrs); + /* We do not return here. */ +} + /* Entry from the mainboard. */ void romstage_common(struct romstage_params *params) { @@ -255,6 +247,14 @@ romstage_handoff_init(prev_sleep_state == ACPI_S3); } +/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK, + * keeping changes in cache_as_ram.S easy to manage. + */ +asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) +{ + romstage_main(base_timestamp); +} + static void fill_postcar_frame(struct postcar_frame *pcf) { uintptr_t top_of_ram; -- To view, visit https://review.coreboot.org/c/coreboot/+/34910 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cfb0a8177c8ca18947ef0109550a36aa4333383 Gerrit-Change-Number: 34910 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: nb/intel/x4x/raminit: Move dummy reads after JEDEC init
by Paul Menzel (Code Review) 27 Aug '19

27 Aug '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/20979 ) Change subject: nb/intel/x4x/raminit: Move dummy reads after JEDEC init ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/c/coreboot/+/20979/8//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/20979/8//COMMIT_MSG@14 PS8, Line 14: ready. > <rant> […] Makes sense. I was just curious. -- To view, visit https://review.coreboot.org/c/coreboot/+/20979 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8069f9c08ad5e5268ddbe3711d58bc42522f938c Gerrit-Change-Number: 20979 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Aug 2019 11:54:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: smsc/superio/sio1007: Fix header name
by Kyösti Mälkki (Code Review) 27 Aug '19

27 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35095 ) Change subject: smsc/superio/sio1007: Fix header name ...................................................................... smsc/superio/sio1007: Fix header name The file chip.h has a special purpose for defining the configuration structure used in static devicetree. Change-Id: If0289c29ca72768009c1b7166311bc4c3cee4171 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/compulab/intense_pc/romstage.c M src/mainboard/intel/emeraldlake2/romstage.c M src/superio/smsc/sio1007/early_serial.c R src/superio/smsc/sio1007/sio1007.h 4 files changed, 7 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/35095/1 diff --git a/src/mainboard/compulab/intense_pc/romstage.c b/src/mainboard/compulab/intense_pc/romstage.c index 6c3d980..74f00c2 100644 --- a/src/mainboard/compulab/intense_pc/romstage.c +++ b/src/mainboard/compulab/intense_pc/romstage.c @@ -17,7 +17,7 @@ #include <arch/io.h> #include <device/pci_ops.h> #include <northbridge/intel/sandybridge/raminit_native.h> -#include <superio/smsc/sio1007/chip.h> +#include <superio/smsc/sio1007/sio1007.h> #include <southbridge/intel/bd82x6x/pch.h> #define SIO_PORT 0x164e diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index a28ae78..ee3cec1 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -19,7 +19,7 @@ #include <device/pci_ops.h> #include <device/pci_def.h> #include <cpu/x86/lapic.h> -#include <superio/smsc/sio1007/chip.h> +#include <superio/smsc/sio1007/sio1007.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit_native.h> diff --git a/src/superio/smsc/sio1007/early_serial.c b/src/superio/smsc/sio1007/early_serial.c index 022a1ab..2028e67 100644 --- a/src/superio/smsc/sio1007/early_serial.c +++ b/src/superio/smsc/sio1007/early_serial.c @@ -15,7 +15,7 @@ #include <stdint.h> #include <arch/io.h> -#include "chip.h" +#include "sio1007.h" void sio1007_setreg(u16 lpc_port, u8 reg, u8 value, u8 mask) { diff --git a/src/superio/smsc/sio1007/chip.h b/src/superio/smsc/sio1007/sio1007.h similarity index 86% rename from src/superio/smsc/sio1007/chip.h rename to src/superio/smsc/sio1007/sio1007.h index 78ac18a..a99ec5c 100644 --- a/src/superio/smsc/sio1007/chip.h +++ b/src/superio/smsc/sio1007/sio1007.h @@ -13,10 +13,11 @@ * GNU General Public License for more details. */ -#ifndef SUPERIO_SMSC_1007_CHIP_H -#define SUPERIO_SMSC_1007_CHIP_H +#ifndef SUPERIO_SMSC_SIO1007_H +#define SUPERIO_SMSC_SIO1007_H -/* FIXME: wrong place for this! */ +#include <stdint.h> + void sio1007_setreg(u16 lpc_port, u8 reg, u8 value, u8 mask); int sio1007_enable_uart_at(u16 port); -- To view, visit https://review.coreboot.org/c/coreboot/+/35095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0289c29ca72768009c1b7166311bc4c3cee4171 Gerrit-Change-Number: 35095 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

5 5

Change in coreboot[master]: coreboot-sdk: Build Clang first in a separate step
by Paul Menzel (Code Review) 27 Aug '19

27 Aug '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29455 ) Change subject: coreboot-sdk: Build Clang first in a separate step ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/29455 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If67b458cde656f1dc6774215f6a575a48d12b797 Gerrit-Change-Number: 29455 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Aug 2019 11:36:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/fsp_broadwell_de: Add ACPI HPET table
by Patrick Georgi (Code Review) 27 Aug '19

27 Aug '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/35027 ) Change subject: soc/intel/fsp_broadwell_de: Add ACPI HPET table ...................................................................... soc/intel/fsp_broadwell_de: Add ACPI HPET table Tested on Mono Lake TEST=Note the kernel log: hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0, 0, 0, 0, 0 hpet0: 8 comparators, 64-bit 14.318180 MHz counter Change-Id: Idae9a7d3d4233037214d6203996bf44fe5f3a845 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35027 Reviewed-by: Johnny Lin Reviewed-by: Andrey Petrov <anpetrov(a)fb.com> Reviewed-by: David Hendricks <david.hendricks(a)gmail.com> Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/fsp_broadwell_de/Kconfig M src/soc/intel/fsp_broadwell_de/acpi.c M src/soc/intel/fsp_broadwell_de/include/soc/acpi.h M src/soc/intel/fsp_broadwell_de/southcluster.c 4 files changed, 20 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified David Hendricks: Looks good to me, but someone else must approve Patrick Rudolph: Looks good to me, but someone else must approve Andrey Petrov: Looks good to me, approved Johnny Lin: Looks good to me, but someone else must approve diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig index fef7a82..c388525 100644 --- a/src/soc/intel/fsp_broadwell_de/Kconfig +++ b/src/soc/intel/fsp_broadwell_de/Kconfig @@ -92,6 +92,10 @@ int default 512 +config HPET_MIN_TICKS + hex + default 0x80 + ## Broadwell-DE Specific FSP Kconfig source src/soc/intel/fsp_broadwell_de/fsp/Kconfig diff --git a/src/soc/intel/fsp_broadwell_de/acpi.c b/src/soc/intel/fsp_broadwell_de/acpi.c index fef7773..6b1d3f6 100644 --- a/src/soc/intel/fsp_broadwell_de/acpi.c +++ b/src/soc/intel/fsp_broadwell_de/acpi.c @@ -566,3 +566,14 @@ return current; } + +unsigned long southcluster_write_acpi_tables(struct device *device, + unsigned long current, + acpi_rsdp_t *rsdp) +{ + current = acpi_write_hpet(device, current, rsdp); + current = acpi_align_current(current); + + printk(BIOS_DEBUG, "current = %lx\n", current); + return current; +} diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/acpi.h b/src/soc/intel/fsp_broadwell_de/include/soc/acpi.h index da30252..44e17d0 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/acpi.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/acpi.h @@ -27,5 +27,7 @@ unsigned long vtd_write_acpi_tables(struct device *const dev, unsigned long current, struct acpi_rsdp *const rsdp); - +unsigned long southcluster_write_acpi_tables(struct device *device, + unsigned long start, + acpi_rsdp_t *rsdp); #endif /* _SOC_ACPI_H_ */ diff --git a/src/soc/intel/fsp_broadwell_de/southcluster.c b/src/soc/intel/fsp_broadwell_de/southcluster.c index 2f87cad..599b8c5 100644 --- a/src/soc/intel/fsp_broadwell_de/southcluster.c +++ b/src/soc/intel/fsp_broadwell_de/southcluster.c @@ -32,7 +32,7 @@ #include <soc/lpc.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> - +#include <soc/acpi.h> #include "chip.h" typedef struct soc_intel_fsp_broadwell_de_config config_t; @@ -277,6 +277,7 @@ .read_resources = sc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = NULL, + .write_acpi_tables = southcluster_write_acpi_tables, .init = sc_init, .enable = southcluster_enable_dev, .scan_bus = scan_lpc_bus, -- To view, visit https://review.coreboot.org/c/coreboot/+/35027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idae9a7d3d4233037214d6203996bf44fe5f3a845 Gerrit-Change-Number: 35027 Gerrit-PatchSet: 4 Gerrit-Owner: Johnny Lin Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: David Hendricks <dhendrix.sync(a)gmail.com> Gerrit-Reviewer: Johnny Lin Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Name of user not set #1002539 Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: Łukasz Siudut Gerrit-MessageType: merged

1 0

Change in ...coreboot[master]: soc/sifive/fu540: add support boot from sdcard
by Xiang Wang (Code Review) 27 Aug '19

27 Aug '19

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30901 Change subject: soc/sifive/fu540: add support boot from sdcard ...................................................................... soc/sifive/fu540: add support boot from sdcard Change-Id: Id97d293aee33082191cfaf47844769bdfa3d7a1b Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/mainboard/sifive/hifive-unleashed/Makefile.inc D src/mainboard/sifive/hifive-unleashed/bootblock.c A src/mainboard/sifive/hifive-unleashed/media.c M src/soc/sifive/fu540/Makefile.inc M src/soc/sifive/fu540/include/soc/memlayout.ld A src/soc/sifive/fu540/include/soc/sd.h D src/soc/sifive/fu540/media.c A src/soc/sifive/fu540/sd.c 8 files changed, 490 insertions(+), 58 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/30901/1 diff --git a/src/mainboard/sifive/hifive-unleashed/Makefile.inc b/src/mainboard/sifive/hifive-unleashed/Makefile.inc index 2dac283..54d97f7 100644 --- a/src/mainboard/sifive/hifive-unleashed/Makefile.inc +++ b/src/mainboard/sifive/hifive-unleashed/Makefile.inc @@ -11,12 +11,26 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. +bootblock-y += memlayout.ld bootblock-y += flash.c -bootblock-y += bootblock.c +bootblock-y += media.c +romstage-y += memlayout.ld romstage-y += flash.c +romstage-y += media.c romstage-y += romstage.c -bootblock-y += memlayout.ld -romstage-y += memlayout.ld ramstage-y += memlayout.ld +ramstage-y += flash.c +ramstage-y += media.c + + +DTB=build/hifive-unleashed.dtb +DTS=src/mainboard/sifive/hifive-unleashed/hifive-unleashed.dts +$(DTB): $(DTS) + dtc -I dts -O dtb -o $(DTB) $(DTS) + +cbfs-files-y += fallback/DTB +fallback/DTB-file := $(DTB) +fallback/DTB-type := raw + diff --git a/src/mainboard/sifive/hifive-unleashed/bootblock.c b/src/mainboard/sifive/hifive-unleashed/bootblock.c deleted file mode 100644 index 777b2aa..0000000 --- a/src/mainboard/sifive/hifive-unleashed/bootblock.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 HardenedLinux - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <soc/addressmap.h> -#include <soc/spi.h> -#include <soc/spi_flash.h> -#include <soc/clock.h> - -extern void flash_init(void); -extern void bootblock_mainboard_init(void); - -void bootblock_mainboard_init(void) -{ - flash_init(); -} diff --git a/src/mainboard/sifive/hifive-unleashed/media.c b/src/mainboard/sifive/hifive-unleashed/media.c new file mode 100644 index 0000000..4a8f463 --- /dev/null +++ b/src/mainboard/sifive/hifive-unleashed/media.c @@ -0,0 +1,123 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 HardenedLinux + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boot_device.h> +#include <symbols.h> +#include <cbfs.h> +#include <arch/io.h> +#include <soc/addressmap.h> +#include <soc/spi.h> +#include <soc/sd.h> +#include <soc/clock.h> +#include <console/console.h> +#include <string.h> + +void flash_init(void); +// void boot_device_init(void); +// const struct region_device *boot_device_ro(void); + +/* At 0x20000000: A 256MiB long memory-mapped view of the flash at QSPI0 */ +static struct mem_region_device spi_mdev = + MEM_REGION_DEV_RO_INIT((void *)0x20000000, CONFIG_ROM_SIZE); + +static ssize_t unleashed_sd_readat(const struct region_device *rdev, void *dest, + size_t offset, size_t count) +{ + if (offset / 512 == (offset + count - 1) / 512) { + size_t lba = offset / 512; + size_t o = offset % 512; + size_t l = count; + uint8_t tmp[512]; + if (sd_copy((spi_ctrl*)FU540_QSPI2, tmp, lba, 1) != 0) { + return -1; + } + memcpy(dest, tmp + o, l); + } else { + int has_begin = !!(offset % 512); + int has_end = !!((offset + count) % 512); + size_t first_lba = offset / 512; + size_t last_lba = (offset + count - 1) / 512; + if (has_begin) { + size_t lba = first_lba; + size_t o = offset % 512; + size_t l = 512 - o; + uint8_t tmp[512]; + if (sd_copy((spi_ctrl*)FU540_QSPI2, tmp, lba, 1) != 0) { + return -1; + } + memcpy(dest, tmp + o, l); + } + if (first_lba + has_begin <= last_lba - has_end) { + size_t lba = first_lba + has_begin; + size_t size = (last_lba - has_end) - (first_lba + has_begin) + 1; + size_t o = 512 - offset % 512; + if (sd_copy((spi_ctrl*)FU540_QSPI2, dest + o, lba, size) != 0) { + return -1; + } + } + if (has_end) { + size_t lba = last_lba; + size_t o = 0; + size_t l = (offset + count) % 512; + uint8_t tmp[512]; + if (sd_copy((spi_ctrl*)FU540_QSPI2, tmp, lba, 1) != 0) { + return -1; + } + memcpy(dest + count - l, tmp + o, l); + } + } + return count; +} + +static const struct region_device_ops unleashed_sd_ops = { + .mmap = mmap_helper_rdev_mmap, + .munmap = mmap_helper_rdev_munmap, + .readat = unleashed_sd_readat, +}; + + +static struct mmap_helper_region_device sd_mdev = + MMAP_HELPER_REGION_INIT(&unleashed_sd_ops, 0, CONFIG_ROM_SIZE); + + +const struct region_device *boot_device_ro() +{ + switch(read32((uint32_t *)FU540_MSEL)) { + case 6: + case 10: + case 15: + return &spi_mdev.rdev; + case 11: + return &sd_mdev.rdev; + } + return NULL; +} + +void boot_device_init() +{ + switch(read32((uint32_t *)FU540_MSEL)) { + case 6: + case 10: + case 15: + flash_init(); + break; + case 11: + sd_init((spi_ctrl*)FU540_QSPI2, clock_get_tlclk_khz()); + mmap_helper_device_init(&sd_mdev, _cbfs_cache, _cbfs_cache_size); + break; + default: + die("Wrong configuration of MSEL"); + } +} diff --git a/src/soc/sifive/fu540/Makefile.inc b/src/soc/sifive/fu540/Makefile.inc index 83c7b1c..866267e 100644 --- a/src/soc/sifive/fu540/Makefile.inc +++ b/src/soc/sifive/fu540/Makefile.inc @@ -15,28 +15,31 @@ bootblock-y += uart.c bootblock-y += clint.c -bootblock-y += media.c +# bootblock-y += media.c bootblock-y += bootblock.c bootblock-y += clock.c bootblock-y += spi.c +bootblock-y += sd.c romstage-y += uart.c romstage-y += clint.c -romstage-y += media.c +# romstage-y += media.c romstage-y += sdram.c romstage-y += cbmem.c romstage-y += otp.c romstage-y += clock.c romstage-y += spi.c +romstage-y += sd.c ramstage-y += uart.c ramstage-y += clint.c -ramstage-y += media.c +# ramstage-y += media.c ramstage-y += sdram.c ramstage-y += cbmem.c ramstage-y += otp.c ramstage-y += clock.c ramstage-y += spi.c +ramstage-y += sd.c CPPFLAGS_common += -Isrc/soc/sifive/fu540/include diff --git a/src/soc/sifive/fu540/include/soc/memlayout.ld b/src/soc/sifive/fu540/include/soc/memlayout.ld index b9b9c47..81a7f9b 100644 --- a/src/soc/sifive/fu540/include/soc/memlayout.ld +++ b/src/soc/sifive/fu540/include/soc/memlayout.ld @@ -28,9 +28,11 @@ CAR_STACK(FU540_L2LIM + 64K, 20K) PRERAM_CBMEM_CONSOLE(FU540_L2LIM + 84K, 8K) ROMSTAGE(FU540_L2LIM + 128K, 128K) + PRERAM_CBFS_CACHE(FU540_L2LIM + 256K, 128K) L2LIM_END(FU540_L2LIM + 2M) DRAM_START(FU540_DRAM) RAMSTAGE(FU540_DRAM, 256K) MEM_STACK(FU540_DRAM + 256K, 20K) + POSTRAM_CBFS_CACHE(FU540_DRAM + 512K, 32M - 512K) } diff --git a/src/soc/sifive/fu540/include/soc/sd.h b/src/soc/sifive/fu540/include/soc/sd.h new file mode 100644 index 0000000..679d0f4 --- /dev/null +++ b/src/soc/sifive/fu540/include/soc/sd.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 SiFive, Inc + * Copyright (C) 2019 HardenedLinux + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#ifndef _LIBRARIES_SD_H +#define _LIBRARIES_SD_H + +#define SD_INIT_ERROR_CMD0 1 +#define SD_INIT_ERROR_CMD8 2 +#define SD_INIT_ERROR_ACMD41 3 +#define SD_INIT_ERROR_CMD58 4 +#define SD_INIT_ERROR_CMD16 5 + +#define SD_COPY_ERROR_CMD18 1 +#define SD_COPY_ERROR_CMD18_CRC 2 + +#ifndef __ASSEMBLER__ + +#include <stdint.h> +#include <stddef.h> + +int sd_init(spi_ctrl* spi, unsigned int input_clk_hz); +int sd_copy(spi_ctrl* spi, void* dst, uint32_t src_lba, size_t size); + +#endif /* !__ASSEMBLER__ */ + +#endif /* _LIBRARIES_SD_H */ diff --git a/src/soc/sifive/fu540/media.c b/src/soc/sifive/fu540/media.c deleted file mode 100644 index 7b9ccb0..0000000 --- a/src/soc/sifive/fu540/media.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Jonathan Neuschäfer - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <boot_device.h> - -/* At 0x20000000: A 256MiB long memory-mapped view of the flash at QSPI0 */ -static struct mem_region_device mdev = - MEM_REGION_DEV_RO_INIT((void *)0x20000000, CONFIG_ROM_SIZE); - -const struct region_device *boot_device_ro(void) -{ - return &mdev.rdev; -} diff --git a/src/soc/sifive/fu540/sd.c b/src/soc/sifive/fu540/sd.c new file mode 100644 index 0000000..3af26ad --- /dev/null +++ b/src/soc/sifive/fu540/sd.c @@ -0,0 +1,302 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 SiFive, Inc + * Copyright (C) 2019 HardenedLinux + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <mcall.h> +#include <arch/io.h> +#include <soc/spi.h> +#include <soc/sd.h> + + +#define SPI_DIR_RX 0 +#define SPI_DIR_TX 1 + +#define SPI_ENDIAN_MSB 0 +#define SPI_ENDIAN_LSB 1 + +#define SPI_CSMODE_AUTO 0 +#define SPI_CSMODE_HOLD 2 +#define SPI_CSMODE_OFF 3 + +#define SPI_PROTO_S 0 +#define SPI_PROTO_D 1 +#define SPI_PROTO_Q 2 + +#define SD_CMD_GO_IDLE_STATE 0 +#define SD_CMD_SEND_IF_COND 8 +#define SD_CMD_STOP_TRANSMISSION 12 +#define SD_CMD_SET_BLOCKLEN 16 +#define SD_CMD_READ_BLOCK_MULTIPLE 18 +#define SD_CMD_APP_SEND_OP_COND 41 +#define SD_CMD_APP_CMD 55 +#define SD_CMD_READ_OCR 58 +#define SD_RESPONSE_IDLE 0x1 +// Data token for commands 17, 18, 24 +#define SD_DATA_TOKEN 0xfe + + +// SD card initialization must happen at 100-400kHz +#define SD_POWER_ON_FREQ_KHZ 400L +// SD cards normally support reading/writing at 20MHz +#define SD_POST_INIT_CLK_KHZ 20000L + + +// Command frame starts by asserting low and then high for first two clock edges +#define SD_CMD(cmd) (0x40 | (cmd)) + + +/** + * Send dummy byte (all ones). + * + * Used in many cases to read one byte from SD card, since SPI is a full-duplex + * protocol and it is necessary to send a byte in order to read a byte. + */ +static inline uint8_t sd_dummy(spi_ctrl* spi) +{ + return spi_txrx(spi, 0xFF); +} + + +static int sd_cmd(spi_ctrl* spi, uint8_t cmd, uint32_t arg, uint8_t crc) +{ + unsigned long n; + uint8_t r; + + spi->csmode.mode = SPI_CSMODE_HOLD; + sd_dummy(spi); + spi_txrx(spi, cmd); + spi_txrx(spi, arg >> 24); + spi_txrx(spi, arg >> 16); + spi_txrx(spi, arg >> 8); + spi_txrx(spi, arg); + spi_txrx(spi, crc); + + n = 1000; + do { + r = sd_dummy(spi); + if (!(r & 0x80)) { + break; + } + } while (--n > 0); + return r; +} + + +static inline void sd_cmd_end(spi_ctrl* spi) +{ + sd_dummy(spi); + spi->csmode.mode = SPI_CSMODE_AUTO; +} + + +static void sd_poweron(spi_ctrl* spi, unsigned int input_clk_khz) +{ + // Initialize SPI controller + spi->fmt.raw_bits = ((spi_reg_fmt) { + .proto = SPI_PROTO_S, + .dir = SPI_DIR_RX, + .endian = SPI_ENDIAN_MSB, + .len = 8, + }).raw_bits; + spi->csdef |= 0x1; + spi->csid = 0; + + spi->sckdiv = spi_min_clk_divisor(input_clk_khz, SD_POWER_ON_FREQ_KHZ); + spi->csmode.mode = SPI_CSMODE_OFF; + + for (int i = 10; i > 0; i--) { + // Set SD card pin DI high for 74+ cycles + // SD CMD pin is the same pin as SPI DI, so CMD = 0xff means assert DI high + // for 8 cycles. + sd_dummy(spi); + } + + spi->csmode.mode = SPI_CSMODE_AUTO; +} + + +/** + * Reset card. + */ +static int sd_cmd0(spi_ctrl* spi) +{ + int rc; + rc = (sd_cmd(spi, SD_CMD(SD_CMD_GO_IDLE_STATE), 0, 0x95) != SD_RESPONSE_IDLE); + sd_cmd_end(spi); + return rc; +} + + +/** + * Check for SD version and supported voltages. + */ +static int sd_cmd8(spi_ctrl* spi) +{ + // Check for high capacity cards + // Fail if card does not support SDHC + int rc; + rc = (sd_cmd(spi, SD_CMD(SD_CMD_SEND_IF_COND), 0x000001AA, 0x87) != SD_RESPONSE_IDLE); + sd_dummy(spi); /* command version; reserved */ + sd_dummy(spi); /* reserved */ + rc |= ((sd_dummy(spi) & 0xF) != 0x1); /* voltage */ + rc |= (sd_dummy(spi) != 0xAA); /* check pattern */ + sd_cmd_end(spi); + return rc; +} + + +/** + * Send app command. Used as prefix to app commands (ACMD). + */ +static void sd_cmd55(spi_ctrl* spi) +{ + sd_cmd(spi, SD_CMD(SD_CMD_APP_CMD), 0, 0x65); + sd_cmd_end(spi); +} + + +/** + * Start SDC initialization process. + */ +static int sd_acmd41(spi_ctrl* spi) +{ + uint8_t r; + do { + sd_cmd55(spi); + r = sd_cmd(spi, SD_CMD(SD_CMD_APP_SEND_OP_COND), 0x40000000, 0x77); /* HCS = 1 */ + sd_cmd_end(spi); + } while (r == SD_RESPONSE_IDLE); + return (r != 0x00); +} + + +/** + * Read operation conditions register (OCR) to check for availability of block + * addressing mode. + */ +static int sd_cmd58(spi_ctrl* spi) +{ + // HACK: Disabled due to bugs. It is not strictly necessary + // to issue this command if we only support SD cards that support SDHC mode. + return 0; + // int rc; + // rc = (sd_cmd(spi, SD_CMD(SD_CMD_READ_OCR), 0, 0xFD) != 0x00); + // rc |= ((sd_dummy(spi) & 0x80) != 0x80); /* Power up status */ + // sd_dummy(spi); /* Supported voltages */ + // sd_dummy(spi); /* Supported voltages */ + // sd_dummy(spi); /* Supported voltages */ + // sd_cmd_end(spi); + // return rc; +} + + +/** + * Set block addressing mode. + */ +static int sd_cmd16(spi_ctrl* spi) +{ + int rc; + rc = (sd_cmd(spi, SD_CMD(SD_CMD_SET_BLOCKLEN), 0x200, 0x15) != 0x00); + sd_cmd_end(spi); + return rc; +} + + +static uint8_t crc7(uint8_t prev, uint8_t in) +{ + // CRC polynomial 0x89 + uint8_t remainder = prev & in; + remainder ^= (remainder >> 4) ^ (remainder >> 7); + remainder ^= remainder << 4; + return remainder & 0x7f; +} + + +static uint16_t crc16(uint16_t crc, uint8_t data) +{ + // CRC polynomial 0x11021 + crc = (uint8_t)(crc >> 8) | (crc << 8); + crc ^= data; + crc ^= (uint8_t)(crc >> 4) & 0xf; + crc ^= crc << 12; + crc ^= (crc & 0xff) << 5; + return crc; +} + + +//int sd_init(spi_ctrl* spi, unsigned int input_clk_khz, int skip_sd_init_commands) +int sd_init(spi_ctrl* spi, unsigned int input_clk_khz) +{ + sd_poweron(spi, input_clk_khz); + if (sd_cmd0(spi)) + return SD_INIT_ERROR_CMD0; + if (sd_cmd8(spi)) + return SD_INIT_ERROR_CMD8; + if (sd_acmd41(spi)) + return SD_INIT_ERROR_ACMD41; + if (sd_cmd58(spi)) + return SD_INIT_ERROR_CMD58; + if (sd_cmd16(spi)) + return SD_INIT_ERROR_CMD16; + + // Increase clock frequency after initialization for higher performance. + spi->sckdiv = spi_min_clk_divisor(input_clk_khz, SD_POST_INIT_CLK_KHZ); + return 0; +} + + +int sd_copy(spi_ctrl* spi, void* dst, uint32_t src_lba, size_t size) +{ + volatile uint8_t *p = dst; + long i = size; + int rc = 0; + + uint8_t c = 0; + c = crc7(c, SD_CMD(SD_CMD_READ_BLOCK_MULTIPLE)); + c = crc7(c, src_lba >> 24); + c = crc7(c, (src_lba >> 16) & 0xff); + c = crc7(c, (src_lba >> 8) & 0xff); + c = crc7(c, src_lba & 0xff); + c = (c << 1) | 1; + if (sd_cmd(spi, SD_CMD(SD_CMD_READ_BLOCK_MULTIPLE), src_lba, c) != 0x00) { + sd_cmd_end(spi); + return SD_COPY_ERROR_CMD18; + } + do { + uint16_t crc, crc_exp; + long n; + + crc = 0; + n = 512; + while (sd_dummy(spi) != SD_DATA_TOKEN); + do { + uint8_t x = sd_dummy(spi); + *p++ = x; + crc = crc16(crc, x); + } while (--n > 0); + + crc_exp = ((uint16_t)sd_dummy(spi) << 8); + crc_exp |= sd_dummy(spi); + + if (crc != crc_exp) { + rc = SD_COPY_ERROR_CMD18_CRC; + break; + } + } while (--i > 0); + + sd_cmd(spi, SD_CMD(SD_CMD_STOP_TRANSMISSION), 0, 0x01); + sd_cmd_end(spi); + return rc; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/30901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id97d293aee33082191cfaf47844769bdfa3d7a1b Gerrit-Change-Number: 30901 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-MessageType: newchange

4 25

Change in coreboot[master]: soc/intel/cannonlake: Use common cpu/intel/car/romstage.c code
by Subrata Banik (Code Review) 27 Aug '19

27 Aug '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35109 ) Change subject: soc/intel/cannonlake: Use common cpu/intel/car/romstage.c code ...................................................................... soc/intel/cannonlake: Use common cpu/intel/car/romstage.c code This patch includes common romstage code to setup the console and load postcar. Change-Id: I9da592960f20ed9742ff696198dbc028ef519ddf Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/romstage/Makefile.inc 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/35109/1 diff --git a/src/soc/intel/cannonlake/romstage/Makefile.inc b/src/soc/intel/cannonlake/romstage/Makefile.inc index 75d7985..33d9629 100644 --- a/src/soc/intel/cannonlake/romstage/Makefile.inc +++ b/src/soc/intel/cannonlake/romstage/Makefile.inc @@ -13,6 +13,7 @@ # GNU General Public License for more details. # +romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += romstage.c romstage-y += fsp_params.c romstage-y += systemagent.c -- To view, visit https://review.coreboot.org/c/coreboot/+/35109 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9da592960f20ed9742ff696198dbc028ef519ddf Gerrit-Change-Number: 35109 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

5 11

Change in coreboot[master]: AUTHORS: Move src/arch/mips copyrights into AUTHORS file
by Martin Roth (Code Review) 27 Aug '19

27 Aug '19

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34607 ) Change subject: AUTHORS: Move src/arch/mips copyrights into AUTHORS file ...................................................................... AUTHORS: Move src/arch/mips copyrights into AUTHORS file As discussed on the mailing list and voted upon, the coreboot project is going to move the majority of copyrights out of the headers and into an AUTHORS file. This will happen a bit at a time, as we'll be unifying license headers at the same time. Additional changes in this patch: - Remove comments saying that a file is based on another file from the coreboot project. Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: If61689db67c58f0d66ab96ca749bfcd589935ce2 --- M AUTHORS M src/arch/mips/Kconfig M src/arch/mips/Makefile.inc M src/arch/mips/ashldi3.c M src/arch/mips/boot.c M src/arch/mips/bootblock.S M src/arch/mips/bootblock_simple.c M src/arch/mips/cache.c M src/arch/mips/include/arch/bootblock_common.h M src/arch/mips/include/arch/byteorder.h M src/arch/mips/include/arch/cache.h M src/arch/mips/include/arch/cbconfig.h M src/arch/mips/include/arch/cpu.h M src/arch/mips/include/arch/early_variables.h M src/arch/mips/include/arch/exception.h M src/arch/mips/include/arch/header.ld M src/arch/mips/include/arch/hlt.h M src/arch/mips/include/arch/memlayout.h M src/arch/mips/include/arch/mmio.h M src/arch/mips/include/arch/mmu.h M src/arch/mips/include/arch/pci_ops.h M src/arch/mips/include/arch/stages.h M src/arch/mips/include/arch/types.h M src/arch/mips/mmu.c M src/arch/mips/stages.c M src/arch/mips/tables.c 26 files changed, 3 insertions(+), 61 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/34607/1 diff --git a/AUTHORS b/AUTHORS index ad8433e..3dbd1d5 100644 --- a/AUTHORS +++ b/AUTHORS @@ -18,6 +18,7 @@ Free Software Foundation, Inc. Gary Jennejohn Google Inc. +Imagination Technologies Kshitij Marius Gröger MontaVista Software, Inc. diff --git a/src/arch/mips/Kconfig b/src/arch/mips/Kconfig index b8570c1..9df514b 100644 --- a/src/arch/mips/Kconfig +++ b/src/arch/mips/Kconfig @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2014 Imagination Technologies -# # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; version 2 of diff --git a/src/arch/mips/Makefile.inc b/src/arch/mips/Makefile.inc index cd474ee..7130aba 100644 --- a/src/arch/mips/Makefile.inc +++ b/src/arch/mips/Makefile.inc @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2014 Imagination Technologies -# # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; version 2 of diff --git a/src/arch/mips/ashldi3.c b/src/arch/mips/ashldi3.c index f68d78e..e3282f5 100644 --- a/src/arch/mips/ashldi3.c +++ b/src/arch/mips/ashldi3.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google, Inc. - * - * Based on linux arch/mips/lib/ashldi3.c - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -13,6 +9,8 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. + * + * Based on linux arch/mips/lib/ashldi3.c */ #ifndef __ORDER_LITTLE_ENDIAN__ diff --git a/src/arch/mips/boot.c b/src/arch/mips/boot.c index 5ab36ec..a8518cd 100644 --- a/src/arch/mips/boot.c +++ b/src/arch/mips/boot.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Imagination Technologies - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/mips/bootblock.S b/src/arch/mips/bootblock.S index f8049c9..8ae1cfd 100644 --- a/src/arch/mips/bootblock.S +++ b/src/arch/mips/bootblock.S @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Imagination Technologies - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/mips/bootblock_simple.c b/src/arch/mips/bootblock_simple.c index e195b6a..be0b176 100644 --- a/src/arch/mips/bootblock_simple.c +++ b/src/arch/mips/bootblock_simple.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Imagination Technologies - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/arch/mips/cache.c b/src/arch/mips/cache.c index 62c20f3..2b56174 100644 --- a/src/arch/mips/cache.c +++ b/src/arch/mips/cache.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Imagination Technologies - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/mips/include/arch/bootblock_common.h b/src/arch/mips/include/arch/bootblock_common.h index f5c11ba..b930b5c 100644 --- a/src/arch/mips/include/arch/bootblock_common.h +++ b/src/arch/mips/include/arch/bootblock_common.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Imagination Technologies - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/mips/include/arch/byteorder.h b/src/arch/mips/include/arch/byteorder.h index 35d444b..7c0ce47 100644 --- a/src/arch/mips/include/arch/byteorder.h +++ b/src/arch/mips/include/arch/byteorder.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Imagination Technologies - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/mips/include/arch/cache.h b/src/arch/mips/include/arch/cache.h index 61a3e7c..c610c99 100644 --- a/src/arch/mips/include/arch/cache.h +++ b/src/arch/mips/include/arch/cache.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Imagination Technologies - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/mips/include/arch/cbconfig.h b/src/arch/mips/include/arch/cbconfig.h index 9467f52..35c1387 100644 --- a/src/arch/mips/include/arch/cbconfig.h +++ b/src/arch/mips/include/arch/cbconfig.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/mips/include/arch/cpu.h b/src/arch/mips/include/arch/cpu.h index 8e35908..9f39992 100644 --- a/src/arch/mips/include/arch/cpu.h +++ b/src/arch/mips/include/arch/cpu.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Imagination Technologies - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/mips/include/arch/early_variables.h b/src/arch/mips/include/arch/early_variables.h index 61f4653..8fc9c19 100644 --- a/src/arch/mips/include/arch/early_variables.h +++ b/src/arch/mips/include/arch/early_variables.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Imagination Technologies - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/mips/include/arch/exception.h b/src/arch/mips/include/arch/exception.h index e70d396..a0ab9ec 100644 --- a/src/arch/mips/include/arch/exception.h +++ b/src/arch/mips/include/arch/exception.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Imagination Technologies - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/mips/include/arch/header.ld b/src/arch/mips/include/arch/header.ld index 1d84a4e..6650132 100644 --- a/src/arch/mips/include/arch/header.ld +++ b/src/arch/mips/include/arch/header.ld @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/mips/include/arch/hlt.h b/src/arch/mips/include/arch/hlt.h index 703773b..5feafe2 100644 --- a/src/arch/mips/include/arch/hlt.h +++ b/src/arch/mips/include/arch/hlt.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Imagination Technologies - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/mips/include/arch/memlayout.h b/src/arch/mips/include/arch/memlayout.h index fe05bd8..bf862a3 100644 --- a/src/arch/mips/include/arch/memlayout.h +++ b/src/arch/mips/include/arch/memlayout.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/mips/include/arch/mmio.h b/src/arch/mips/include/arch/mmio.h index c491b51..2564e3b 100644 --- a/src/arch/mips/include/arch/mmio.h +++ b/src/arch/mips/include/arch/mmio.h @@ -1,12 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Imagination Technologies - * - * Based on arch/armv7/include/arch/io.h: - * Copyright 2013 Google Inc. - * Copyright (C) 1996-2000 Russell King - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/mips/include/arch/mmu.h b/src/arch/mips/include/arch/mmu.h index 8997e27..f7377bb 100644 --- a/src/arch/mips/include/arch/mmu.h +++ b/src/arch/mips/include/arch/mmu.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/mips/include/arch/pci_ops.h b/src/arch/mips/include/arch/pci_ops.h index 7bfcbdd..5be52aa 100644 --- a/src/arch/mips/include/arch/pci_ops.h +++ b/src/arch/mips/include/arch/pci_ops.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/mips/include/arch/stages.h b/src/arch/mips/include/arch/stages.h index 802199f..63306bd 100644 --- a/src/arch/mips/include/arch/stages.h +++ b/src/arch/mips/include/arch/stages.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Imagination Technologies - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/mips/include/arch/types.h b/src/arch/mips/include/arch/types.h index 31a2f9f..fa14b6a 100644 --- a/src/arch/mips/include/arch/types.h +++ b/src/arch/mips/include/arch/types.h @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Imagination Technologies - * - * Based on src/arch/armv7/include/arch/types.h - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/mips/mmu.c b/src/arch/mips/mmu.c index b144fd3..5ef276d 100644 --- a/src/arch/mips/mmu.c +++ b/src/arch/mips/mmu.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google, Inc. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/arch/mips/stages.c b/src/arch/mips/stages.c index e940faa..0971e98 100644 --- a/src/arch/mips/stages.c +++ b/src/arch/mips/stages.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Imagination Technologies - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/mips/tables.c b/src/arch/mips/tables.c index 50d2a55..e9de4bf 100644 --- a/src/arch/mips/tables.c +++ b/src/arch/mips/tables.c @@ -1,11 +1,6 @@ /* * This file is part of the coreboot project. * - * Based on src/arch/armv7/tables.c: - * Copyright (C) 2003 Eric Biederman - * Copyright (C) 2005 Steve Magnani - * Copyright (C) 2008-2009 coresystems GmbH - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. -- To view, visit https://review.coreboot.org/c/coreboot/+/34607 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If61689db67c58f0d66ab96ca749bfcd589935ce2 Gerrit-Change-Number: 34607 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit August 2019