coreboot-gerrit August 2019

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Change in coreboot[master]: soc/intel: Move fill_postcar_frame to memmap.c
by Kyösti Mälkki (Code Review) 29 Aug '19

29 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34894 ) Change subject: soc/intel: Move fill_postcar_frame to memmap.c ...................................................................... soc/intel: Move fill_postcar_frame to memmap.c Change-Id: I84b1fad52d623a879f00c3f721f480f58d7d6d8a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/apollolake/memmap.c M src/soc/intel/apollolake/romstage.c M src/soc/intel/baytrail/memmap.c M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/cannonlake/memmap.c M src/soc/intel/cannonlake/romstage/romstage.c M src/soc/intel/denverton_ns/memmap.c M src/soc/intel/denverton_ns/romstage.c M src/soc/intel/icelake/memmap.c M src/soc/intel/icelake/romstage/romstage.c M src/soc/intel/quark/memmap.c M src/soc/intel/quark/romstage/fsp2_0.c M src/soc/intel/skylake/memmap.c M src/soc/intel/skylake/romstage/romstage_fsp20.c 14 files changed, 150 insertions(+), 150 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/34894/1 diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index 8b51a85..4c84f7a 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -47,3 +47,31 @@ *start = sa_get_tseg_base(); *size = sa_get_tseg_size(); } + +void fill_postcar_frame(struct postcar_frame *pcf) +{ + uintptr_t top_of_ram; + uintptr_t smm_base; + size_t smm_size; + + /* + * We need to make sure ramstage will be run cached. At this point exact + * location of ramstage in cbmem is not known. Instruct postcar to cache + * 16 megs under cbmem top which is a safe bet to cover ramstage. + */ + top_of_ram = (uintptr_t) cbmem_top(); + /* cbmem_top() needs to be at least 16 MiB aligned */ + assert(ALIGN_DOWN(top_of_ram, 16*MiB) == top_of_ram); + postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB, + MTRR_TYPE_WRBACK); + + /* + * Cache the TSEG region at the top of ram. This region is + * not restricted to SMM mode until SMM has been relocated. + * By setting the region to cacheable it provides faster access + * when relocating the SMM handler as well as using the TSEG + * region for other purposes. + */ + smm_region(&smm_base, &smm_size); + postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); +} diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 8324b77..4581291 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -229,34 +229,6 @@ mainboard_save_dimm_info(); } -void fill_postcar_frame(struct postcar_frame *pcf) -{ - uintptr_t top_of_ram; - uintptr_t smm_base; - size_t smm_size; - - /* - * We need to make sure ramstage will be run cached. At this point exact - * location of ramstage in cbmem is not known. Instruct postcar to cache - * 16 megs under cbmem top which is a safe bet to cover ramstage. - */ - top_of_ram = (uintptr_t) cbmem_top(); - /* cbmem_top() needs to be at least 16 MiB aligned */ - assert(ALIGN_DOWN(top_of_ram, 16*MiB) == top_of_ram); - postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB, - MTRR_TYPE_WRBACK); - - /* - * Cache the TSEG region at the top of ram. This region is - * not restricted to SMM mode until SMM has been relocated. - * By setting the region to cacheable it provides faster access - * when relocating the SMM handler as well as using the TSEG - * region for other purposes. - */ - smm_region(&smm_base, &smm_size); - postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); -} - static void fill_console_params(FSPM_UPD *mupd) { if (CONFIG(CONSOLE_SERIAL)) { diff --git a/src/soc/intel/baytrail/memmap.c b/src/soc/intel/baytrail/memmap.c index 015f13c..ee49302 100644 --- a/src/soc/intel/baytrail/memmap.c +++ b/src/soc/intel/baytrail/memmap.c @@ -37,3 +37,16 @@ *start = (iosf_bunit_read(BUNIT_SMRRL) & 0xFFFF) << 20; *size = smm_region_size(); } + +void fill_postcar_frame(struct postcar_frame *pcf) +{ + uintptr_t top_of_ram; + + /* Cache at least 8 MiB below the top of ram, and at most 8 MiB + * above top of the ram. This satisfies MTRR alignment requirement + * with different TSEG size configurations. + */ + top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); + postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB, + MTRR_TYPE_WRBACK); +} diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 2b37d18..91bb857 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -234,16 +234,3 @@ romstage_handoff_init(prev_sleep_state == ACPI_S3); } - -void fill_postcar_frame(struct postcar_frame *pcf) -{ - uintptr_t top_of_ram; - - /* Cache at least 8 MiB below the top of ram, and at most 8 MiB - * above top of the ram. This satisfies MTRR alignment requirement - * with different TSEG size configurations. - */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); - postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB, - MTRR_TYPE_WRBACK); -} diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c index 276b9a3..ddc6842 100644 --- a/src/soc/intel/cannonlake/memmap.c +++ b/src/soc/intel/cannonlake/memmap.c @@ -264,3 +264,18 @@ return (void *)(uintptr_t)ebda_cfg.tolum_base; } + +void fill_postcar_frame(struct postcar_frame *pcf) +{ + uintptr_t top_of_ram; + /* + * We need to make sure ramstage will be run cached. At this + * point exact location of ramstage in cbmem is not known. + * Instruct postcar to cache 16 megs under cbmem top which is + * a safe bet to cover ramstage. + */ + top_of_ram = (uintptr_t) cbmem_top(); + printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); + top_of_ram -= 16*MiB; + postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); +} diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index 75cedc8..a49b4dd 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -146,18 +146,3 @@ if (!s3wake) save_dimm_info(); } - -void fill_postcar_frame(struct postcar_frame *pcf) -{ - uintptr_t top_of_ram; - /* - * We need to make sure ramstage will be run cached. At this - * point exact location of ramstage in cbmem is not known. - * Instruct postcar to cache 16 megs under cbmem top which is - * a safe bet to cover ramstage. - */ - top_of_ram = (uintptr_t) cbmem_top(); - printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); - top_of_ram -= 16*MiB; - postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); -} diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c index 0cca4b9..27a2127 100644 --- a/src/soc/intel/denverton_ns/memmap.c +++ b/src/soc/intel/denverton_ns/memmap.c @@ -75,3 +75,29 @@ *start = smm_region_start(); *size = smm_region_size(); } + +void fill_postcar_frame(struct postcar_frame *pcf) +{ + uintptr_t top_of_ram; + uintptr_t smm_base; + size_t smm_size; + + /* + * We need to make sure ramstage will be run cached. At this point exact + * location of ramstage in cbmem is not known. Instruct postcar to cache + * 16 megs under cbmem top which is a safe bet to cover ramstage. + */ + top_of_ram = (uintptr_t)cbmem_top(); + postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB, + MTRR_TYPE_WRBACK); + + /* + * Cache the TSEG region at the top of ram. This region is + * not restricted to SMM mode until SMM has been relocated. + * By setting the region to cacheable it provides faster access + * when relocating the SMM handler as well as using the TSEG + * region for other purposes. + */ + smm_region(&smm_base, &smm_size); + postcar_frame_add_mtrr(pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); +} diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index 624ba46..aafd968 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -153,32 +153,6 @@ #endif } -void fill_postcar_frame(struct postcar_frame *pcf) -{ - uintptr_t top_of_ram; - uintptr_t smm_base; - size_t smm_size; - - /* - * We need to make sure ramstage will be run cached. At this point exact - * location of ramstage in cbmem is not known. Instruct postcar to cache - * 16 megs under cbmem top which is a safe bet to cover ramstage. - */ - top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB, - MTRR_TYPE_WRBACK); - - /* - * Cache the TSEG region at the top of ram. This region is - * not restricted to SMM mode until SMM has been relocated. - * By setting the region to cacheable it provides faster access - * when relocating the SMM handler as well as using the TSEG - * region for other purposes. - */ - smm_region(&smm_base, &smm_size); - postcar_frame_add_mtrr(pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); -} - static void soc_memory_init_params(FSP_M_CONFIG *m_cfg) { FSPM_UPD *mupd = container_of(m_cfg, FSPM_UPD, FspmConfig); diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c index 0d41f25..c1038fa 100644 --- a/src/soc/intel/icelake/memmap.c +++ b/src/soc/intel/icelake/memmap.c @@ -262,3 +262,18 @@ return (void *)(uintptr_t)ebda_cfg.tolum_base; } + +void fill_postcar_frame(struct postcar_frame *pcf) +{ + uintptr_t top_of_ram; + /* + * We need to make sure ramstage will be run cached. At this + * point exact location of ramstage in cbmem is not known. + * Instruct postcar to cache 16 megs under cbmem top which is + * a safe bet to cover ramstage. + */ + top_of_ram = (uintptr_t) cbmem_top(); + printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); + top_of_ram -= 16*MiB; + postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); +} diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c index 0b6a75b..39e7f90 100644 --- a/src/soc/intel/icelake/romstage/romstage.c +++ b/src/soc/intel/icelake/romstage/romstage.c @@ -131,18 +131,3 @@ if (!s3wake) save_dimm_info(); } - -void fill_postcar_frame(struct postcar_frame *pcf) -{ - uintptr_t top_of_ram; - /* - * We need to make sure ramstage will be run cached. At this - * point exact location of ramstage in cbmem is not known. - * Instruct postcar to cache 16 megs under cbmem top which is - * a safe bet to cover ramstage. - */ - top_of_ram = (uintptr_t) cbmem_top(); - printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); - top_of_ram -= 16*MiB; - postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); -} diff --git a/src/soc/intel/quark/memmap.c b/src/soc/intel/quark/memmap.c index d67856c..00b2904 100644 --- a/src/soc/intel/quark/memmap.c +++ b/src/soc/intel/quark/memmap.c @@ -32,3 +32,28 @@ /* Return the top of memory */ return (void *)top_of_memory; } + +void fill_postcar_frame(struct postcar_frame *pcf) +{ + uintptr_t top_of_ram; + uintptr_t top_of_low_usable_memory; + + /* Locate the top of RAM */ + top_of_low_usable_memory = (uintptr_t) cbmem_top(); + top_of_ram = ALIGN(top_of_low_usable_memory, 16 * MiB); + + /* Cache postcar and ramstage */ + postcar_frame_add_mtrr(pcf, top_of_ram - (16 * MiB), 16 * MiB, + MTRR_TYPE_WRBACK); + + /* Cache RMU area */ + postcar_frame_add_mtrr(pcf, (uintptr_t) top_of_low_usable_memory, + 0x10000, MTRR_TYPE_WRTHROUGH); + + /* Cache ESRAM */ + postcar_frame_add_mtrr(pcf, 0x80000000, 0x80000, MTRR_TYPE_WRBACK); + + pcf->skip_common_mtrr = 1; + /* Cache SPI flash - Write protect not supported */ + postcar_frame_add_romcache(pcf, MTRR_TYPE_WRTHROUGH); +} diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index 41830c7..756bfa8 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -60,31 +60,6 @@ pcie_init(); } -void fill_postcar_frame(struct postcar_frame *pcf) -{ - uintptr_t top_of_ram; - uintptr_t top_of_low_usable_memory; - - /* Locate the top of RAM */ - top_of_low_usable_memory = (uintptr_t) cbmem_top(); - top_of_ram = ALIGN(top_of_low_usable_memory, 16 * MiB); - - /* Cache postcar and ramstage */ - postcar_frame_add_mtrr(pcf, top_of_ram - (16 * MiB), 16 * MiB, - MTRR_TYPE_WRBACK); - - /* Cache RMU area */ - postcar_frame_add_mtrr(pcf, (uintptr_t) top_of_low_usable_memory, - 0x10000, MTRR_TYPE_WRTHROUGH); - - /* Cache ESRAM */ - postcar_frame_add_mtrr(pcf, 0x80000000, 0x80000, MTRR_TYPE_WRBACK); - - pcf->skip_common_mtrr = 1; - /* Cache SPI flash - Write protect not supported */ - postcar_frame_add_romcache(pcf, MTRR_TYPE_WRTHROUGH); -} - static struct chipset_power_state power_state; struct chipset_power_state *get_power_state(void) diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index 9d3f377..e3590fd 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -289,3 +289,31 @@ return (void *)(uintptr_t)ebda_cfg.tolum_base; } + +void fill_postcar_frame(struct postcar_frame *pcf) +{ + uintptr_t top_of_ram; + uintptr_t smm_base; + size_t smm_size; + + /* + * We need to make sure ramstage will be run cached. At this + * point exact location of ramstage in cbmem is not known. + * Instruct postcar to cache 16 megs under cbmem top which is + * a safe bet to cover ramstage. + */ + top_of_ram = (uintptr_t) cbmem_top(); + printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); + top_of_ram -= 16*MiB; + postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); + + /* + * Cache the TSEG region at the top of ram. This region is + * not restricted to SMM mode until SMM has been relocated. + * By setting the region to cacheable it provides faster access + * when relocating the SMM handler as well as using the TSEG + * region for other purposes. + */ + smm_region(&smm_base, &smm_size); + postcar_frame_add_mtrr(pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); +} diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 0c39d6a..ab3930f 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -158,34 +158,6 @@ save_dimm_info(); } -void fill_postcar_frame(struct postcar_frame *pcf) -{ - uintptr_t top_of_ram; - uintptr_t smm_base; - size_t smm_size; - - /* - * We need to make sure ramstage will be run cached. At this - * point exact location of ramstage in cbmem is not known. - * Instruct postcar to cache 16 megs under cbmem top which is - * a safe bet to cover ramstage. - */ - top_of_ram = (uintptr_t) cbmem_top(); - printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); - top_of_ram -= 16*MiB; - postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); - - /* - * Cache the TSEG region at the top of ram. This region is - * not restricted to SMM mode until SMM has been relocated. - * By setting the region to cacheable it provides faster access - * when relocating the SMM handler as well as using the TSEG - * region for other purposes. - */ - smm_region(&smm_base, &smm_size); - postcar_frame_add_mtrr(pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); -} - static void cpu_flex_override(FSP_M_CONFIG *m_cfg) { msr_t flex_ratio; -- To view, visit https://review.coreboot.org/c/coreboot/+/34894 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84b1fad52d623a879f00c3f721f480f58d7d6d8a Gerrit-Change-Number: 34894 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 11

Change in coreboot[master]: build: build the open-power ffs tools
by Marty E. Plummer (Code Review) 29 Aug '19

29 Aug '19

Marty E. Plummer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35008 ) Change subject: build: build the open-power ffs tools ...................................................................... build: build the open-power ffs tools Change-Id: I0ed8b8de001835e5676203c384a1659a2f29ff71 Signed-off-by: Marty E. Plummer <hanetzer(a)startmail.com> --- M Makefile.inc 1 file changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/35008/1 diff --git a/Makefile.inc b/Makefile.inc index c275d1e..9ad0c59 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -515,6 +515,8 @@ IFWITOOL:=$(objutil)/cbfstool/ifwitool IFITTOOL:=$(objutil)/cbfstool/ifittool AMDCOMPRESS:=$(objutil)/cbfstool/amdcompress +FPART:=$(objutil)/ffs/fpart/fpart +ECC:=$(objutil)/ffs/ecc/ecc $(obj)/cbfstool: $(CBFSTOOL) cp $< $@ @@ -534,6 +536,21 @@ $(obj)/amdcompress: $(AMDCOMPRESS) cp $< $@ +$(FPART): + mkdir -p $(objutil)/ffs + cd $(top)/3rdparty/ffs && autoreconf -i + cd $(objutil)/ffs && $(top)/3rdparty/ffs/configure CC="$(HOSTCC)" LD="$(LD)" + $(MAKE) -C $(objutil)/ffs + +$(ECC): $(FPART) + true + +$(obj)/fpart: $(FPART) + cp $< $@ + +$(obj)/ecc: $(ECC) + cp $< $@ + _WINCHECK=$(shell uname -o 2> /dev/null) STACK= ifeq ($(_WINCHECK),Msys) -- To view, visit https://review.coreboot.org/c/coreboot/+/35008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ed8b8de001835e5676203c384a1659a2f29ff71 Gerrit-Change-Number: 35008 Gerrit-PatchSet: 1 Gerrit-Owner: Marty E. Plummer <hanetzer(a)startmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Marty E. Plummer <hanetzer(a)startmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF
by Angel Pons (Code Review) 28 Aug '19

28 Aug '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32734 ) Change subject: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF ...................................................................... Patch Set 74: (1 comment) https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/… File src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb: https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/… PS74, Line 263: device pnp 2e.b on # SUART3 > A bit of a nit, but in reality all the UARTS are virtual and what physical wires they end up depends […] Right, then I wonder if SUART3 and SUART4 are actually used for anything. -- To view, visit https://review.coreboot.org/c/coreboot/+/32734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2edaa4a928de3a065e517c0f20e3302b4b702323 Gerrit-Change-Number: 32734 Gerrit-PatchSet: 74 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Keno Fischer <keno(a)alumni.harvard.edu> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Name of user not set #1002358 Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: T. Hudson <trammell.hudson(a)gmail.com> Gerrit-Reviewer: Trammell Hudson <hudson(a)trmm.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-CC: Michael Niewöhner Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 28 Aug 2019 20:50:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Keno Fischer <keno(a)alumni.harvard.edu> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner Gerrit-MessageType: comment

1 0

Change in coreboot[master]: arch/ppc64: subdir power8 specifics
by Marty E. Plummer (Code Review) 28 Aug '19

28 Aug '19

Marty E. Plummer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35081 ) Change subject: arch/ppc64: subdir power8 specifics ...................................................................... arch/ppc64: subdir power8 specifics Change-Id: I04fe1b3622e9b3e20c1f8ef02638f34654af3075 Signed-off-by: Marty E. Plummer <hanetzer(a)startmail.com> --- M src/arch/ppc64/Kconfig M src/arch/ppc64/Makefile.inc A src/arch/ppc64/power8/Kconfig A src/arch/ppc64/power8/Makefile.inc R src/arch/ppc64/power8/bootblock.S M src/mainboard/emulation/qemu-power8/Kconfig 6 files changed, 48 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/35081/1 diff --git a/src/arch/ppc64/Kconfig b/src/arch/ppc64/Kconfig index 0699e91..0f65c0c 100644 --- a/src/arch/ppc64/Kconfig +++ b/src/arch/ppc64/Kconfig @@ -18,3 +18,5 @@ config ARCH_RAMSTAGE_PPC64 bool select ARCH_PPC64 + +source "src/arch/ppc64/power8/Kconfig" diff --git a/src/arch/ppc64/Makefile.inc b/src/arch/ppc64/Makefile.inc index 99d8634..03b455a 100644 --- a/src/arch/ppc64/Makefile.inc +++ b/src/arch/ppc64/Makefile.inc @@ -16,16 +16,21 @@ ## ################################################################################ -ppc64_flags = -I$(src)/arch/ppc64/ -mbig-endian -mcpu=power8 -mtune=power8 - +ppc64_flags = -I$(src)/arch/ppc64/ -mbig-endian ppc64_asm_flags = ################################################################################ +## Take care of subdirectories +################################################################################ + +subdirs-y += power8/ + +################################################################################ ## bootblock ################################################################################ ifeq ($(CONFIG_ARCH_BOOTBLOCK_PPC64),y) -bootblock-y = bootblock.S stages.c +bootblock-y += stages.c bootblock-y += boot.c bootblock-y += rom_media.c bootblock-y += \ @@ -90,8 +95,6 @@ $(top)/src/lib/memmove.c \ $(top)/src/lib/memset.c -$(eval $(call create_class_compiler,rmodules,power8)) - ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c diff --git a/src/arch/ppc64/power8/Kconfig b/src/arch/ppc64/power8/Kconfig new file mode 100644 index 0000000..61494d1 --- /dev/null +++ b/src/arch/ppc64/power8/Kconfig @@ -0,0 +1,15 @@ +config ARCH_BOOTBLOCK_PPC64_POWER8 + def_bool n + select ARCH_BOOTBLOCK_PPC64 + +config ARCH_VERSTAGE_PPC64_POWER8 + def_bool n + select ARCH_VERSTAGE_PPC64 + +config ARCH_ROMSTAGE_PPC64_POWER8 + def_bool n + select ARCH_ROMSTAGE_PPC64 + +config ARCH_RAMSTAGE_PPC64_POWER8 + def_bool n + select ARCH_RAMSTAGE_PPC64 diff --git a/src/arch/ppc64/power8/Makefile.inc b/src/arch/ppc64/power8/Makefile.inc new file mode 100644 index 0000000..0c51ca9 --- /dev/null +++ b/src/arch/ppc64/power8/Makefile.inc @@ -0,0 +1,19 @@ +ppc64_flags += -mcpu=power8 -mtune=power8 + +################################################################################ +## bootblock +################################################################################ +ifeq ($(CONFIG_ARCH_BOOTBLOCK_PPC64_POWER8),y) + +bootblock-y += bootblock.S + +endif # CONFIG_ARCH_BOOTBLOCK_PPC64_POWER8 + +################################################################################ +## ramstage +################################################################################ +ifeq ($(CONFIG_ARCH_RAMSTAGE_PPC64_POWER8),y) + +$(eval $(call create_class_compiler,rmodules,power8)) + +endif # CONFIG_ARCH_RAMSTAGE_PPC64_POWER8 diff --git a/src/arch/ppc64/bootblock.S b/src/arch/ppc64/power8/bootblock.S similarity index 100% rename from src/arch/ppc64/bootblock.S rename to src/arch/ppc64/power8/bootblock.S diff --git a/src/mainboard/emulation/qemu-power8/Kconfig b/src/mainboard/emulation/qemu-power8/Kconfig index 0496178..f74e8fc 100644 --- a/src/mainboard/emulation/qemu-power8/Kconfig +++ b/src/mainboard/emulation/qemu-power8/Kconfig @@ -21,10 +21,10 @@ def_bool y select CPU_QEMU_POWER8 select BOARD_ROMSIZE_KB_4096 - select ARCH_BOOTBLOCK_PPC64 - select ARCH_VERSTAGE_PPC64 - select ARCH_ROMSTAGE_PPC64 - select ARCH_RAMSTAGE_PPC64 + select ARCH_BOOTBLOCK_PPC64_POWER8 + select ARCH_VERSTAGE_PPC64_POWER8 + select ARCH_ROMSTAGE_PPC64_POWER8 + select ARCH_RAMSTAGE_PPC64_POWER8 select HAVE_UART_SPECIAL select BOOT_DEVICE_NOT_SPI_FLASH select MISSING_BOARD_RESET -- To view, visit https://review.coreboot.org/c/coreboot/+/35081 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04fe1b3622e9b3e20c1f8ef02638f34654af3075 Gerrit-Change-Number: 35081 Gerrit-PatchSet: 1 Gerrit-Owner: Marty E. Plummer <hanetzer(a)startmail.com> Gerrit-MessageType: newchange

2 7

Change in coreboot[master]: mb/asrock/h110m: disable unused serial buses
by Maxim Polyakov (Code Review) 28 Aug '19

28 Aug '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35070 ) Change subject: mb/asrock/h110m: disable unused serial buses ...................................................................... mb/asrock/h110m: disable unused serial buses Disable psi0, i2c0 and i2c1 in the “SerialIoDevMode” register for the following reasons: 1. when the AMI BIOS is used, these pci devices are disabled in lspci.log; 2. there are no pads in the inteltool.log that use the functions of these buses Change-Id: I01ab10eb3fd41e81a1726805247c2b472d72287c Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/35070/1 diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 934083a..f87ca45 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -190,13 +190,13 @@ # PCH UART, SPI, I2C register "SerialIoDevMode" = "{ \ - [PchSerialIoIndexI2C0] = PchSerialIoPci, \ - [PchSerialIoIndexI2C1] = PchSerialIoPci, \ + [PchSerialIoIndexI2C0] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, \ [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \ [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ - [PchSerialIoIndexSpi0] = PchSerialIoPci, \ + [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ [PchSerialIoIndexUart0] = PchSerialIoDisabled, \ [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ -- To view, visit https://review.coreboot.org/c/coreboot/+/35070 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01ab10eb3fd41e81a1726805247c2b472d72287c Gerrit-Change-Number: 35070 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: Makefile: Pass .xcompile into genbuild_h
by Raul Rangel (Code Review) 28 Aug '19

28 Aug '19

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34240 ) Change subject: Makefile: Pass .xcompile into genbuild_h ...................................................................... Makefile: Pass .xcompile into genbuild_h I'm moving the .xcompile file into the $(obj) directory so we can leave the source pristine. We need to pass the location of .xcompile into genbuild_h.sh. BUG=b:112267918 TEST=Ran genbuild_h with and without an .xcompile and verified it was passed. Change-Id: I8b3a75b478fad92a0b09246f0a00b0580f8c4aef Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> --- M Makefile.inc M util/genbuild_h/genbuild_h.sh 2 files changed, 9 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/34240/1 diff --git a/Makefile.inc b/Makefile.inc index 28f1363..b1553a2 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -497,7 +497,7 @@ # Report new `build.ht` as dependency if `build.h` differs. build_h_check := \ export $(foreach exp,$(build_h_exports),$(exp)="$($(exp))"); \ - util/genbuild_h/genbuild_h.sh >$(build_h)t 2>/dev/null; \ + util/genbuild_h/genbuild_h.sh .xcompile >$(build_h)t 2>/dev/null; \ cmp -s $(build_h)t $(build_h) >/dev/null 2>&1 || echo $(build_h)t $(build_h): $$(shell $$(build_h_check)) diff --git a/util/genbuild_h/genbuild_h.sh b/util/genbuild_h/genbuild_h.sh index c264b74..bffdc01 100755 --- a/util/genbuild_h/genbuild_h.sh +++ b/util/genbuild_h/genbuild_h.sh @@ -22,6 +22,13 @@ export LC_ALL=C export TZ=UTC0 +XCOMPILE=$1 + +if [ -z "$XCOMPILE" ]; then + echo "usage: $0 <xcompile>" >&2 + exit 1 +fi + # $1: format string get_git_head_data() { LANG= git log --no-show-signature -1 --format="format:$1" 2>/dev/null || \ @@ -53,7 +60,7 @@ } IASL=util/crossgcc/xgcc/bin/iasl -eval $(grep ^IASL:= .xcompile 2>/dev/null | sed s,:=,=,) +eval $(grep ^IASL:= "$XCOMPILE" 2>/dev/null | sed s,:=,=,) #Print out the information that goes into build.h printf "/* build system definitions (autogenerated) */\n" -- To view, visit https://review.coreboot.org/c/coreboot/+/34240 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b3a75b478fad92a0b09246f0a00b0580f8c4aef Gerrit-Change-Number: 34240 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: Makefile: Write .xcompile to $(obj)
by Raul Rangel (Code Review) 28 Aug '19

28 Aug '19

Hello Julius Werner, Paul Menzel, build bot (Jenkins), Martin Roth, Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/28101 to look at the new patch set (#7). Change subject: Makefile: Write .xcompile to $(obj) ...................................................................... Makefile: Write .xcompile to $(obj) This file was being written to the root src directory. It is the only file being written to src during a normal build, while all others are being written to $(obj). I also cleaned up the generation of xcompile by removing the unnecessary eval and NOCOMPILE check. I also left .xcompile in distclean so it cleans up stale files. Since .xcompile is written into $(obj), `make clean` will now remove it. The tegra Makefiles are outside of the normal build process, so I just updated those Makefiles to point to the default xcompile location of a normal build. The what-jenkins-does target had to be updated to support these special targets. We generate an xcompile specifically for these targets and pass it into the Makefile. Ideally we should get these targets added to the main build. The COREBOOT_BUILD_DIR default value comes from the abuild script. The abuild missing_arches check will now generate a xcompile object into the build directory. BUG=b:112267918 TEST=ran `emerge-grunt coreboot` and `make what-jenkins-does` Change-Id: Ia83f234447b977efa824751c9674154b77d606b0 Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> --- M Makefile M Makefile.inc M src/soc/nvidia/tegra124/lp0/Makefile M src/soc/nvidia/tegra210/lp0/Makefile M util/abuild/abuild M util/crossgcc/Makefile.inc M util/docker/Makefile M util/testing/Makefile.inc 8 files changed, 26 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/28101/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/28101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia83f234447b977efa824751c9674154b77d606b0 Gerrit-Change-Number: 28101 Gerrit-PatchSet: 7 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: WIP: Change fmd for drallion
by Mathew King (Code Review) 28 Aug '19

28 Aug '19

Mathew King has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34762 ) Change subject: WIP: Change fmd for drallion ...................................................................... WIP: Change fmd for drallion Change-Id: I6f84712b31b8ada6c72ce56497f48ece5009dd60 --- M src/mainboard/google/drallion/chromeos.fmd 1 file changed, 11 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/34762/1 diff --git a/src/mainboard/google/drallion/chromeos.fmd b/src/mainboard/google/drallion/chromeos.fmd index ece0eda..cf4efac 100644 --- a/src/mainboard/google/drallion/chromeos.fmd +++ b/src/mainboard/google/drallion/chromeos.fmd @@ -1,27 +1,27 @@ FLASH@0xfe000000 0x2000000 { - SI_ALL@0x0 0x400000 { + SI_ALL@0x0 0x800000 { SI_DESC@0x0 0x1000 SI_EC@0x1000 0x100000 SI_GBE(PRESERVE)@0x101000 0x2000 - SI_ME@0x103000 0x2f9000 - SI_PDR(PRESERVE)@0x3fc000 0x4000 + SI_ME@0x103000 0x6f9000 + SI_PDR(PRESERVE)@0x7fc000 0x4000 } - SI_BIOS@0x400000 0x1c00000 { - RW_DIAG@0x0 0x12d0000 { - RW_LEGACY(CBFS)@0x0 0x12c0000 - DIAG_NVRAM@0x12c0000 0x10000 + SI_BIOS@0x800000 0x1800000 { + RW_DIAG@0x0 0xED0000 { + RW_LEGACY(CBFS)@0x0 0xec0000 + DIAG_NVRAM@0xec0000 0x10000 } - RW_SECTION_A@0x12d0000 0x280000 { + RW_SECTION_A@0xED0000 0x280000 { VBLOCK_A@0x0 0x10000 FW_MAIN_A(CBFS)@0x10000 0x26ffc0 RW_FWID_A@0x27ffc0 0x40 } - RW_SECTION_B@0x1550000 0x280000 { + RW_SECTION_B@0x1150000 0x280000 { VBLOCK_B@0x0 0x10000 FW_MAIN_B(CBFS)@0x10000 0x26ffc0 RW_FWID_B@0x27ffc0 0x40 } - RW_MISC@0x17d0000 0x30000 { + RW_MISC@0x13d0000 0x30000 { UNIFIED_MRC_CACHE@0x0 0x20000 { RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 @@ -34,7 +34,7 @@ RW_VPD(PRESERVE)@0x28000 0x2000 RW_NVRAM(PRESERVE)@0x2a000 0x6000 } - WP_RO@0x1800000 0x400000 { + WP_RO@0x1400000 0x400000 { RO_VPD(PRESERVE)@0x0 0x4000 RO_UNUSED@0x4000 0xc000 RO_SECTION@0x10000 0x3f0000 { -- To view, visit https://review.coreboot.org/c/coreboot/+/34762 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f84712b31b8ada6c72ce56497f48ece5009dd60 Gerrit-Change-Number: 34762 Gerrit-PatchSet: 1 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: abuild: Add -Z / --clean-somewhat option
by Patrick Georgi (Code Review) 28 Aug '19

28 Aug '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35136 ) Change subject: abuild: Add -Z / --clean-somewhat option ...................................................................... abuild: Add -Z / --clean-somewhat option This option removes everything in the build tree but coreboot.rom, config.build, config.h and make.log - a useful subset of the tree for further testing. Change-Id: I27e559d8d7dc90d8fe5c4ed8e25249e202e5da36 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M util/abuild/abuild 1 file changed, 12 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/35136/1 diff --git a/util/abuild/abuild b/util/abuild/abuild index ef4e46b..4a62cfa 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -398,6 +398,10 @@ if [ "$clean_work" = "true" ]; then rm -rf "${build_dir}" fi + if [ "$clean_objs" = "true" ]; then + find ${build_dir} \! $ -name coreboot.rom -o -name config.h -o -name config.build -o -name make.log $ -type f -exec rm {} + + find ${build_dir} -type d -exec rmdir -p {} + 2>/dev/null + fi return $MAKE_FAILED } @@ -595,6 +599,7 @@ (defaults to $XMLFILE) [-y|--ccache] Use ccache [-z|--clean] Remove build results when finished + [-Z|--clean-somewhat] Remove build but keep coreboot.rom + config [-V|--version] Print version number and exit [-h|--help] Print this help and exit @@ -641,12 +646,12 @@ # shellcheck disable=SC2086 if [ "${getoptbrand:0:6}" == "getopt" ]; then # Detected GNU getopt that supports long options. - args=$(getopt -l version,verbose,quiet,help,all,target:,board-variant:,payloads:,cpus:,silent,junit,config,loglevel:,remove,prefix:,update,scan-build,ccache,blobs,clang,any-toolchain,clean,outdir:,chromeos,xmlfile:,kconfig:,dir:,root:,recursive,checksum:,timeless,exitcode,asserts -o Vvqhat:b:p:c:sJCl:rP:uyBLAzo:xX:K:d:R:Ie -- "$@") || exit 1 + args=$(getopt -l version,verbose,quiet,help,all,target:,board-variant:,payloads:,cpus:,silent,junit,config,loglevel:,remove,prefix:,update,scan-build,ccache,blobs,clang,any-toolchain,clean,clean-somewhat,outdir:,chromeos,xmlfile:,kconfig:,dir:,root:,recursive,checksum:,timeless,exitcode,asserts -o Vvqhat:b:p:c:sJCl:rP:uyBLAzZo:xX:K:d:R:Ie -- "$@") || exit 1 eval set -- $args retval=$? else # Detected non-GNU getopt - args=$(getopt Vvqhat:b:p:c:sJCl:rP:uyBLAzo:xX:K:d:R:Ie "$@") + args=$(getopt Vvqhat:b:p:c:sJCl:rP:uyBLAZzo:xX:K:d:R:Ie "$@") set -- $args retval=$? fi @@ -658,6 +663,7 @@ chromeos=false clean_work=false +clean_objs=false verboseopt='V=0' customizing="" configoptions="" @@ -730,6 +736,10 @@ customizing="${customizing}, clean" clean_work=true ;; + -Z|--clean-somewhat) shift + customizing="${customizing}, clean-somewhat" + clean_objs=true + ;; -o|--outdir) shift TARGET=$1; shift ;; -- To view, visit https://review.coreboot.org/c/coreboot/+/35136 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27e559d8d7dc90d8fe5c4ed8e25249e202e5da36 Gerrit-Change-Number: 35136 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: what-jenkins-does: Fix tree pruning
by Patrick Georgi (Code Review) 28 Aug '19

28 Aug '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35112 ) Change subject: what-jenkins-does: Fix tree pruning ...................................................................... what-jenkins-does: Fix tree pruning The regex wasn't effective and it didn't help that we built into default/ and then tried to prune regular/. Just use * instead. Change-Id: Ic2feecd58658e8bac8c6e7a851737784e35b83ef Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M util/testing/Makefile.inc 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/35112/1 diff --git a/util/testing/Makefile.inc b/util/testing/Makefile.inc index 5bf3e8e..c65ce98 100644 --- a/util/testing/Makefile.inc +++ b/util/testing/Makefile.inc @@ -93,8 +93,8 @@ util/lint/lint lint-extended --junit util/abuild/abuild -o $(COREBOOT_BUILD_DIR)/chromeos $(ABUILD_OPTIONS) -x -X $(top)/abuild-chromeos.xml util/abuild/abuild -o $(COREBOOT_BUILD_DIR)/default $(ABUILD_OPTIONS) - -find $(COREBOOT_BUILD_DIR)/{regular,chromeos}/[A-Z]*/* \! $ -name coreboot.rom -o -name config.h -o -name config.build $ -type f -exec rm {} + - -find $(COREBOOT_BUILD_DIR)/{regular,chromeos}/[A-Z]*/* -type d -exec rmdir -p {} + 2>/dev/null + -find $(COREBOOT_BUILD_DIR)/*/[A-Z]*/* \! $ -name coreboot.rom -o -name config.h -o -name config.build $ -type f -exec rm {} + + -find $(COREBOOT_BUILD_DIR)/*/[A-Z]*/* -type d -exec rmdir -p {} + 2>/dev/null $(foreach tool, $(TOOLLIST), $(MAKE) CPUS=$(CPUS) V=$(V) Q=$(Q) BLD_DIR="util/$(tool)" BLD="$(tool)" MFLAGS= MAKEFLAGS= MAKETARGET= junit.xml; ) unset COREBOOT_BUILD_DIR;$(MAKE) CPUS=$(CPUS) V=$(V) Q=$(Q) BLD_DIR=payloads/nvramcui BLD=nvramcui MFLAGS= MAKEFLAGS= MAKETARGET=all junit.xml unset COREBOOT_BUILD_DIR;$(MAKE) CPUS=$(CPUS) V=$(V) Q=$(Q) BLD_DIR=payloads/coreinfo BLD=coreinfo MFLAGS= MAKEFLAGS= MAKETARGET=defaultbuild junit.xml -- To view, visit https://review.coreboot.org/c/coreboot/+/35112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2feecd58658e8bac8c6e7a851737784e35b83ef Gerrit-Change-Number: 35112 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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