coreboot-gerrit August 2019

coreboot-gerrit@coreboot.org

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1942 discussions

Change in coreboot[master]: mb/google/hatch/variants: Update the touchscreen reset dealy to 200ms
by Sumeet R Pawnikar (Code Review) 28 Aug '19

28 Aug '19

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34626 ) Change subject: mb/google/hatch/variants: Update the touchscreen reset dealy to 200ms ...................................................................... mb/google/hatch/variants: Update the touchscreen reset dealy to 200ms Set the appropriate delay of 200ms between enable and reset for Goodix Touchscreen. BUG=138413748 BRANCH=None TEST=Built and tested on Hatch system Change-Id: I15005c568f285ec7bad9a0bec4498e2fdd20782b Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/hatch/variants/hatch/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/34626/1 diff --git a/src/mainboard/google/hatch/variants/hatch/overridetree.cb b/src/mainboard/google/hatch/variants/hatch/overridetree.cb index e40a5664..fbd87b5 100644 --- a/src/mainboard/google/hatch/variants/hatch/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch/overridetree.cb @@ -89,7 +89,7 @@ register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" - register "generic.reset_delay_ms" = "10" + register "generic.reset_delay_ms" = "200" register "generic.reset_off_delay_ms" = "3" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" register "generic.enable_delay_ms" = "12" -- To view, visit https://review.coreboot.org/c/coreboot/+/34626 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15005c568f285ec7bad9a0bec4498e2fdd20782b Gerrit-Change-Number: 34626 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/x86/postcar: unexpose postcar_commit_mtrrs() symbol
by Aaron Durbin (Code Review) 28 Aug '19

28 Aug '19

Aaron Durbin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35130 ) Change subject: arch/x86/postcar: unexpose postcar_commit_mtrrs() symbol ...................................................................... arch/x86/postcar: unexpose postcar_commit_mtrrs() symbol postcar_commit_mtrrs() isn't used outside the postcar_loader compilation unit. Make it static to reduce API surface area. Change-Id: If07f34467941d00de731489867e485cfff80ea63 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- M src/arch/x86/include/arch/romstage.h M src/arch/x86/postcar_loader.c 2 files changed, 1 insertion(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/35130/1 diff --git a/src/arch/x86/include/arch/romstage.h b/src/arch/x86/include/arch/romstage.h index 7816a7c..2ac2258 100644 --- a/src/arch/x86/include/arch/romstage.h +++ b/src/arch/x86/include/arch/romstage.h @@ -58,12 +58,6 @@ void postcar_frame_common_mtrrs(struct postcar_frame *pcf); /* - * Push used MTRR and Max MTRRs on to the stack - * and return pointer to stack top. - */ -void *postcar_commit_mtrrs(struct postcar_frame *pcf); - -/* * fill_postcar_frame() is called after raminit completes and right before * calling run_postcar_phase(). Implementation should call postcar_frame_add_mtrr() * to tag memory ranges as cacheable to speed up execution of postcar and diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index 4a7d549..b9487a7 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -147,7 +147,7 @@ /* We do not return here. */ } -void *postcar_commit_mtrrs(struct postcar_frame *pcf) +static void postcar_commit_mtrrs(struct postcar_frame *pcf) { /* * Place the number of used variable MTRRs on stack then max number -- To view, visit https://review.coreboot.org/c/coreboot/+/35130 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If07f34467941d00de731489867e485cfff80ea63 Gerrit-Change-Number: 35130 Gerrit-PatchSet: 1 Gerrit-Owner: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: google/leon: Add DRIVERS_I2C_RTD2132
by Kyösti Mälkki (Code Review) 28 Aug '19

28 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35106 ) Change subject: google/leon: Add DRIVERS_I2C_RTD2132 ...................................................................... google/leon: Add DRIVERS_I2C_RTD2132 This is LVDS bridge, I assume this was lost while upstreaming or converting boards to variants. Change-Id: I816a6b4035c4e935150cc77089c4224eee719c10 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/slippy/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/35106/1 diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index 242876d..35fced0 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -16,6 +16,7 @@ select INTEL_INT15 select MAINBOARD_HAS_LIBGFXINIT select INTEL_GMA_HAVE_VBT + select DRIVERS_I2C_RTD2132 if BOARD_GOOGLE_LEON if BOARD_GOOGLE_BASEBOARD_SLIPPY -- To view, visit https://review.coreboot.org/c/coreboot/+/35106 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I816a6b4035c4e935150cc77089c4224eee719c10 Gerrit-Change-Number: 35106 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: lenovo/t431s,w530: Add DRIVERS_RICOH_RCE822
by Kyösti Mälkki (Code Review) 28 Aug '19

28 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35105 ) Change subject: lenovo/t431s,w530: Add DRIVERS_RICOH_RCE822 ...................................................................... lenovo/t431s,w530: Add DRIVERS_RICOH_RCE822 Device is present in devicetree but not included in the build. Change-Id: I8555d94902e94c623d8fbe6f1a4ffe7637988530 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/lenovo/t430s/Kconfig M src/mainboard/lenovo/t530/Kconfig 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/35105/1 diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig index b0a22aa..0c7d075 100644 --- a/src/mainboard/lenovo/t430s/Kconfig +++ b/src/mainboard/lenovo/t430s/Kconfig @@ -22,6 +22,7 @@ select GFX_GMA_INTERNAL_IS_LVDS if BOARD_LENOVO_T430S select INTEL_GMA_HAVE_VBT select MAINBOARD_USES_IFD_GBE_REGION + select DRIVERS_RICOH_RCE822 if BOARD_LENOVO_T431S # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index 5fd9118..f63a120 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -21,6 +21,7 @@ select GFX_GMA_INTERNAL_IS_LVDS select INTEL_GMA_HAVE_VBT select MAINBOARD_USES_IFD_GBE_REGION + select DRIVERS_RICOH_RCE822 if BOARD_LENOVO_W530 # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE -- To view, visit https://review.coreboot.org/c/coreboot/+/35105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8555d94902e94c623d8fbe6f1a4ffe7637988530 Gerrit-Change-Number: 35105 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mediatek/mt8183: Set DRAM vlotage for each DRAM frequency
by Paul Menzel (Code Review) 28 Aug '19

28 Aug '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35017 ) Change subject: mediatek/mt8183: Set DRAM vlotage for each DRAM frequency ...................................................................... Patch Set 2: (2 comments) https://review.coreboot.org/c/coreboot/+/35017/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/35017/2//COMMIT_MSG@7 PS2, Line 7: vlotage voltage https://review.coreboot.org/c/coreboot/+/35017/2/src/soc/mediatek/mt8183/em… File src/soc/mediatek/mt8183/emi.c: https://review.coreboot.org/c/coreboot/+/35017/2/src/soc/mediatek/mt8183/em… PS2, Line 389: #if DUAL_FREQ_K Can you implement this without preprocessor statements? -- To view, visit https://review.coreboot.org/c/coreboot/+/35017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9539473ff708f9d0d39eb17bd3fdcb916265d33e Gerrit-Change-Number: 35017 Gerrit-PatchSet: 2 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: huayang duan <huayangduan(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 28 Aug 2019 12:10:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cnl: Add CML GT IDs
by Meera Ravindranath (Code Review) 28 Aug '19

28 Aug '19

Hello Usha P, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/35120 to review the following change. Change subject: soc/intel/cnl: Add CML GT IDs ...................................................................... soc/intel/cnl: Add CML GT IDs TEST=Build and boot CMLRVP. Change-Id: Ib79995606f6da12bfa7aa5c1a1dbc0b972bb1688 Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Signed-off-by: Usha P <usha.p(a)intel.com> --- M src/include/device/pci_ids.h M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/common/block/graphics/graphics.c 3 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/35120/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index cdd1c62..5ad61e0 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3083,6 +3083,8 @@ #define PCI_DEVICE_ID_INTEL_CML_GT2_ULT_2 0x9B4A #define PCI_DEVICE_ID_INTEL_CML_GT1_ULT_3 0x9B2B #define PCI_DEVICE_ID_INTEL_CML_GT1_ULT_4 0x9B2C +#define PCI_DEVICE_ID_INTEL_CML_GT2_ULT_5 0x9BAA +#define PCI_DEVICE_ID_INTEL_CML_GT2_ULT_6 0x9BCA #define PCI_DEVICE_ID_INTEL_CML_GT2_ULT_3 0x9B4B #define PCI_DEVICE_ID_INTEL_CML_GT2_ULT_4 0x9B4C #define PCI_DEVICE_ID_INTEL_CML_GT1_ULX_1 0x9B20 diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index de2feaf..67d991c 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -135,6 +135,8 @@ { PCI_DEVICE_ID_INTEL_CML_GT1_ULT_4, "CometLake ULT GT1" }, { PCI_DEVICE_ID_INTEL_CML_GT2_ULT_3, "CometLake ULT GT2" }, { PCI_DEVICE_ID_INTEL_CML_GT2_ULT_4, "CometLake ULT GT2" }, + { PCI_DEVICE_ID_INTEL_CML_GT2_ULT_5, "CometLake ULT GT2" }, + { PCI_DEVICE_ID_INTEL_CML_GT2_ULT_6, "CometLake ULT GT2" } { PCI_DEVICE_ID_INTEL_CML_GT1_ULX_1, "CometLake ULX GT1" }, { PCI_DEVICE_ID_INTEL_CML_GT2_ULX_1, "CometLake ULX GT2" }, { PCI_DEVICE_ID_INTEL_CML_GT1_S_1, "CometLake S GT1" }, diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 2b4c4a7..7aece76 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -177,6 +177,8 @@ PCI_DEVICE_ID_INTEL_CML_GT2_ULT_2, PCI_DEVICE_ID_INTEL_CML_GT1_ULT_3, PCI_DEVICE_ID_INTEL_CML_GT1_ULT_4, + PCI_DEVICE_ID_INTEL_CML_GT2_ULT_5, + PCI_DEVICE_ID_INTEL_CML_GT2_ULT_6, PCI_DEVICE_ID_INTEL_CML_GT2_ULT_3, PCI_DEVICE_ID_INTEL_CML_GT2_ULT_4, PCI_DEVICE_ID_INTEL_CML_GT1_ULX_1, -- To view, visit https://review.coreboot.org/c/coreboot/+/35120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib79995606f6da12bfa7aa5c1a1dbc0b972bb1688 Gerrit-Change-Number: 35120 Gerrit-PatchSet: 1 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mediatek/mt8183: Enable DRAM frequency 3600Mbps for EMCP DDR
by Huayang Duan (Code Review) 28 Aug '19

28 Aug '19

Huayang Duan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34990 ) Change subject: mediatek/mt8183: Enable DRAM frequency 3600Mbps for EMCP DDR ...................................................................... Patch Set 3: (3 comments) https://review.coreboot.org/c/coreboot/+/34990/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/34990/2//COMMIT_MSG@9 PS2, Line 9: 3600Mbs > Mbps Done https://review.coreboot.org/c/coreboot/+/34990/2//COMMIT_MSG@11 PS2, Line 11: proformance > performance Done https://review.coreboot.org/c/coreboot/+/34990/2/src/soc/mediatek/mt8183/em… File src/soc/mediatek/mt8183/emi.c: https://review.coreboot.org/c/coreboot/+/34990/2/src/soc/mediatek/mt8183/em… PS2, Line 23: #define LP4X_HIGH_FREQ LP4X_DDR3600 : #define LP4X_MIDDLE_FREQ LP4X_DDR3200 : #define LP4X_LOW_FREQ LP4X_DDR1600 > Consider aligning these 3 lines: […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/34990 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6a9c2c390feeb9497b051a255b29566909e656 Gerrit-Change-Number: 34990 Gerrit-PatchSet: 3 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: SJ Huang <sj.huang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: huayang duan <huayangduan(a)gmail.com> Gerrit-CC: Huayang Duan <huayang.duan(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Wed, 28 Aug 2019 09:41:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mediatek/mt8183: Enable DRAM frequency 3600Mbps for EMCP DDR
by huayang duan (Code Review) 28 Aug '19

28 Aug '19

Hello Yu-Ping Wu, Julius Werner, You-Cheng Syu, Hung-Te Lin, SJ Huang, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/34990 to look at the new patch set (#3). Change subject: mediatek/mt8183: Enable DRAM frequency 3600Mbps for EMCP DDR ...................................................................... mediatek/mt8183: Enable DRAM frequency 3600Mbps for EMCP DDR Devices using eMCP may run in a high DRAM frequency (e.g., 3600Mbps) while discrete DRAM can only run at 3200Mbps. Enable 3600Mbps for EMCP DDR for better system preformance. BUG=b:80501386 BRANCH=none TEST=Boots correctly and stress test pass on Kukui. Change-Id: Iab6a9c2c390feeb9497b051a255b29566909e656 Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/soc/mediatek/mt8183/emi.c 1 file changed, 8 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/34990/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/34990 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6a9c2c390feeb9497b051a255b29566909e656 Gerrit-Change-Number: 34990 Gerrit-PatchSet: 3 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: SJ Huang <sj.huang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: huayang duan <huayangduan(a)gmail.com> Gerrit-CC: Huayang Duan <huayang.duan(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/hatch: Enable Override DLLs for Kindred
by Jamie Chen (Code Review) 28 Aug '19

28 Aug '19

Jamie Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35094 ) Change subject: mb/google/hatch: Enable Override DLLs for Kindred ...................................................................... mb/google/hatch: Enable Override DLLs for Kindred Enable SOC_INTEL_COMMON_MMC_OVERRIDE for Kindred BUG=b:136784418 BRANCH=none TEST=Boot to OS 100 times on Kindred proto 1 board. Change-Id: I390d237b9119ae42f4b0bb802bf9857552af78bf Signed-off-by: Jamie Chen <jamie.chen(a)intel.com> --- M src/mainboard/google/hatch/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/35094/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 5c7c267..fc2dae3 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -122,4 +122,8 @@ select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN select VBOOT_LID_SWITCH +config SOC_INTEL_COMMON_MMC_OVERRIDE + bool + default y if BOARD_GOOGLE_KINDRED + endif # BOARD_GOOGLE_BASEBOARD_HATCH -- To view, visit https://review.coreboot.org/c/coreboot/+/35094 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I390d237b9119ae42f4b0bb802bf9857552af78bf Gerrit-Change-Number: 35094 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Chen <jamie.chen(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: intel/common/mmc: Provide mmc.c for setting dll registers.
by Jamie Chen (Code Review) 28 Aug '19

28 Aug '19

Hello Kane Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/35040 to review the following change. Change subject: intel/common/mmc: Provide mmc.c for setting dll registers. ...................................................................... intel/common/mmc: Provide mmc.c for setting dll registers. Currently, we don't have UPDs to set emmc settings per mainboard on CML. This code change is to create mmc.c to provide interface to override dll settings per mainboard. Notice: mainboard_get_mmc_dll function will override the dll values in FSP. BUG=b:131401116 BRANCH=none TEST=Boot to OS and confirm the dll values have been overrided. Change-Id: Ib3c72b9851f41585ec099d8ae83a721af87ed383 Signed-off-by: Kane Chen <kane.chen(a)intel.com> Signed-off-by: Jamie Chen <jamie.chen(a)intel.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/include/intelblocks/early_mmc.h M src/soc/intel/common/block/scs/Makefile.inc M src/soc/intel/common/block/scs/early_mmc.c A src/soc/intel/common/block/scs/mmc.c 5 files changed, 107 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/35040/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 3ac6560..f7a4c95 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3220,6 +3220,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_SD 0xa375 #define PCI_DEVICE_ID_INTEL_ICL_SD 0x34f8 #define PCI_DEVICE_ID_INTEL_CMP_SD 0x02f5 +#define PCI_DEVICE_ID_INTEL_CMP_MMC 0x02c4 /* Intel EMMC device Ids */ #define PCI_DEVICE_ID_INTEL_SKL_EMMC 0x9d2b diff --git a/src/soc/intel/common/block/include/intelblocks/early_mmc.h b/src/soc/intel/common/block/include/intelblocks/early_mmc.h index 39aaf58..2ec22ec 100644 --- a/src/soc/intel/common/block/include/intelblocks/early_mmc.h +++ b/src/soc/intel/common/block/include/intelblocks/early_mmc.h @@ -60,6 +60,23 @@ * returns 0, if able to get register settings; otherwise returns -1 */ int soc_get_mmc_dll(struct mmc_dll_params *params); +/* + * SOC specific API to set mmc delay register settings. + * returns 0, if able to set register settings; otherwise returns -1 + */ +int set_mmc_dll(void *ioaddr); +/* + * mainboard specific API to get mmc delay register settings. + * returns 0, if able to get register settings; otherwise returns -1 + */ +int mainboard_get_mmc_dll(struct mmc_dll_params *params); + +#define EMMC_TX_CMD_CNTL_OFFSET 0x820 +#define EMMC_TX_DATA_CNTL1_OFFSET 0x824 +#define EMMC_TX_DATA_CNTL2_OFFSET 0x828 +#define EMMC_RX_CMD_DATA_CNTL1_OFFSET 0x82C +#define EMMC_RX_STROBE_CNTL_OFFSET 0x830 +#define EMMC_RX_CMD_DATA_CNTL2_OFFSET 0x834 #if CONFIG(SOC_INTEL_COMMON_EARLY_MMC_WAKE) /* diff --git a/src/soc/intel/common/block/scs/Makefile.inc b/src/soc/intel/common/block/scs/Makefile.inc index 1160802..707a334 100644 --- a/src/soc/intel/common/block/scs/Makefile.inc +++ b/src/soc/intel/common/block/scs/Makefile.inc @@ -1,2 +1,3 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SCS) += sd.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SCS) += mmc.c romstage-$(CONFIG_SOC_INTEL_COMMON_EARLY_MMC_WAKE) += early_mmc.c diff --git a/src/soc/intel/common/block/scs/early_mmc.c b/src/soc/intel/common/block/scs/early_mmc.c index 8f47ec7..297b9c4 100644 --- a/src/soc/intel/common/block/scs/early_mmc.c +++ b/src/soc/intel/common/block/scs/early_mmc.c @@ -26,13 +26,6 @@ #include <soc/pci_devs.h> #include <string.h> -#define EMMC_TX_CMD_CNTL_OFFSET 0x820 -#define EMMC_TX_DATA_CNTL1_OFFSET 0x824 -#define EMMC_TX_DATA_CNTL2_OFFSET 0x828 -#define EMMC_RX_CMD_DATA_CNTL1_OFFSET 0x82C -#define EMMC_RX_STROBE_CNTL_OFFSET 0x830 -#define EMMC_RX_CMD_DATA_CNTL2_OFFSET 0x834 - void soc_sd_mmc_controller_quirks(struct sd_mmc_ctrlr *ctrlr) { uint32_t f_min, f_max; @@ -62,32 +55,6 @@ ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY)); } -static int set_mmc_dll(void *ioaddr) -{ - struct mmc_dll_params dll_params; - - if (soc_get_mmc_dll(&dll_params) < 0) { - printk(BIOS_ERR, - "MMC early init: failed to get mmc DLL parameters\n"); - return -1; - } - - write32(ioaddr + EMMC_TX_DATA_CNTL1_OFFSET, - dll_params.emmc_tx_data_cntl1); - write32(ioaddr + EMMC_TX_DATA_CNTL2_OFFSET, - dll_params.emmc_tx_data_cntl2); - write32(ioaddr + EMMC_RX_CMD_DATA_CNTL1_OFFSET, - dll_params.emmc_rx_cmd_data_cntl1); - write32(ioaddr + EMMC_RX_CMD_DATA_CNTL2_OFFSET, - dll_params.emmc_rx_cmd_data_cntl2); - write32(ioaddr + EMMC_RX_STROBE_CNTL_OFFSET, - dll_params.emmc_rx_strobe_cntl); - write32(ioaddr + EMMC_TX_CMD_CNTL_OFFSET, - dll_params.emmc_tx_cmd_cntl); - - return 0; -} - static void set_early_mmc_wake_status(int32_t status) { int32_t *ms_cbmem; diff --git a/src/soc/intel/common/block/scs/mmc.c b/src/soc/intel/common/block/scs/mmc.c new file mode 100644 index 0000000..b55db4a --- /dev/null +++ b/src/soc/intel/common/block/scs/mmc.c @@ -0,0 +1,88 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/pci.h> +#include <device/pci_ids.h> +#include <console/console.h> +#include <intelblocks/early_mmc.h> + +/* Common weak definition, needs to be implemented in mainboard */ +int __weak mainboard_get_mmc_dll(struct mmc_dll_params *params) +{ + return -1; +} + +int set_mmc_dll(void *ioaddr) +{ + struct mmc_dll_params dll_params; + + if (mainboard_get_mmc_dll(&dll_params) < 0) { + printk(BIOS_INFO, "Skip Emmc dll value programming \n"); + return -1; + } + + printk(BIOS_INFO, "Override emmc dll value \n"); + + write32(ioaddr + EMMC_TX_DATA_CNTL1_OFFSET, + dll_params.emmc_tx_data_cntl1); + + write32(ioaddr + EMMC_TX_DATA_CNTL2_OFFSET, + dll_params.emmc_tx_data_cntl2); + + write32(ioaddr + EMMC_RX_CMD_DATA_CNTL1_OFFSET, + dll_params.emmc_rx_cmd_data_cntl1); + + write32(ioaddr + EMMC_RX_CMD_DATA_CNTL2_OFFSET, + dll_params.emmc_rx_cmd_data_cntl2); + + write32(ioaddr + EMMC_RX_STROBE_CNTL_OFFSET, + dll_params.emmc_rx_strobe_cntl); + + write32(ioaddr + EMMC_TX_CMD_CNTL_OFFSET, + dll_params.emmc_tx_cmd_cntl); + + return 0; +} + +static void mmc_soc_init(struct device *dev) +{ + uint32_t *cfg0; + const struct resource *res; + + res = find_resource(dev, PCI_BASE_ADDRESS_0); + cfg0 = (void *)(uintptr_t)(res->base); + + set_mmc_dll(cfg0); +} + + +static struct device_operations dev_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = mmc_soc_init, + .ops_pci = &pci_dev_ops_pci, +}; + +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_CMP_MMC, + 0 +}; + +static const struct pci_driver pch_sd __pci_driver = { + .ops = &dev_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/35040 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3c72b9851f41585ec099d8ae83a721af87ed383 Gerrit-Change-Number: 35040 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit August 2019