coreboot-gerrit August 2019

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Change in coreboot[master]: soc/intel/common: Include cometlake EMMC controller ID
by Jamie Chen (Code Review) 26 Aug '19

26 Aug '19

Jamie Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35093 ) Change subject: soc/intel/common: Include cometlake EMMC controller ID ...................................................................... soc/intel/common: Include cometlake EMMC controller ID Add cometlake EMMC controller ID BUG=none BRANCH=none TEST=none Change-Id: I3943dad57918df3df7885c2e2d3a86ab0e1d6008 Signed-off-by: Jamie Chen <jamie.chen(a)intel.com> --- M src/include/device/pci_ids.h 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/35093/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 2501640..b4cbc38 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3221,6 +3221,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_SD 0xa375 #define PCI_DEVICE_ID_INTEL_ICL_SD 0x34f8 #define PCI_DEVICE_ID_INTEL_CMP_SD 0x02f5 +#define PCI_DEVICE_ID_INTEL_CMP_MMC 0x02c4 /* Intel EMMC device Ids */ #define PCI_DEVICE_ID_INTEL_SKL_EMMC 0x9d2b -- To view, visit https://review.coreboot.org/c/coreboot/+/35093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3943dad57918df3df7885c2e2d3a86ab0e1d6008 Gerrit-Change-Number: 35093 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Chen <jamie.chen(a)intel.com> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: AUTHORS: Move src/arch/arm64 copyrights into AUTHORS file
by Martin Roth (Code Review) 26 Aug '19

26 Aug '19

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34606 ) Change subject: AUTHORS: Move src/arch/arm64 copyrights into AUTHORS file ...................................................................... AUTHORS: Move src/arch/arm64 copyrights into AUTHORS file As discussed on the mailing list and voted upon, the coreboot project is going to move the majority of copyrights out of the headers and into an AUTHORS file. This will happen a bit at a time, as we'll be unifying license headers at the same time. Additional changes in this patch: - Make sure files say that they're part of the coreboot project - Move descriptions below the license header Note that the file include/arch/acpi.h is a fantastic example of why moving to the authors file is needed. Excluding the guard statements, it has 8 lines of copyrights for 3 function declarations. Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I334baab2b4311eb1bd9ce3f67f49a68e8b73630c --- M AUTHORS M src/arch/arm64/Makefile.inc M src/arch/arm64/arch_timer.c M src/arch/arm64/arm_tf.c M src/arch/arm64/armv8/Makefile.inc M src/arch/arm64/armv8/bootblock.S M src/arch/arm64/armv8/cpu.S M src/arch/arm64/armv8/exception.c M src/arch/arm64/boot.c M src/arch/arm64/div0.c M src/arch/arm64/eabi_compat.c M src/arch/arm64/fit_payload.c M src/arch/arm64/include/arch/acpi.h M src/arch/arm64/include/arch/asm.h M src/arch/arm64/include/arch/cbconfig.h M src/arch/arm64/include/arch/early_variables.h M src/arch/arm64/include/arch/header.ld M src/arch/arm64/include/arch/memlayout.h M src/arch/arm64/include/arch/mpidr.h M src/arch/arm64/include/arch/pci_ops.h M src/arch/arm64/include/arch/stages.h M src/arch/arm64/include/arch/transition.h M src/arch/arm64/include/arm_tf.h M src/arch/arm64/include/arm_tf_temp.h M src/arch/arm64/include/armv8/arch/barrier.h M src/arch/arm64/include/armv8/arch/cpu.h M src/arch/arm64/include/armv8/arch/exception.h M src/arch/arm64/include/armv8/arch/lib_helpers.h M src/arch/arm64/include/armv8/arch/mmio.h M src/arch/arm64/include/armv8/arch/mmu.h M src/arch/arm64/include/clocks.h M src/arch/arm64/include/cpu/cortex_a57.h M src/arch/arm64/memcpy.S M src/arch/arm64/memmove.S M src/arch/arm64/memset.S M src/arch/arm64/romstage.c M src/arch/arm64/tables.c M src/arch/arm64/transition.c M src/arch/arm64/transition_asm.S 39 files changed, 35 insertions(+), 100 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/34606/1 diff --git a/AUTHORS b/AUTHORS index ab4f082..ad8433e 100644 --- a/AUTHORS +++ b/AUTHORS @@ -6,27 +6,35 @@ # git log --pretty=format:%an | sort | uniq # +Alex Züpke Alexander Couzens Alexandru Gagniuc -Alex Züpke +ARM Limited and Contributors +ARM Ltd coresystems GmbH DENX Software Engineering Eric Biederman +Facebook, Inc. Free Software Foundation, Inc. Gary Jennejohn Google Inc. Kshitij Marius Gröger MontaVista Software, Inc. +Nick Barker Per Odlund +Raptor Engineering Richard Woodruff Ronald G. Minnich Russell King +Siemens AG Steve Magnani +SUSE LINUX AG Syed Mohammed Khasim Texas Instruments The Chromium OS Authors The Linux Foundation +Timothy Pearson Wolfgang Denk @@ -34,3 +42,4 @@ # Directories transferred src/acpi src/arch/arm +src/arch/arm64 diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index 6bb7196..30bc6ac 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -2,12 +2,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2014 Google Inc. -## Copyright (C) 2012-2013 The ChromiumOS Authors -## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> -## Copyright (C) 2009-2010 coresystems GmbH -## Copyright (C) 2009 Ronald G. Minnich -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm64/arch_timer.c b/src/arch/arm64/arch_timer.c index e7f3732..2db235a 100644 --- a/src/arch/arm64/arch_timer.c +++ b/src/arch/arm64/arch_timer.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and * only version 2 as published by the Free Software Foundation. diff --git a/src/arch/arm64/arm_tf.c b/src/arch/arm64/arm_tf.c index 291e4ee..5059a89 100644 --- a/src/arch/arm64/arm_tf.c +++ b/src/arch/arm64/arm_tf.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm64/armv8/Makefile.inc b/src/arch/arm64/armv8/Makefile.inc index 44ebdef..127c5f1 100644 --- a/src/arch/arm64/armv8/Makefile.inc +++ b/src/arch/arm64/armv8/Makefile.inc @@ -2,8 +2,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2014 The ChromiumOS Authors -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm64/armv8/bootblock.S b/src/arch/arm64/armv8/bootblock.S index 3950f55..64d2405 100644 --- a/src/arch/arm64/armv8/bootblock.S +++ b/src/arch/arm64/armv8/bootblock.S @@ -1,7 +1,5 @@ /* - * Early initialization code for aarch64 (a.k.a. armv8) - * - * Copyright 2015 Google Inc. + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -12,6 +10,8 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. + * + * Early initialization code for aarch64 (a.k.a. armv8) */ #include <arch/asm.h> diff --git a/src/arch/arm64/armv8/cpu.S b/src/arch/arm64/armv8/cpu.S index 935f1fe..2bc4def 100644 --- a/src/arch/arm64/armv8/cpu.S +++ b/src/arch/arm64/armv8/cpu.S @@ -1,8 +1,5 @@ /* - * Optimized assembly for low-level CPU operations on ARM64 processors. - * - * Copyright (c) 2010 Per Odlund <per.odlund(a)armagedon.se> - * Copyright (c) 2014 Google Inc. + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -12,6 +9,8 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. + * + * Optimized assembly for low-level CPU operations on ARM64 processors. */ #include <arch/asm.h> diff --git a/src/arch/arm64/armv8/exception.c b/src/arch/arm64/armv8/exception.c index 58a3523..579e104 100644 --- a/src/arch/arm64/armv8/exception.c +++ b/src/arch/arm64/armv8/exception.c @@ -1,5 +1,5 @@ /* - * This file is part of the libpayload project. + * This file is part of the coreboot project. * * Copyright 2013 Google Inc. * diff --git a/src/arch/arm64/boot.c b/src/arch/arm64/boot.c index 7fbc525..58d7234 100644 --- a/src/arch/arm64/boot.c +++ b/src/arch/arm64/boot.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm64/div0.c b/src/arch/arm64/div0.c index afd9dad..daf1d92 100644 --- a/src/arch/arm64/div0.c +++ b/src/arch/arm64/div0.c @@ -1,6 +1,5 @@ /* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/arch/arm64/eabi_compat.c b/src/arch/arm64/eabi_compat.c index a6f40a4..79b2017 100644 --- a/src/arch/arm64/eabi_compat.c +++ b/src/arch/arm64/eabi_compat.c @@ -1,7 +1,5 @@ /* - * Utility functions needed for (some) EABI conformant tool chains. - * - * (C) Copyright 2009 Wolfgang Denk <wd(a)denx.de> + * This file is part of the coreboot project. * * This program is Free Software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -12,6 +10,8 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. + * + * Utility functions needed for (some) EABI conformant tool chains. */ int raise (int signum) __attribute__((used)); diff --git a/src/arch/arm64/fit_payload.c b/src/arch/arm64/fit_payload.c index 46bea23..4ade1c7 100644 --- a/src/arch/arm64/fit_payload.c +++ b/src/arch/arm64/fit_payload.c @@ -1,6 +1,5 @@ /* - * Copyright 2013 Google Inc. - * Copyright 2018 Facebook, Inc. + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/arch/arm64/include/arch/acpi.h b/src/arch/arm64/include/arch/acpi.h index 6e16482..4015d18 100644 --- a/src/arch/arm64/include/arch/acpi.h +++ b/src/arch/arm64/include/arch/acpi.h @@ -1,15 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2004 SUSE LINUX AG - * Copyright (C) 2004 Nick Barker - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, - * Raptor Engineering - * Copyright (C) 2016 Siemens AG - * (Written by Stefan Reinauer <stepan(a)coresystems.de>) - * Copyright 2018-present Facebook, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm64/include/arch/asm.h b/src/arch/arm64/include/arch/asm.h index b52724f..7d3ad7e 100644 --- a/src/arch/arm64/include/arch/asm.h +++ b/src/arch/arm64/include/arch/asm.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm64/include/arch/cbconfig.h b/src/arch/arm64/include/arch/cbconfig.h index 9467f52..35c1387 100644 --- a/src/arch/arm64/include/arch/cbconfig.h +++ b/src/arch/arm64/include/arch/cbconfig.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm64/include/arch/early_variables.h b/src/arch/arm64/include/arch/early_variables.h index c469446..9f06923 100644 --- a/src/arch/arm64/include/arch/early_variables.h +++ b/src/arch/arm64/include/arch/early_variables.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm64/include/arch/header.ld b/src/arch/arm64/include/arch/header.ld index 9d8764e..dcba068 100644 --- a/src/arch/arm64/include/arch/header.ld +++ b/src/arch/arm64/include/arch/header.ld @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm64/include/arch/memlayout.h b/src/arch/arm64/include/arch/memlayout.h index a3fdd66..984a09b 100644 --- a/src/arch/arm64/include/arch/memlayout.h +++ b/src/arch/arm64/include/arch/memlayout.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm64/include/arch/mpidr.h b/src/arch/arm64/include/arch/mpidr.h index 8d7651e..cc43309 100644 --- a/src/arch/arm64/include/arch/mpidr.h +++ b/src/arch/arm64/include/arch/mpidr.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm64/include/arch/pci_ops.h b/src/arch/arm64/include/arch/pci_ops.h index 7a62d4a..65dd059 100644 --- a/src/arch/arm64/include/arch/pci_ops.h +++ b/src/arch/arm64/include/arch/pci_ops.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm64/include/arch/stages.h b/src/arch/arm64/include/arch/stages.h index 2d6d583..d86172b 100644 --- a/src/arch/arm64/include/arch/stages.h +++ b/src/arch/arm64/include/arch/stages.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 The ChromiumOS Authors - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm64/include/arch/transition.h b/src/arch/arm64/include/arch/transition.h index 290265e..8a49eed 100644 --- a/src/arch/arm64/include/arch/transition.h +++ b/src/arch/arm64/include/arch/transition.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm64/include/arm_tf.h b/src/arch/arm64/include/arm_tf.h index ea5a0f4..692a5be 100644 --- a/src/arch/arm64/include/arm_tf.h +++ b/src/arch/arm64/include/arm_tf.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm64/include/arm_tf_temp.h b/src/arch/arm64/include/arm_tf_temp.h index 8db5dcb..f8ee48d 100644 --- a/src/arch/arm64/include/arm_tf_temp.h +++ b/src/arch/arm64/include/arm_tf_temp.h @@ -1,4 +1,6 @@ /* + * This file is part of the coreboot project. + * * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/src/arch/arm64/include/armv8/arch/barrier.h b/src/arch/arm64/include/armv8/arch/barrier.h index 3c3feb6..8da2cc2 100644 --- a/src/arch/arm64/include/armv8/arch/barrier.h +++ b/src/arch/arm64/include/armv8/arch/barrier.h @@ -1,7 +1,5 @@ /* - * Based on arch/arm/include/asm/barrier.h - * - * Copyright (C) 2012 ARM Ltd. + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -11,6 +9,8 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. + * + * Based on arch/arm/include/asm/barrier.h */ #ifndef __ASM_ARM_BARRIER_H #define __ASM_ARM_BARRIER_H diff --git a/src/arch/arm64/include/armv8/arch/cpu.h b/src/arch/arm64/include/armv8/arch/cpu.h index 6e096cc..ccad4d2 100644 --- a/src/arch/arm64/include/armv8/arch/cpu.h +++ b/src/arch/arm64/include/armv8/arch/cpu.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm64/include/armv8/arch/exception.h b/src/arch/arm64/include/armv8/arch/exception.h index f897fef..155060f 100644 --- a/src/arch/arm64/include/armv8/arch/exception.h +++ b/src/arch/arm64/include/armv8/arch/exception.h @@ -1,5 +1,5 @@ /* - * This file is part of the libpayload project. + * This file is part of the coreboot project. * * Copyright 2013 Google Inc. * diff --git a/src/arch/arm64/include/armv8/arch/lib_helpers.h b/src/arch/arm64/include/armv8/arch/lib_helpers.h index b6d067c..0afbf82 100644 --- a/src/arch/arm64/include/armv8/arch/lib_helpers.h +++ b/src/arch/arm64/include/armv8/arch/lib_helpers.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/arch/arm64/include/armv8/arch/mmio.h b/src/arch/arm64/include/armv8/arch/mmio.h index aabfa87..4342fc6 100644 --- a/src/arch/arm64/include/armv8/arch/mmio.h +++ b/src/arch/arm64/include/armv8/arch/mmio.h @@ -1,9 +1,5 @@ /* - * Originally imported from linux/include/asm-arm/io.h. This file has changed - * substantially since then. - * - * Copyright 2014 Google Inc. - * Copyright (C) 1996-2000 Russell King + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -14,16 +10,8 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * Modifications: - * 08-Apr-2013 G Replaced several macros with inlines for type safety. - * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both - * constant addresses and variable addresses. - * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture - * specific IO header files. - * 27-Mar-1999 PJB Second parameter of memcpy_toio is const.. - * 04-Apr-1999 PJB Added check_signature. - * 12-Dec-1999 RMK More cleanups - * 18-Jun-2000 RMK Removed virt_to_* and friends definitions + * Originally imported from linux/include/asm-arm/io.h. This file has changed + * substantially since then. */ #ifndef __ARCH_MMIO_H__ diff --git a/src/arch/arm64/include/armv8/arch/mmu.h b/src/arch/arm64/include/armv8/arch/mmu.h index 6c83749..4b6d787 100644 --- a/src/arch/arm64/include/armv8/arch/mmu.h +++ b/src/arch/arm64/include/armv8/arch/mmu.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm64/include/clocks.h b/src/arch/arm64/include/clocks.h index 60afb44..4904b6e 100644 --- a/src/arch/arm64/include/clocks.h +++ b/src/arch/arm64/include/clocks.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011 The Chromium OS Authors. + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/arch/arm64/include/cpu/cortex_a57.h b/src/arch/arm64/include/cpu/cortex_a57.h index 1a1becd..3259934 100644 --- a/src/arch/arm64/include/cpu/cortex_a57.h +++ b/src/arch/arm64/include/cpu/cortex_a57.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm64/memcpy.S b/src/arch/arm64/memcpy.S index 9cfbbb3..ef37ea5 100644 --- a/src/arch/arm64/memcpy.S +++ b/src/arch/arm64/memcpy.S @@ -1,5 +1,5 @@ /* - * Copyright (C) 2013 ARM Ltd. + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/src/arch/arm64/memmove.S b/src/arch/arm64/memmove.S index fc704f7..ac28650 100644 --- a/src/arch/arm64/memmove.S +++ b/src/arch/arm64/memmove.S @@ -1,5 +1,5 @@ /* - * Copyright (C) 2013 ARM Ltd. + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/src/arch/arm64/memset.S b/src/arch/arm64/memset.S index a6e98b7..5b61b31 100644 --- a/src/arch/arm64/memset.S +++ b/src/arch/arm64/memset.S @@ -1,5 +1,5 @@ /* - * Copyright (C) 2013 ARM Ltd. + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/src/arch/arm64/romstage.c b/src/arch/arm64/romstage.c index 8cdb16b..58c47e7 100644 --- a/src/arch/arm64/romstage.c +++ b/src/arch/arm64/romstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google Inc. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/arch/arm64/tables.c b/src/arch/arm64/tables.c index 492eadd..62334a7 100644 --- a/src/arch/arm64/tables.c +++ b/src/arch/arm64/tables.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2003 Eric Biederman - * Copyright (C) 2005 Steve Magnani - * Copyright (C) 2008-2009 coresystems GmbH - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm64/transition.c b/src/arch/arm64/transition.c index b1ab2fc..3e8d7f0 100644 --- a/src/arch/arm64/transition.c +++ b/src/arch/arm64/transition.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm64/transition_asm.S b/src/arch/arm64/transition_asm.S index 73821c8..718832b 100644 --- a/src/arch/arm64/transition_asm.S +++ b/src/arch/arm64/transition_asm.S @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. -- To view, visit https://review.coreboot.org/c/coreboot/+/34606 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I334baab2b4311eb1bd9ce3f67f49a68e8b73630c Gerrit-Change-Number: 34606 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

2 8

Change in coreboot[master]: util/abuild: Ensure .xcompile exists
by Aaron Durbin (Code Review) 26 Aug '19

26 Aug '19

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29483 ) Change subject: util/abuild: Ensure .xcompile exists ...................................................................... Patch Set 1: (1 comment) Maybe add more to the commit description to explain the scenario this is needed? https://review.coreboot.org/c/coreboot/+/29483/1/util/abuild/abuild File util/abuild/abuild: https://review.coreboot.org/c/coreboot/+/29483/1/util/abuild/abuild@759 PS1, Line 759: $MAKE -C"${ROOT}" .xcompile || exit 1 I'm not if this does fix things yet, but I was trying to run this myself on the command line and the recipe for .xcompile was hidden. Sounds like this could fix my problem. -- To view, visit https://review.coreboot.org/c/coreboot/+/29483 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib485e7741b7700fa241c192e60900ae5f1d977f5 Gerrit-Change-Number: 29483 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Mon, 26 Aug 2019 18:16:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: util/abuild: Ensure .xcompile exists
by Aaron Durbin (Code Review) 26 Aug '19

26 Aug '19

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29483 ) Change subject: util/abuild: Ensure .xcompile exists ...................................................................... Patch Set 1: > Patch Set 1: > > > Patch Set 1: > > > > Is there a trick that makes it available on the builders? I get this > > when I run `docker-what-jenkins-does`: > > > > /tmp/GmyYXllJ:1: .xcompile: No such file or directory > > make[1]: *** No rule to make target '.xcompile'. Stop. > > > > I don't see it in actual logs on the builders. > > Makefile:145 should ensure that the file is around. What issue are you trying to solve with this commit? I ran into this by removing .xcompile which I decided to do because I updated my compilers. I normally only run abuild and don't do builds from within a checkout (no menuconfig, etc). To work around this problem I had to manually generate .xcompile. Side note: It wasn't clear to me how one is supposed to use XGCCPATH or not. When setting that environment variables there's stricter checks in toolchain.inc. When I just have the cross compiler paths in my $PATH environment variable and regenerate .xcompile then things work well. -- To view, visit https://review.coreboot.org/c/coreboot/+/29483 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib485e7741b7700fa241c192e60900ae5f1d977f5 Gerrit-Change-Number: 29483 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Mon, 26 Aug 2019 18:15:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/fsp_broadwell_de: Add ACPI HPET table
by Andrey Petrov (Code Review) 26 Aug '19

26 Aug '19

Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35027 ) Change subject: soc/intel/fsp_broadwell_de: Add ACPI HPET table ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/35027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idae9a7d3d4233037214d6203996bf44fe5f3a845 Gerrit-Change-Number: 35027 Gerrit-PatchSet: 3 Gerrit-Owner: Johnny Lin Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: David Hendricks <dhendrix.sync(a)gmail.com> Gerrit-Reviewer: Johnny Lin Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Name of user not set #1002539 Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: Łukasz Siudut Gerrit-Comment-Date: Mon, 26 Aug 2019 18:15:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: google/kukui: Enable EC_GOOGLE_CHROMEEC_AP_WATCHDOG_FLAG
by You-Cheng Syu (Code Review) 26 Aug '19

26 Aug '19

You-Cheng Syu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31844 Change subject: google/kukui: Enable EC_GOOGLE_CHROMEEC_AP_WATCHDOG_FLAG ...................................................................... google/kukui: Enable EC_GOOGLE_CHROMEEC_AP_WATCHDOG_FLAG Kukui AP doesn't remember if the last AP reset was due to AP watchdog. We need to enable EC_GOOGLE_CHROMEEC_AP_WATCHDOG_FLAG so that it will query the reset reason from EC during watchdog initialization. Besides, we should set BOOTBLOCK_EN_L before mtk_wdt_init so that we can communicate with EC at the time. BUG=b:109900671,b:118654976 BRANCH=none TEST=1. run 'mosys eventlog clear; stop daisydog; echo > /dev/watchdog' 2. wait for watchdog reset 3. see 'WDT: Last reset was hardware watchdog' in AP console 4. check 'mosys eventlog list | grep watchdog' Change-Id: I053cc7664bbaf0d3fcae26ba9481a0ad700dca90 Signed-off-by: You-Cheng Syu <youcheng(a)google.com> --- M src/mainboard/google/kukui/Kconfig M src/mainboard/google/kukui/early_init.c 2 files changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/31844/1 diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index 9f477e5..4d4feac 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -33,6 +33,7 @@ select FATAL_ASSERTS select SPI_FLASH_INCLUDE_ALL_DRIVERS select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_AP_WATCHDOG_FLAG select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_SPI select MAINBOARD_HAS_SPI_TPM_CR50 if VBOOT diff --git a/src/mainboard/google/kukui/early_init.c b/src/mainboard/google/kukui/early_init.c index a16a335..9495af3 100644 --- a/src/mainboard/google/kukui/early_init.c +++ b/src/mainboard/google/kukui/early_init.c @@ -25,11 +25,11 @@ void mainboard_early_init(void) { - mt8183_early_init(); - /* Turn on real eMMC and allow communication to EC. */ gpio_output(BOOTBLOCK_EN_L, 1); + mt8183_early_init(); + setup_chromeos_gpios(); /* Declare we are in S0 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31844 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I053cc7664bbaf0d3fcae26ba9481a0ad700dca90 Gerrit-Change-Number: 31844 Gerrit-PatchSet: 1 Gerrit-Owner: You-Cheng Syu <youcheng(a)google.com> Gerrit-MessageType: newchange

4 14

Change in coreboot[master]: Revert "{drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLO...
by Angel Pons (Code Review) 26 Aug '19

26 Aug '19

Hello Patrick Rudolph, Huang Jin, Arthur Heymans, York Yang, Frans Hendriks, Lee Leahy, Matt DeVillier, build bot (Jenkins), Hannah Williams, Michał Żygowski, Patrick Georgi, Martin Roth, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/34304 to review the following change. Change subject: Revert "{drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLOCK support" ...................................................................... Revert "{drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLOCK support" This reverts commit 4e0ec592553fd94e14a239eeb05ba9ccb668b814. Reason for revert: Causes boot failures and no fix was ever issued. Revert it before a release gets tagged with a broken platform. Change-Id: I67b68f0d6154249ab2633997f29c0a1699ef0c76 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/drivers/intel/fsp1_1/Makefile.inc R src/drivers/intel/fsp1_1/cache_as_ram.inc M src/drivers/intel/fsp1_1/car.c M src/drivers/intel/fsp1_1/include/fsp/car.h M src/mainboard/google/cyan/Makefile.inc M src/mainboard/google/cyan/com_init.c M src/mainboard/intel/strago/Makefile.inc M src/mainboard/intel/strago/com_init.c M src/soc/intel/braswell/Kconfig M src/soc/intel/braswell/Makefile.inc M src/soc/intel/braswell/bootblock/bootblock.c M src/soc/intel/braswell/include/soc/romstage.h M src/soc/intel/braswell/romstage/Makefile.inc R src/soc/intel/braswell/romstage/pmc.c M src/soc/intel/braswell/romstage/romstage.c 15 files changed, 195 insertions(+), 138 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/34304/1 diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc index 10877b9..93f3b59 100644 --- a/src/drivers/intel/fsp1_1/Makefile.inc +++ b/src/drivers/intel/fsp1_1/Makefile.inc @@ -21,7 +21,6 @@ verstage-$(CONFIG_SEPARATE_VERSTAGE) += verstage.c bootblock-y += bootblock.c -bootblock-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += cache_as_ram.S bootblock-y += fsp_util.c romstage-y += car.c @@ -43,6 +42,8 @@ CPPFLAGS_common += -Isrc/drivers/intel/fsp1_1/include +cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_1/cache_as_ram.inc + postcar-y += stage_cache.c ifneq ($(CONFIG_SKIP_FSP_CAR),y) postcar-y += temp_ram_exit.c diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.inc similarity index 93% rename from src/drivers/intel/fsp1_1/cache_as_ram.S rename to src/drivers/intel/fsp1_1/cache_as_ram.inc index 3460b9d..493dbc8 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.S +++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc @@ -5,7 +5,6 @@ * Copyright (C) 2007-2008 coresystems GmbH * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2018-2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,8 +16,6 @@ * GNU General Public License for more details. */ -#include <cpu/x86/post_code.h> - /* * Replacement for cache_as_ram.inc when using the FSP binary. This code * locates the FSP binary, initializes the cache as RAM and performs the @@ -27,10 +24,8 @@ * performs the final stage of initialization. */ -#define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */ - -.global bootblock_pre_c_entry -bootblock_pre_c_entry: +/* I/O delay between post codes on failure */ +#define LHLT_DELAY 0x50000 /* * Per FSP1.1 specs, following registers are preserved: * EBX, EDI, ESI, EBP, MM0, MM1 @@ -134,9 +129,10 @@ /* Need to align stack to 16 bytes at call instruction. Account for the pushes below. */ andl $0xfffffff0, %esp - subl $8, %esp + subl $4, %esp - /* Push initial timestamp on the stack */ + /* Push BIST and initial timestamp on the stack */ + pushl %ebx /* bist */ movd %mm1, %eax pushl %eax /* tsc[63:32] */ movd %mm0, %eax @@ -145,10 +141,12 @@ before_romstage: post_code(0x2A) - /* Call bootblock_c_entry(uint64_t base_timestamp) */ - call bootblock_c_entry + /* Call bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) + in cpu/intel/car/romstage.c */ + call bootblock_c_entry_bist - /* Never reached */ + movb $0x69, %ah + jmp .Lhlt halt1: /* diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index 67ed099..dd1766403 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -101,6 +101,18 @@ * is still enabled. We can directly access work buffer here. */ struct prog fsp = PROG_INIT(PROG_REFCODE, "fsp.bin"); + if (!CONFIG(C_ENVIRONMENT_BOOTBLOCK)) { + /* Call into pre-console init code then initialize console. */ + car_soc_pre_console_init(); + car_mainboard_pre_console_init(); + console_init(); + + display_mtrrs(); + + car_soc_post_console_init(); + car_mainboard_post_console_init(); + } + if (prog_locate(&fsp)) die_with_post_code(POST_INVALID_CBFS, "Unable to locate fsp.bin"); @@ -113,3 +125,19 @@ cache_as_ram_stage_main(fih); } + +void __weak car_mainboard_pre_console_init(void) +{ +} + +void __weak car_soc_pre_console_init(void) +{ +} + +void __weak car_mainboard_post_console_init(void) +{ +} + +void __weak car_soc_post_console_init(void) +{ +} diff --git a/src/drivers/intel/fsp1_1/include/fsp/car.h b/src/drivers/intel/fsp1_1/include/fsp/car.h index 3d99fa6..8d7a683 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/car.h +++ b/src/drivers/intel/fsp1_1/include/fsp/car.h @@ -24,4 +24,12 @@ * cache_as_ram_stage_main() is the stack pointer to use in RAM after * exiting cache-as-ram mode. */ void cache_as_ram_stage_main(FSP_INFO_HEADER *fih); + +/* Mainboard and SoC initialization prior to console. */ +void car_mainboard_pre_console_init(void); +void car_soc_pre_console_init(void); +/* Mainboard and SoC initialization post console initialization. */ +void car_mainboard_post_console_init(void); +void car_soc_post_console_init(void); + #endif diff --git a/src/mainboard/google/cyan/Makefile.inc b/src/mainboard/google/cyan/Makefile.inc index 027c49c..92b0422 100644 --- a/src/mainboard/google/cyan/Makefile.inc +++ b/src/mainboard/google/cyan/Makefile.inc @@ -14,9 +14,8 @@ ## GNU General Public License for more details. ## -bootblock-$(CONFIG_ENABLE_BUILTIN_COM1) += com_init.c - romstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += com_init.c romstage-y += spd/spd.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c diff --git a/src/mainboard/google/cyan/com_init.c b/src/mainboard/google/cyan/com_init.c index b08dbce..44260bb 100644 --- a/src/mainboard/google/cyan/com_init.c +++ b/src/mainboard/google/cyan/com_init.c @@ -14,14 +14,14 @@ * GNU General Public License for more details. */ -#include <bootblock_common.h> #include <device/mmio.h> #include <device/pci_ops.h> #include <soc/gpio.h> #include <soc/lpc.h> #include <soc/pci_devs.h> +#include <soc/romstage.h> -void bootblock_mainboard_early_init(void) +void car_mainboard_pre_console_init(void) { uint32_t reg; uint32_t *pad_config_reg; diff --git a/src/mainboard/intel/strago/Makefile.inc b/src/mainboard/intel/strago/Makefile.inc index e6f0c9e..bbef8b9 100644 --- a/src/mainboard/intel/strago/Makefile.inc +++ b/src/mainboard/intel/strago/Makefile.inc @@ -14,9 +14,8 @@ ## GNU General Public License for more details. ## -bootblock-$(CONFIG_ENABLE_BUILTIN_COM1) += com_init.c - romstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c +romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += com_init.c ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += ec.c diff --git a/src/mainboard/intel/strago/com_init.c b/src/mainboard/intel/strago/com_init.c index 695ea98..b89d655 100644 --- a/src/mainboard/intel/strago/com_init.c +++ b/src/mainboard/intel/strago/com_init.c @@ -14,12 +14,12 @@ * GNU General Public License for more details. */ -#include <bootblock_common.h> #include <device/mmio.h> #include <device/pci_ops.h> #include <soc/gpio.h> #include <soc/lpc.h> #include <soc/pci_devs.h> +#include <soc/romstage.h> /* * return family number and internal pad number in that community @@ -30,7 +30,7 @@ /* family number in high byte and inner pad number in lowest byte */ -void bootblock_mainboard_early_init(void) +void car_mainboard_pre_console_init(void) { uint32_t reg; uint32_t *pad_config_reg; diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 920179f83..ed5c972 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -51,23 +51,15 @@ select INTEL_GMA_SWSMISCI select CPU_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS - select C_ENVIRONMENT_BOOTBLOCK - -config DCACHE_BSP_STACK_SIZE - hex - default 0x2000 - help - The amount of anticipated stack usage in CAR by bootblock and - other stages. - -config C_ENV_BOOTBLOCK_SIZE - hex - default 0x8000 config VBOOT select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_ROMSTAGE +config BOOTBLOCK_CPU_INIT + string + default "soc/intel/braswell/bootblock/bootblock.c" + config MMCONF_BASE_ADDRESS hex default 0xe0000000 diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index 1017d80..e479a3c 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -9,14 +9,9 @@ subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/intel/common -bootblock-y += gpio_support.c -bootblock-y += bootblock/bootblock.c -bootblock-y += lpc_init.c -bootblock-y += pmutil.c -bootblock-y += tsc_freq.c - romstage-y += gpio_support.c romstage-y += iosf.c +romstage-y += lpc_init.c romstage-y += memmap.c romstage-y += pmutil.c romstage-y += smbus.c diff --git a/src/soc/intel/braswell/bootblock/bootblock.c b/src/soc/intel/braswell/bootblock/bootblock.c index 2d1a3e8..457b8b8 100644 --- a/src/soc/intel/braswell/bootblock/bootblock.c +++ b/src/soc/intel/braswell/bootblock/bootblock.c @@ -3,7 +3,6 @@ * * Copyright (C) 2013 Google, Inc. * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,93 +14,37 @@ * GNU General Public License for more details. */ -#include <bootblock_common.h> -#include <build.h> -#include <console/console.h> #include <device/pci_ops.h> -#include <pc80/mc146818rtc.h> -#include <soc/bootblock.h> -#include <soc/gpio.h> -#include <soc/iomap.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> #include <soc/iosf.h> -#include <soc/lpc.h> -#include <soc/pm.h> -#include <soc/spi.h> +#include <cpu/intel/microcode/microcode.c> -asmlinkage void bootblock_c_entry(uint64_t base_timestamp) +static void set_var_mtrr(int reg, uint32_t base, uint32_t size, int type) { - /* Call lib/bootblock.c main */ - bootblock_main_with_timestamp(base_timestamp, NULL, 0); + msr_t basem, maskm; + basem.lo = base | type; + basem.hi = 0; + wrmsr(MTRR_PHYS_BASE(reg), basem); + maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; + maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; + wrmsr(MTRR_PHYS_MASK(reg), maskm); } -static void program_base_addresses(void) +static void enable_rom_caching(void) { - uint32_t reg; - const uint32_t lpc_dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); + msr_t msr; - /* Memory Mapped IO registers. */ - reg = PMC_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, PBASE, reg); - reg = IO_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, IOBASE, reg); - reg = ILB_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, IBASE, reg); - reg = SPI_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, SBASE, reg); - reg = MPHY_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, MPBASE, reg); - reg = PUNIT_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, PUBASE, reg); - reg = RCBA_BASE_ADDRESS | 1; - pci_write_config32(lpc_dev, RCBA, reg); + disable_cache(); + /* Why only top 4MiB ? */ + set_var_mtrr(1, 0xffc00000, 4*1024*1024, MTRR_TYPE_WRPROT); + enable_cache(); - /* IO Port Registers. */ - reg = ACPI_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, ABASE, reg); - reg = GPIO_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, GBASE, reg); -} - -static void tco_disable(void) -{ - uint32_t reg; - - reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT); - reg |= TCO_TMR_HALT; - outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT); -} - -static void spi_init(void) -{ - void *scs = (void *)(SPI_BASE_ADDRESS + SCS); - void *bcr = (void *)(SPI_BASE_ADDRESS + BCR); - uint32_t reg; - - /* Disable generating SMI when setting WPD bit. */ - write32(scs, read32(scs) & ~SMIWPEN); - /* - * Enable caching and prefetching in the SPI controller. Disable - * the SMM-only BIOS write and set WPD bit. - */ - reg = (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH | BCR_WPD; - reg &= ~EISS; - write32(bcr, reg); -} - -static void soc_rtc_init(void) -{ - int rtc_failed = rtc_failure(); - - if (rtc_failed) { - printk(BIOS_ERR, - "RTC Failure detected. Resetting date to %x/%x/%x%x\n", - COREBOOT_BUILD_MONTH_BCD, - COREBOOT_BUILD_DAY_BCD, - 0x20, - COREBOOT_BUILD_YEAR_BCD); - } - - cmos_init(rtc_failed); + /* Enable Variable MTRRs */ + msr.hi = 0x00000000; + msr.lo = 0x00000800; + wrmsr(MTRR_DEF_TYPE_MSR, msr); } static void setup_mmconfig(void) @@ -124,22 +67,12 @@ pci_io_write_config32(IOSF_PCI_DEV, MCR_REG, reg); } - -void bootblock_soc_early_init(void) +static void bootblock_cpu_init(void) { /* Allow memory-mapped PCI config access. */ setup_mmconfig(); - /* Early chipset initialization */ - program_base_addresses(); - tco_disable(); -} -void bootblock_soc_init(void) -{ - /* Continue chipset initialization */ - soc_rtc_init(); - set_max_freq(); - spi_init(); - - lpc_init(); + /* Load microcode before any caching. */ + intel_update_microcode_from_cbfs(); + enable_rom_caching(); } diff --git a/src/soc/intel/braswell/include/soc/romstage.h b/src/soc/intel/braswell/include/soc/romstage.h index 9fad9bc..4ecbd2c 100644 --- a/src/soc/intel/braswell/include/soc/romstage.h +++ b/src/soc/intel/braswell/include/soc/romstage.h @@ -23,10 +23,12 @@ #include <soc/pm.h> void gfx_init(void); +void tco_disable(void); void punit_init(void); void set_max_freq(void); -/* romstage.c functions */ +/* romstage_common.c functions */ +void program_base_addresses(void); int chipset_prev_sleep_state(struct chipset_power_state *ps); /* Values for FSP's PcdMemoryTypeEnable */ diff --git a/src/soc/intel/braswell/romstage/Makefile.inc b/src/soc/intel/braswell/romstage/Makefile.inc index d405133..3d3e407 100644 --- a/src/soc/intel/braswell/romstage/Makefile.inc +++ b/src/soc/intel/braswell/romstage/Makefile.inc @@ -1,2 +1,3 @@ romstage-y += ../../../../cpu/intel/car/romstage.c +romstage-y += pmc.c romstage-y += romstage.c diff --git a/src/soc/intel/braswell/include/soc/bootblock.h b/src/soc/intel/braswell/romstage/pmc.c similarity index 67% rename from src/soc/intel/braswell/include/soc/bootblock.h rename to src/soc/intel/braswell/romstage/pmc.c index e6e25cc..127458e 100644 --- a/src/soc/intel/braswell/include/soc/bootblock.h +++ b/src/soc/intel/braswell/romstage/pmc.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -14,9 +14,15 @@ * GNU General Public License for more details. */ -#ifndef _SOC_BOOTBLOCK_H_ -#define _SOC_BOOTBLOCK_H_ +#include <arch/io.h> +#include <soc/iomap.h> +#include <soc/romstage.h> -void set_max_freq(void); +void tco_disable(void) +{ + uint32_t reg; -#endif /* _SOC_BOOTBLOCK_H_ */ + reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT); + reg |= TCO_TMR_HALT; + outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT); +} diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index e0e22f2..8dfc291 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -19,13 +19,90 @@ #include <stddef.h> #include <arch/io.h> #include <device/mmio.h> +#include <device/pci_ops.h> +#include <arch/cbfs.h> +#include <cpu/x86/mtrr.h> #include <console/console.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <elog.h> +#include <mrc_cache.h> +#include <string.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <fsp/util.h> +#include <soc/gpio.h> #include <soc/iomap.h> #include <soc/iosf.h> +#include <soc/lpc.h> +#include <soc/pci_devs.h> #include <soc/romstage.h> +#include <soc/smm.h> +#include <soc/spi.h> +#include <build.h> +#include <pc80/mc146818rtc.h> #include "../chip.h" +void program_base_addresses(void) +{ + uint32_t reg; + const uint32_t lpc_dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); + + /* Memory Mapped IO registers. */ + reg = PMC_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, PBASE, reg); + reg = IO_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, IOBASE, reg); + reg = ILB_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, IBASE, reg); + reg = SPI_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, SBASE, reg); + reg = MPHY_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, MPBASE, reg); + reg = PUNIT_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, PUBASE, reg); + reg = RCBA_BASE_ADDRESS | 1; + pci_write_config32(lpc_dev, RCBA, reg); + + /* IO Port Registers. */ + reg = ACPI_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, ABASE, reg); + reg = GPIO_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, GBASE, reg); +} + +static void spi_init(void) +{ + void *scs = (void *)(SPI_BASE_ADDRESS + SCS); + void *bcr = (void *)(SPI_BASE_ADDRESS + BCR); + uint32_t reg; + + /* Disable generating SMI when setting WPD bit. */ + write32(scs, read32(scs) & ~SMIWPEN); + /* + * Enable caching and prefetching in the SPI controller. Disable + * the SMM-only BIOS write and set WPD bit. + */ + reg = (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH | BCR_WPD; + reg &= ~EISS; + write32(bcr, reg); +} + +static void soc_rtc_init(void) +{ + int rtc_failed = rtc_failure(); + + if (rtc_failed) { + printk(BIOS_ERR, + "RTC Failure detected. Resetting date to %x/%x/%x%x\n", + COREBOOT_BUILD_MONTH_BCD, + COREBOOT_BUILD_DAY_BCD, + 0x20, + COREBOOT_BUILD_YEAR_BCD); + } + + cmos_init(rtc_failed); +} static struct chipset_power_state power_state; @@ -94,6 +171,24 @@ return prev_sleep_state; } +/* SOC initialization before the console is enabled */ +void car_soc_pre_console_init(void) +{ + /* Early chipset initialization */ + program_base_addresses(); + tco_disable(); +} + +/* SOC initialization after console is enabled */ +void car_soc_post_console_init(void) +{ + /* Continue chipset initialization */ + soc_rtc_init(); + set_max_freq(); + spi_init(); + + lpc_init(); +} /* SOC initialization after RAM is enabled */ void soc_after_ram_init(struct romstage_params *params) -- To view, visit https://review.coreboot.org/c/coreboot/+/34304 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67b68f0d6154249ab2633997f29c0a1699ef0c76 Gerrit-Change-Number: 34304 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: AUTHORS: Move src/arch/ppc64 copyrights into AUTHORS file
by Werner Zeh (Code Review) 26 Aug '19

26 Aug '19

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34637 ) Change subject: AUTHORS: Move src/arch/ppc64 copyrights into AUTHORS file ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/34637 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51d5b1f01ff47ed752761116e3f32cb9e168584f Gerrit-Change-Number: 34637 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Mon, 26 Aug 2019 14:05:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: AUTHORS: Move src/arch/ppc64 copyrights into AUTHORS file
by Patrick Georgi (Code Review) 26 Aug '19

26 Aug '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34637 ) Change subject: AUTHORS: Move src/arch/ppc64 copyrights into AUTHORS file ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/34637 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51d5b1f01ff47ed752761116e3f32cb9e168584f Gerrit-Change-Number: 34637 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Mon, 26 Aug 2019 13:57:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: AUTHORS: Move src/arch/arm copyrights into AUTHORS file
by Martin Roth (Code Review) 26 Aug '19

26 Aug '19

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34605 ) Change subject: AUTHORS: Move src/arch/arm copyrights into AUTHORS file ...................................................................... AUTHORS: Move src/arch/arm copyrights into AUTHORS file As discussed on the mailing list and voted upon, the coreboot project is going to move the majority of copyrights out of the headers and into an AUTHORS file. This will happen a bit at a time, as we'll be unifying license headers at the same time. Additional changes in this patch: - Make sure files say that they're part of the coreboot project - Move descriptions below the license header - Fix some spacing Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: Id5f26a73f0df366651c076a94975bce1fb321b70 --- M AUTHORS M src/arch/arm/Makefile.inc M src/arch/arm/armv4/Makefile.inc M src/arch/arm/armv4/bootblock.S M src/arch/arm/armv7/Makefile.inc M src/arch/arm/armv7/bootblock.S M src/arch/arm/armv7/cpu.S M src/arch/arm/armv7/exception.c M src/arch/arm/armv7/exception_asm.S M src/arch/arm/armv7/exception_mr.c M src/arch/arm/armv7/thread.c M src/arch/arm/asmlib.h M src/arch/arm/boot.c M src/arch/arm/div0.c M src/arch/arm/eabi_compat.c M src/arch/arm/include/arch/asm.h M src/arch/arm/include/arch/cbconfig.h M src/arch/arm/include/arch/clock.h M src/arch/arm/include/arch/early_variables.h M src/arch/arm/include/arch/header.ld M src/arch/arm/include/arch/memlayout.h M src/arch/arm/include/arch/pci_ops.h M src/arch/arm/include/arch/stages.h M src/arch/arm/include/armv4/arch/cpu.h M src/arch/arm/include/armv4/arch/mmio.h M src/arch/arm/include/armv7.h M src/arch/arm/include/armv7/arch/cpu.h M src/arch/arm/include/armv7/arch/exception.h M src/arch/arm/include/armv7/arch/mmio.h M src/arch/arm/include/clocks.h M src/arch/arm/libgcc/Makefile.inc M src/arch/arm/libgcc/ashldi3.S M src/arch/arm/libgcc/lib1funcs.S M src/arch/arm/libgcc/lshrdi3.S M src/arch/arm/libgcc/muldi3.S M src/arch/arm/libgcc/ucmpdi2.S M src/arch/arm/libgcc/uldivmod.S M src/arch/arm/memcpy.S M src/arch/arm/memmove.S M src/arch/arm/memset.S M src/arch/arm/stages.c M src/arch/arm/tables.c 42 files changed, 97 insertions(+), 166 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/34605/1 diff --git a/AUTHORS b/AUTHORS index c5fec18..ab4f082 100644 --- a/AUTHORS +++ b/AUTHORS @@ -7,8 +7,30 @@ # Alexander Couzens +Alexandru Gagniuc +Alex Züpke +coresystems GmbH +DENX Software Engineering +Eric Biederman +Free Software Foundation, Inc. +Gary Jennejohn +Google Inc. +Kshitij +Marius Gröger +MontaVista Software, Inc. +Per Odlund +Richard Woodruff +Ronald G. Minnich +Russell King +Steve Magnani +Syed Mohammed Khasim +Texas Instruments +The Chromium OS Authors +The Linux Foundation +Wolfgang Denk # Directories transferred src/acpi +src/arch/arm diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc index 06adfe4..508b0a8 100644 --- a/src/arch/arm/Makefile.inc +++ b/src/arch/arm/Makefile.inc @@ -2,11 +2,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2012-2013 The ChromiumOS Authors -## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> -## Copyright (C) 2009-2010 coresystems GmbH -## Copyright (C) 2009 Ronald G. Minnich -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm/armv4/Makefile.inc b/src/arch/arm/armv4/Makefile.inc index e8e49a6..2cc5ebb 100644 --- a/src/arch/arm/armv4/Makefile.inc +++ b/src/arch/arm/armv4/Makefile.inc @@ -2,8 +2,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 The ChromiumOS Authors -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm/armv4/bootblock.S b/src/arch/arm/armv4/bootblock.S index 0391ebf..cf37647 100644 --- a/src/arch/arm/armv4/bootblock.S +++ b/src/arch/arm/armv4/bootblock.S @@ -1,17 +1,5 @@ /* - * Early initialization code for ARM architecture. - * - * This file is based off of the OMAP3530/ARM Cortex start.S file from Das - * U-Boot, which itself got the file from armboot. - * - * Copyright (c) 2004 Texas Instruments <r-woodruff2(a)ti.com> - * Copyright (c) 2001 Marius Gröger <mag(a)sysgo.de> - * Copyright (c) 2002 Alex Züpke <azu(a)sysgo.de> - * Copyright (c) 2002 Gary Jennejohn <garyj(a)denx.de> - * Copyright (c) 2003 Richard Woodruff <r-woodruff2(a)ti.com> - * Copyright (c) 2003 Kshitij <kshitij(a)ti.com> - * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim(a)ti.com> - * Copyright (c) 2013 The Chromium OS Authors + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -22,6 +10,11 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. + * + * Early initialization code for ARM architecture. + * + * This file is based off of the OMAP3530/ARM Cortex start.S file from Das + * U-Boot, which itself got the file from armboot. */ #include <arch/asm.h> diff --git a/src/arch/arm/armv7/Makefile.inc b/src/arch/arm/armv7/Makefile.inc index 1d3ae52..58592a0 100644 --- a/src/arch/arm/armv7/Makefile.inc +++ b/src/arch/arm/armv7/Makefile.inc @@ -2,8 +2,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 The ChromiumOS Authors -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm/armv7/bootblock.S b/src/arch/arm/armv7/bootblock.S index e2d76a14..da2671c 100644 --- a/src/arch/arm/armv7/bootblock.S +++ b/src/arch/arm/armv7/bootblock.S @@ -1,17 +1,5 @@ /* - * Early initialization code for ARMv7 architecture. - * - * This file is based off of the OMAP3530/ARM Cortex start.S file from Das - * U-Boot, which itself got the file from armboot. - * - * Copyright (c) 2004 Texas Instruments <r-woodruff2(a)ti.com> - * Copyright (c) 2001 Marius Gröger <mag(a)sysgo.de> - * Copyright (c) 2002 Alex Züpke <azu(a)sysgo.de> - * Copyright (c) 2002 Gary Jennejohn <garyj(a)denx.de> - * Copyright (c) 2003 Richard Woodruff <r-woodruff2(a)ti.com> - * Copyright (c) 2003 Kshitij <kshitij(a)ti.com> - * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim(a)ti.com> - * Copyright (c) 2013 The Chromium OS Authors + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -22,6 +10,11 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. + * + * Early initialization code for ARMv7 architecture. + * + * This file is based off of the OMAP3530/ARM Cortex start.S file from Das + * U-Boot, which itself got the file from armboot. */ #include <arch/asm.h> diff --git a/src/arch/arm/armv7/cpu.S b/src/arch/arm/armv7/cpu.S index 1f6cd5b..3f90c0b 100644 --- a/src/arch/arm/armv7/cpu.S +++ b/src/arch/arm/armv7/cpu.S @@ -1,7 +1,5 @@ /* - * Optimized assembly for low-level CPU operations on ARMv7 processors. - * - * Cache flushing code based off sys/arch/arm/arm/cpufunc_asm_armv7.S in NetBSD + * This file is part of the coreboot project. * * Copyright (c) 2010 Per Odlund <per.odlund(a)armagedon.se> * Copyright (c) 2014 Google Inc. @@ -28,6 +26,10 @@ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. + * + * Optimized assembly for low-level CPU operations on ARMv7 processors. + * + * Cache flushing code based off sys/arch/arm/arm/cpufunc_asm_armv7.S in NetBSD */ #include <arch/asm.h> diff --git a/src/arch/arm/armv7/exception.c b/src/arch/arm/armv7/exception.c index 4fac0bc..d6891b0 100644 --- a/src/arch/arm/armv7/exception.c +++ b/src/arch/arm/armv7/exception.c @@ -1,5 +1,5 @@ /* - * This file is part of the libpayload project. + * This file is part of the coreboot project. * * Copyright 2013 Google Inc. * diff --git a/src/arch/arm/armv7/exception_asm.S b/src/arch/arm/armv7/exception_asm.S index f54cd85..6aa4188 100644 --- a/src/arch/arm/armv7/exception_asm.S +++ b/src/arch/arm/armv7/exception_asm.S @@ -1,5 +1,5 @@ /* - * This file is part of the libpayload project. + * This file is part of the coreboot project. * * Copyright 2013 Google Inc. * diff --git a/src/arch/arm/armv7/exception_mr.c b/src/arch/arm/armv7/exception_mr.c index d76cc6a..01e834e 100644 --- a/src/arch/arm/armv7/exception_mr.c +++ b/src/arch/arm/armv7/exception_mr.c @@ -1,5 +1,5 @@ /* - * This file is part of the libpayload project. + * This file is part of the coreboot project. * * Copyright 2013 Google Inc. * diff --git a/src/arch/arm/armv7/thread.c b/src/arch/arm/armv7/thread.c index bcf6923..4e82be7 100644 --- a/src/arch/arm/armv7/thread.c +++ b/src/arch/arm/armv7/thread.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm/asmlib.h b/src/arch/arm/asmlib.h index 0d51551..cae4081 100644 --- a/src/arch/arm/asmlib.h +++ b/src/arch/arm/asmlib.h @@ -1,9 +1,5 @@ /* - * arch/arm/asmlib.h - * - * Adapted from Linux arch/arm/include/assembler.h - * - * Copyright (C) 1996-2000 Russell King + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -17,6 +13,8 @@ * This file contains arm architecture specific defines * for the different processors. * + * Adapted from Linux arch/arm/include/assembler.h + * * Do not include any C declarations in this file - it is included by * assembler source. */ diff --git a/src/arch/arm/boot.c b/src/arch/arm/boot.c index 1767fe0..9d1e4cd 100644 --- a/src/arch/arm/boot.c +++ b/src/arch/arm/boot.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm/div0.c b/src/arch/arm/div0.c index e474f73..fa3bf7f 100644 --- a/src/arch/arm/div0.c +++ b/src/arch/arm/div0.c @@ -1,6 +1,5 @@ /* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/arch/arm/eabi_compat.c b/src/arch/arm/eabi_compat.c index 15f7d36..45f4651 100644 --- a/src/arch/arm/eabi_compat.c +++ b/src/arch/arm/eabi_compat.c @@ -1,7 +1,5 @@ /* - * Utility functions needed for (some) EABI conformant tool chains. - * - * (C) Copyright 2009 Wolfgang Denk <wd(a)denx.de> + * This file is part of the coreboot project. * * This program is Free Software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -12,6 +10,8 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. + * + * Utility functions needed for (some) EABI conformant tool chains. */ #include <stdint.h> diff --git a/src/arch/arm/include/arch/asm.h b/src/arch/arm/include/arch/asm.h index b148d12..b9591b6 100644 --- a/src/arch/arm/include/arch/asm.h +++ b/src/arch/arm/include/arch/asm.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm/include/arch/cbconfig.h b/src/arch/arm/include/arch/cbconfig.h index 9467f52..35c1387 100644 --- a/src/arch/arm/include/arch/cbconfig.h +++ b/src/arch/arm/include/arch/cbconfig.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm/include/arch/clock.h b/src/arch/arm/include/arch/clock.h index 77d09d8..248da06 100644 --- a/src/arch/arm/include/arch/clock.h +++ b/src/arch/arm/include/arch/clock.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm/include/arch/early_variables.h b/src/arch/arm/include/arch/early_variables.h index c469446..9f06923 100644 --- a/src/arch/arm/include/arch/early_variables.h +++ b/src/arch/arm/include/arch/early_variables.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm/include/arch/header.ld b/src/arch/arm/include/arch/header.ld index 8947310..5d93673 100644 --- a/src/arch/arm/include/arch/header.ld +++ b/src/arch/arm/include/arch/header.ld @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm/include/arch/memlayout.h b/src/arch/arm/include/arch/memlayout.h index 4ba2bf8..26b8ef4 100644 --- a/src/arch/arm/include/arch/memlayout.h +++ b/src/arch/arm/include/arch/memlayout.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm/include/arch/pci_ops.h b/src/arch/arm/include/arch/pci_ops.h index 75bb20e..4cb05e7 100644 --- a/src/arch/arm/include/arch/pci_ops.h +++ b/src/arch/arm/include/arch/pci_ops.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm/include/arch/stages.h b/src/arch/arm/include/arch/stages.h index 68a3bd1..3841265 100644 --- a/src/arch/arm/include/arch/stages.h +++ b/src/arch/arm/include/arch/stages.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 The ChromiumOS Authors - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm/include/armv4/arch/cpu.h b/src/arch/arm/include/armv4/arch/cpu.h index d32bf58..3a27743 100644 --- a/src/arch/arm/include/armv4/arch/cpu.h +++ b/src/arch/arm/include/armv4/arch/cpu.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2012 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm/include/armv4/arch/mmio.h b/src/arch/arm/include/armv4/arch/mmio.h index ad89ef5..2c43789 100644 --- a/src/arch/arm/include/armv4/arch/mmio.h +++ b/src/arch/arm/include/armv4/arch/mmio.h @@ -1,9 +1,5 @@ /* - * Originally imported from linux/include/asm-arm/io.h. This file has changed - * substantially since then. - * - * Copyright 2013 Google Inc. - * Copyright (C) 1996-2000 Russell King + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -14,16 +10,8 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * Modifications: - * 08-Apr-2013 G Replaced several macros with inlines for type safety. - * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both - * constant addresses and variable addresses. - * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture - * specific IO header files. - * 27-Mar-1999 PJB Second parameter of memcpy_toio is const.. - * 04-Apr-1999 PJB Added check_signature. - * 12-Dec-1999 RMK More cleanups - * 18-Jun-2000 RMK Removed virt_to_* and friends definitions + * Originally imported from linux/include/asm-arm/io.h. This file has changed + * substantially since then. */ #ifndef __ARCH_MMIO_H__ diff --git a/src/arch/arm/include/armv7.h b/src/arch/arm/include/armv7.h index bec7fd7..626e608 100644 --- a/src/arch/arm/include/armv7.h +++ b/src/arch/arm/include/armv7.h @@ -1,7 +1,5 @@ /* - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - * Aneesh V <aneesh(a)ti.com> + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/arch/arm/include/armv7/arch/cpu.h b/src/arch/arm/include/armv7/arch/cpu.h index 22b3fb4..ccf2f92 100644 --- a/src/arch/arm/include/armv7/arch/cpu.h +++ b/src/arch/arm/include/armv7/arch/cpu.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2012 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm/include/armv7/arch/exception.h b/src/arch/arm/include/armv7/arch/exception.h index 57076bd..df39309 100644 --- a/src/arch/arm/include/armv7/arch/exception.h +++ b/src/arch/arm/include/armv7/arch/exception.h @@ -1,5 +1,5 @@ /* - * This file is part of the libpayload project. + * This file is part of the coreboot project. * * Copyright 2013 Google Inc. * diff --git a/src/arch/arm/include/armv7/arch/mmio.h b/src/arch/arm/include/armv7/arch/mmio.h index b245b26..87f6871 100644 --- a/src/arch/arm/include/armv7/arch/mmio.h +++ b/src/arch/arm/include/armv7/arch/mmio.h @@ -1,9 +1,5 @@ /* - * Originally imported from linux/include/asm-arm/io.h. This file has changed - * substantially since then. - * - * Copyright 2013 Google Inc. - * Copyright (C) 1996-2000 Russell King + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -14,16 +10,8 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * Modifications: - * 08-Apr-2013 G Replaced several macros with inlines for type safety. - * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both - * constant addresses and variable addresses. - * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture - * specific IO header files. - * 27-Mar-1999 PJB Second parameter of memcpy_toio is const.. - * 04-Apr-1999 PJB Added check_signature. - * 12-Dec-1999 RMK More cleanups - * 18-Jun-2000 RMK Removed virt_to_* and friends definitions + * Originally imported from linux/include/asm-arm/io.h. This file has changed + * substantially since then. */ #ifndef __ARCH_MMIO_H__ diff --git a/src/arch/arm/include/clocks.h b/src/arch/arm/include/clocks.h index 60afb44..4904b6e 100644 --- a/src/arch/arm/include/clocks.h +++ b/src/arch/arm/include/clocks.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011 The Chromium OS Authors. + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/arch/arm/libgcc/Makefile.inc b/src/arch/arm/libgcc/Makefile.inc index 9a8d4fc..2d0f6a8 100644 --- a/src/arch/arm/libgcc/Makefile.inc +++ b/src/arch/arm/libgcc/Makefile.inc @@ -2,8 +2,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 The ChromiumOS Authors -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm/libgcc/ashldi3.S b/src/arch/arm/libgcc/ashldi3.S index 1e3aefa..473e15f 100644 --- a/src/arch/arm/libgcc/ashldi3.S +++ b/src/arch/arm/libgcc/ashldi3.S @@ -1,5 +1,5 @@ -/* Copyright 1995, 1996, 1998, 1999, 2000, 2003, 2004, 2005 - Free Software Foundation, Inc. +/* +This file is part of the coreboot project. This file is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the diff --git a/src/arch/arm/libgcc/lib1funcs.S b/src/arch/arm/libgcc/lib1funcs.S index a642185..5c2a6ad 100644 --- a/src/arch/arm/libgcc/lib1funcs.S +++ b/src/arch/arm/libgcc/lib1funcs.S @@ -1,12 +1,5 @@ /* - * linux/arch/arm/lib/lib1funcs.S: Optimized ARM division routines - * - * Author: Nicolas Pitre <nico(a)fluxnic.net> - * - contributed to gcc-3.4 on Sep 30, 2003 - * - adapted for the Linux kernel on Oct 2, 2003 - */ - -/* Copyright 1995, 1996, 1998, 1999, 2000, 2003 Free Software Foundation, Inc. +This file is part of the coreboot project. This file is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the @@ -28,6 +21,10 @@ General Public License for more details. */ +/* + * linux/arch/arm/lib/lib1funcs.S: Optimized ARM division routines + */ + #if defined __GNUC__ diff --git a/src/arch/arm/libgcc/lshrdi3.S b/src/arch/arm/libgcc/lshrdi3.S index 119ec45..5e67690 100644 --- a/src/arch/arm/libgcc/lshrdi3.S +++ b/src/arch/arm/libgcc/lshrdi3.S @@ -1,5 +1,5 @@ -/* Copyright 1995, 1996, 1998, 1999, 2000, 2003, 2004, 2005 - Free Software Foundation, Inc. +/* +This file is part of the coreboot project. This file is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the diff --git a/src/arch/arm/libgcc/muldi3.S b/src/arch/arm/libgcc/muldi3.S index 1d783ec..c758474 100644 --- a/src/arch/arm/libgcc/muldi3.S +++ b/src/arch/arm/libgcc/muldi3.S @@ -1,18 +1,16 @@ /* - * linux/arch/arm/lib/muldi3.S + * This file is part of the coreboot project. * - * Author: Nicolas Pitre - * Created: Oct 19, 2005 - * Copyright: Monta Vista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. + * + * Based on linux/arch/arm/lib/muldi3.S */ #if defined __GNUC__ diff --git a/src/arch/arm/libgcc/ucmpdi2.S b/src/arch/arm/libgcc/ucmpdi2.S index 8b21043..771e93b 100644 --- a/src/arch/arm/libgcc/ucmpdi2.S +++ b/src/arch/arm/libgcc/ucmpdi2.S @@ -1,18 +1,16 @@ /* - * linux/arch/arm/lib/ucmpdi2.S + * This file is part of the coreboot project. * - * Author: Nicolas Pitre - * Created: Oct 19, 2005 - * Copyright: Monta Vista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. + * + * Based on linux/arch/arm/lib/ucmpdi2.S */ #if defined __GNUC__ diff --git a/src/arch/arm/libgcc/uldivmod.S b/src/arch/arm/libgcc/uldivmod.S index 521a5d1..ecbeccf 100644 --- a/src/arch/arm/libgcc/uldivmod.S +++ b/src/arch/arm/libgcc/uldivmod.S @@ -1,4 +1,6 @@ /* + * This file is part of the coreboot project. + * * Copyright 2010, Google Inc. * All rights reserved. * diff --git a/src/arch/arm/memcpy.S b/src/arch/arm/memcpy.S index fe4f400..19592db 100644 --- a/src/arch/arm/memcpy.S +++ b/src/arch/arm/memcpy.S @@ -1,18 +1,16 @@ /* - * linux/arch/arm/lib/memcpy.S + * This file is part of the coreboot project. * - * Author: Nicolas Pitre - * Created: Sep 28, 2005 - * Copyright: MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. + * + * Based on linux/arch/arm/lib/memcpy.S */ #include <arch/asm.h> diff --git a/src/arch/arm/memmove.S b/src/arch/arm/memmove.S index f4da9e8..3b5681c 100644 --- a/src/arch/arm/memmove.S +++ b/src/arch/arm/memmove.S @@ -1,18 +1,16 @@ /* - * linux/arch/arm/lib/memmove.S + * This file is part of the coreboot project. * - * Author: Nicolas Pitre - * Created: Sep 28, 2005 - * Copyright: (C) MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. + * + * Based on linux/arch/arm/lib/memmove.S */ #include <arch/asm.h> diff --git a/src/arch/arm/memset.S b/src/arch/arm/memset.S index 9a3bc72..7d71a88 100644 --- a/src/arch/arm/memset.S +++ b/src/arch/arm/memset.S @@ -1,7 +1,5 @@ /* - * linux/arch/arm/lib/memset.S - * - * Copyright (C) 1995-2000 Russell King + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -12,7 +10,9 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * ASM optimised string functions + * Based on linux/arch/arm/lib/memset.S + * + * ASM optimised string functions */ #include <arch/asm.h> diff --git a/src/arch/arm/stages.c b/src/arch/arm/stages.c index 22ade63..c9f5744 100644 --- a/src/arch/arm/stages.c +++ b/src/arch/arm/stages.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2012 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/arch/arm/tables.c b/src/arch/arm/tables.c index 682715f..ab2b579 100644 --- a/src/arch/arm/tables.c +++ b/src/arch/arm/tables.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2003 Eric Biederman - * Copyright (C) 2005 Steve Magnani - * Copyright (C) 2008-2009 coresystems GmbH - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. -- To view, visit https://review.coreboot.org/c/coreboot/+/34605 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5f26a73f0df366651c076a94975bce1fb321b70 Gerrit-Change-Number: 34605 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit August 2019