coreboot-gerrit August 2019

coreboot-gerrit@coreboot.org

1 participants
1942 discussions

Change in coreboot[master]: mediatek/mt8183: postpone dcxo low power mode setting
by Weiyi Lu (Code Review) 04 Sep '19

04 Sep '19

Hello Weiyi Lu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/34777 to review the following change. Change subject: mediatek/mt8183: postpone dcxo low power mode setting ...................................................................... mediatek/mt8183: postpone dcxo low power mode setting Consider the association between MD and DCXO, this patch is a fix for eb5e47d("mediatek/mt8183: update dcxo output buffer setting") [1] We should not disable XO_CEL and block the bblpm request when MD is still ON. [1] https://review.coreboot.org/c/coreboot/+/32323 BRANCH=none TEST=Boots correctly on Krane. Change-Id: I047ebed615e874977ca211aafd52b5551c71b764 Signed-off-by: Weiyi Lu <weiyi.lu(a)mediatek.com> --- M src/soc/mediatek/mt8183/include/soc/rtc.h M src/soc/mediatek/mt8183/rtc.c M src/soc/mediatek/mt8183/soc.c 3 files changed, 14 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/34777/1 diff --git a/src/soc/mediatek/mt8183/include/soc/rtc.h b/src/soc/mediatek/mt8183/include/soc/rtc.h index 5a61208..aa4cc43 100644 --- a/src/soc/mediatek/mt8183/include/soc/rtc.h +++ b/src/soc/mediatek/mt8183/include/soc/rtc.h @@ -147,6 +147,7 @@ /* PMIC DCXO Register Definition */ enum { PMIC_RG_DCXO_CW00 = 0x0788, + PMIC_RG_DCXO_CW00_CLR = 0x078C, PMIC_RG_DCXO_CW02 = 0x0790, PMIC_RG_DCXO_CW07 = 0x079A, PMIC_RG_DCXO_CW09 = 0x079E, @@ -218,5 +219,6 @@ void rtc_osc_init(void); int rtc_init(u8 recover); void rtc_boot(void); +void dcxo_disable_unused(void); #endif /* SOC_MEDIATEK_MT8183_RTC_H */ diff --git a/src/soc/mediatek/mt8183/rtc.c b/src/soc/mediatek/mt8183/rtc.c index af30d1f..464fff3 100644 --- a/src/soc/mediatek/mt8183/rtc.c +++ b/src/soc/mediatek/mt8183/rtc.c @@ -411,10 +411,9 @@ rtc_write(PMIC_RG_DCXO_CW16, 0x9855); /* 26M enable control */ - /* Enable clock buffer XO_SOC */ - rtc_write(PMIC_RG_DCXO_CW00, 0x4005); + /* Enable clock buffer XO_SOC, XO_CEL */ + rtc_write(PMIC_RG_DCXO_CW00, 0x4805); rtc_write(PMIC_RG_DCXO_CW11, 0x8000); - rtc_write(PMIC_RG_DCXO_CW23, 0x0053); /* Load thermal coefficient */ rtc_write(PMIC_RG_TOP_TMA_KEY, 0x9CA7); @@ -432,6 +431,14 @@ mdelay(5); } +void dcxo_disable_unused(void) +{ + /* Disable clock buffer XO_CEL */ + rtc_write(PMIC_RG_DCXO_CW00_CLR, 0x0800); + /* Mask bblpm */ + rtc_write(PMIC_RG_DCXO_CW23, 0x0053); +} + /* the rtc boot flow entry */ void rtc_boot(void) { diff --git a/src/soc/mediatek/mt8183/soc.c b/src/soc/mediatek/mt8183/soc.c index c9c2147..f190480 100644 --- a/src/soc/mediatek/mt8183/soc.c +++ b/src/soc/mediatek/mt8183/soc.c @@ -17,6 +17,7 @@ #include <soc/emi.h> #include <soc/md_ctrl.h> #include <soc/mmu_operations.h> +#include <soc/rtc.h> #include <soc/sspm.h> #include <symbols.h> @@ -29,6 +30,7 @@ { mtk_mmu_disable_l2c_sram(); mtk_md_early_init(); + dcxo_disable_unused(); sspm_init(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/34777 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I047ebed615e874977ca211aafd52b5551c71b764 Gerrit-Change-Number: 34777 Gerrit-PatchSet: 1 Gerrit-Owner: Weiyi Lu <weiyi.lu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Weiyi Lu <weiyi.lu(a)mediatek.com> Gerrit-MessageType: newchange

5 10

Change in coreboot[master]: inteltool: add Lewisburg C62x chipset family PCI IDs
by Maxim Polyakov (Code Review) 04 Sep '19

04 Sep '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34941 ) Change subject: inteltool: add Lewisburg C62x chipset family PCI IDs ...................................................................... inteltool: add Lewisburg C62x chipset family PCI IDs These changes are in accordance with the documentation: [*] page 39, Intel(R) C620 Series Chipset Platform Controller Hub (PCH) Datasheet, Document Number: 336067-007US, May 2019 https://www3.intel.com/content/dam/www/public/us/en/documents/ datasheets/c620-series-chipset-datasheet.pdf Change-Id: I7a1ae0cc4c5d4b02599dfafd30f4a87b3ce74b74 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M util/inteltool/inteltool.c M util/inteltool/inteltool.h 2 files changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/34941/1 diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 76b1abe..15ad815 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -260,6 +260,13 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM175, "HM175" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QM175, "QM175" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CM238, "CM238" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_C621, "Lewisburg C621" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_C622, "Lewisburg C622" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_C624, "Lewisburg C624" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_C625, "Lewisburg C625" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_C626, "Lewisburg C626" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_C627, "Lewisburg C627" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_C628, "Lewisburg C628" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H310, "H310" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H370, "H370" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z390, "Z390" }, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 483c930..a0108ee 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -170,6 +170,14 @@ #define PCI_DEVICE_ID_INTEL_QM175 0xa153 #define PCI_DEVICE_ID_INTEL_CM238 0xa154 +#define PCI_DEVICE_ID_INTEL_LEWISBURG_C621 0xa1c1 +#define PCI_DEVICE_ID_INTEL_LEWISBURG_C622 0xa1c2 +#define PCI_DEVICE_ID_INTEL_LEWISBURG_C624 0xa1c3 +#define PCI_DEVICE_ID_INTEL_LEWISBURG_C625 0xa1c4 +#define PCI_DEVICE_ID_INTEL_LEWISBURG_C626 0xa1c5 +#define PCI_DEVICE_ID_INTEL_LEWISBURG_C627 0xa1c6 +#define PCI_DEVICE_ID_INTEL_LEWISBURG_C628 0xa1c7 + #define PCI_DEVICE_ID_INTEL_H310 0xa303 #define PCI_DEVICE_ID_INTEL_H370 0xa304 #define PCI_DEVICE_ID_INTEL_Z390 0xa305 -- To view, visit https://review.coreboot.org/c/coreboot/+/34941 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a1ae0cc4c5d4b02599dfafd30f4a87b3ce74b74 Gerrit-Change-Number: 34941 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

4 20

Change in ...coreboot[master]: security/tpm/tss/tcg-2.0: Use tlcl_get_hash_size_from_algo() for has...
by Frans Hendriks (Code Review) 04 Sep '19

04 Sep '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33251 Change subject: security/tpm/tss/tcg-2.0: Use tlcl_get_hash_size_from_algo() for hash size ...................................................................... security/tpm/tss/tcg-2.0: Use tlcl_get_hash_size_from_algo() for hash size mashal_TPMT_HA() uses size of SHA-256 hash. Use tlcll_get_hash_size_from_algo(0) to determince the hash size. BUG=N/A TEST=Build binary and verified logging on Facebook FBG-1701 Change-Id: I739260e13e9cd10a61d52e13e8741b12ec868d7f Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/security/tpm/tss.h M src/security/tpm/tss/tcg-2.0/tss.c M src/security/tpm/tss/tcg-2.0/tss_marshaling.c M src/security/tpm/tss/tcg-2.0/tss_structures.h 4 files changed, 52 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/33251/1 diff --git a/src/security/tpm/tss.h b/src/security/tpm/tss.h index 548a39a..2ff9eed 100644 --- a/src/security/tpm/tss.h +++ b/src/security/tpm/tss.h @@ -70,6 +70,14 @@ * custom tpm standards like cr50 */ void *tpm_process_command(TPM_CC command, void *command_body); +/* + * Return size of digest. + * + * @param[in] HashAlgo Hash algorithm + * + * @return size of digest + */ +uint16_t tlcl_get_hash_size_from_algo(TPMI_ALG_HASH hashAlgo); #endif diff --git a/src/security/tpm/tss/tcg-2.0/tss.c b/src/security/tpm/tss/tcg-2.0/tss.c index e579bff..24d7726 100644 --- a/src/security/tpm/tss/tcg-2.0/tss.c +++ b/src/security/tpm/tss/tcg-2.0/tss.c @@ -361,3 +361,33 @@ return TPM_SUCCESS; } +/** + Return size of digest. + + @param[in] HashAlgo Hash algorithm + + @return size of digest +**/ + +uint16_t tlcl_get_hash_size_from_algo(TPMI_ALG_HASH hashAlgo) +{ + uint16_t value; + + switch (hashAlgo) { + case TPM_ALG_ERROR: + value = 1; + break; + case TPM_ALG_SHA1: + value = SHA1_DIGEST_SIZE; + break; + case TPM_ALG_SHA256: + value = SHA256_DIGEST_SIZE; + break; + default: + printk(BIOS_SPEW, "%s: unknown hash algorithm %d\n", __func__, + hashAlgo); + value = 0; + }; + + return value; +} diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c index 21da73a..a74eb09 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c +++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c @@ -12,6 +12,7 @@ #include "tss_marshaling.h" #include <security/tpm/tss/vendor/cr50/cr50.h> +#include <security/tpm/tss.h> static uint16_t tpm_tag CAR_GLOBAL; /* Depends on the command type. */ @@ -82,7 +83,7 @@ rc |= marshal_TPMI_ALG_HASH(ob, tpmtha->hashAlg); rc |= obuf_write(ob, tpmtha->digest.sha256, - sizeof(tpmtha->digest.sha256)); + tlcl_get_hash_size_from_algo(tpmtha->hashAlg)); return rc; } diff --git a/src/security/tpm/tss/tcg-2.0/tss_structures.h b/src/security/tpm/tss/tcg-2.0/tss_structures.h index 991cbcf..dcd4468 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_structures.h +++ b/src/security/tpm/tss/tcg-2.0/tss_structures.h @@ -36,12 +36,24 @@ typedef TPM_HANDLE TPM_RH; /* Some hardcoded algorithm values. */ +/* Table 7 - TPM_ALG_ID Constants */ +#define TPM_ALG_ERROR ((TPM_ALG_ID)0x0000) #define TPM_ALG_HMAC ((TPM_ALG_ID)0x0005) #define TPM_ALG_NULL ((TPM_ALG_ID)0x0010) #define TPM_ALG_SHA1 ((TPM_ALG_ID)0x0004) #define TPM_ALG_SHA256 ((TPM_ALG_ID)0x000b) +#define TPM_ALG_SHA384 ((TPM_ALG_ID)0x000C) +#define TPM_ALG_SHA512 ((TPM_ALG_ID)0x000D) +#define TPM_ALG_SM3_256 ((TPM_ALG_ID)0x0012) +/* Annex A Algorithm Constants */ + +/* Table 205 - Defines for SHA1 Hash Values */ +#define SHA1_DIGEST_SIZE 20 +/* Table 206 - Defines for SHA256 Hash Values */ #define SHA256_DIGEST_SIZE 32 +/* Table 208 - Defines for SHA512 Hash Values */ +#define SHA512_DIGEST_SIZE 64 /* Some hardcoded hierarchies. */ #define TPM_RH_NULL 0x40000007 -- To view, visit https://review.coreboot.org/c/coreboot/+/33251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I739260e13e9cd10a61d52e13e8741b12ec868d7f Gerrit-Change-Number: 33251 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

4 11

Change in coreboot[master]: [UNTESTED] skylake: do not rely on P2SB data to generate DRHD
by Angel Pons (Code Review) 03 Sep '19

03 Sep '19

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35108 ) Change subject: [UNTESTED] skylake: do not rely on P2SB data to generate DRHD ...................................................................... [UNTESTED] skylake: do not rely on P2SB data to generate DRHD The P2SB PCI device can be "hidden", which causes all sorts of nightmares and bugs. Moreover, FSP tends to hide it, so finding a good solution to this problem is impossible with FSP into the mix. Since the values for IBDF and HBDF were already hardcoded as FSP parameters, write them with coreboot code and use these values directly to generate the DRHD, so as to avoid using the P2SB when it might be already hidden. Note that the possibility of fireworks happening has not been ruled out. Change-Id: I7eb20182380b953a1842083e7a3c67919d6971b9 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/bootblock/pch.c M src/soc/intel/skylake/chip_fsp20.c M src/soc/intel/skylake/include/soc/systemagent.h M src/soc/intel/skylake/romstage/romstage_fsp20.c 5 files changed, 29 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/35108/1 diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index aa51cbe..9c5b674 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -30,7 +30,6 @@ #include <ec/google/chromeec/ec.h> #include <intelblocks/cpulib.h> #include <intelblocks/lpc_lib.h> -#include <intelblocks/p2sb.h> #include <intelblocks/sgx.h> #include <intelblocks/uart.h> #include <intelblocks/systemagent.h> @@ -575,30 +574,19 @@ acpi_dmar_rmrr_fixup(tmp, current); } - struct device *const p2sb_dev = pcidev_path_on_root(PCH_DEVFN_P2SB); const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff; const bool vtvc0en = MCHBAR32(VTVC0BAR) & 1; /* General VTBAR has to be set and in 32-bit space. */ - if (p2sb_dev && vtvc0bar && vtvc0en && !MCHBAR32(VTVC0BAR + 4)) { + if (vtvc0bar && vtvc0en && !MCHBAR32(VTVC0BAR + 4)) { const unsigned long tmp = current; - /* P2SB may already be hidden. There's no clear rule, when. */ - const u8 p2sb_hidden = - pci_read_config8(p2sb_dev, PCH_P2SB_E0 + 1); - pci_write_config8(p2sb_dev, PCH_P2SB_E0 + 1, 0); + current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); - const u16 ibdf = pci_read_config16(p2sb_dev, PCH_P2SB_IBDF); - const u16 hbdf = pci_read_config16(p2sb_dev, PCH_P2SB_HBDF); - - pci_write_config8(p2sb_dev, PCH_P2SB_E0 + 1, p2sb_hidden); - - current += acpi_create_dmar_drhd(current, - DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); - current += acpi_create_dmar_ds_ioapic(current, - 2, ibdf >> 8, PCI_SLOT(ibdf), PCI_FUNC(ibdf)); - current += acpi_create_dmar_ds_msi_hpet(current, - 0, hbdf >> 8, PCI_SLOT(hbdf), PCI_FUNC(hbdf)); + current += acpi_create_dmar_ds_ioapic(current, 2, V_P2SB_IBDF_BUS, + V_P2SB_IBDF_DEV, V_P2SB_IBDF_FUN); + current += acpi_create_dmar_ds_msi_hpet(current, 0, V_P2SB_HBDF_BUS, + V_P2SB_HBDF_DEV, V_P2SB_HBDF_FUN); acpi_dmar_drhd_fixup(tmp, current); } diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index c95a8d8..cc43415 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -35,6 +35,7 @@ #include <soc/pm.h> #include <soc/pmc.h> #include <soc/smbus.h> +#include <soc/systemagent.h> #include "../chip.h" @@ -50,6 +51,12 @@ fast_spi_early_init(SPI_BASE_ADDRESS); p2sb_enable_bar(); p2sb_configure_hpet(); + + // Write the IOAPIC Bus:Dev.Fun value to P2SB IBDF register + pci_write_config16(PCH_DEV_P2SB, PCH_P2SB_IBDF, V_DEFAULT_IBDF); + + // Write the HPET Bus:Dev.Fun value to P2SB HBDF register + pci_write_config16(PCH_DEV_P2SB, PCH_P2SB_HBDF, V_DEFAULT_HBDF); } static void soc_config_acpibase(void) diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 064f71e..fa39607 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -484,10 +484,8 @@ params->X2ApicOptOut = 0; tconfig->VtdDisable = 0; - params->PchIoApicBdfValid = 1; - params->PchIoApicBusNumber = 250; - params->PchIoApicDeviceNumber = 31; - params->PchIoApicFunctionNumber = 0; + // We set that in coreboot already + params->PchIoApicBdfValid = 0; } soc_irq_settings(params); diff --git a/src/soc/intel/skylake/include/soc/systemagent.h b/src/soc/intel/skylake/include/soc/systemagent.h index d7dec65..42b4eec 100644 --- a/src/soc/intel/skylake/include/soc/systemagent.h +++ b/src/soc/intel/skylake/include/soc/systemagent.h @@ -61,4 +61,16 @@ VTVC0_BASE_SIZE, "VTVC0BAR" }; + +// Hardcoded default values for PCI Bus:Dev.Fun for IOAPIC and HPET +#define V_P2SB_IBDF_BUS 250 +#define V_P2SB_IBDF_DEV 31 +#define V_P2SB_IBDF_FUN 0 +#define V_DEFAULT_IBDF ((V_P2SB_IBDF_BUS << 8) | PCI_DEVFN(V_P2SB_IBDF_DEV, V_P2SB_IBDF_FUN)) + +#define V_P2SB_HBDF_BUS 250 +#define V_P2SB_HBDF_DEV 15 +#define V_P2SB_HBDF_FUN 0 +#define V_DEFAULT_HBDF ((V_P2SB_HBDF_BUS << 8) | PCI_DEVFN(V_P2SB_HBDF_DEV, V_P2SB_HBDF_FUN)) + #endif diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 8b5cd18..00cb6fe 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -288,10 +288,8 @@ cpu_flex_override(m_cfg); if (!config->ignore_vtd) { - m_cfg->PchHpetBdfValid = 1; - m_cfg->PchHpetBusNumber = 250; - m_cfg->PchHpetDeviceNumber = 15; - m_cfg->PchHpetFunctionNumber = 0; + // We set that in coreboot already + m_cfg->PchHpetBdfValid = 0; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/35108 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7eb20182380b953a1842083e7a3c67919d6971b9 Gerrit-Change-Number: 35108 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

5 24

Change in coreboot[master]: mb/google/drallion: memory spd data debug
by EricR Lai (Code Review) 03 Sep '19

03 Sep '19

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35157 ) Change subject: mb/google/drallion: memory spd data debug ...................................................................... mb/google/drallion: memory spd data debug Add debug function for printing SPD data. This can be enable by unmark the SPD_DEBUG flag. BUG=b:139397313 BRANCH=N/A TEST=Tested the same code on Hatch and checked cbmem log. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ie8e448f6f53db4ea0fd2ffdc58699064716c1d57 --- M src/mainboard/google/drallion/romstage.c 1 file changed, 114 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/35157/1 diff --git a/src/mainboard/google/drallion/romstage.c b/src/mainboard/google/drallion/romstage.c index 20eee7f..12cc3b3 100644 --- a/src/mainboard/google/drallion/romstage.c +++ b/src/mainboard/google/drallion/romstage.c @@ -17,6 +17,117 @@ #include <soc/cnl_memcfg_init.h> #include <soc/romstage.h> +//#define SPD_DEBUG +#ifdef SPD_DEBUG +#include <variant/gpio.h> +#include <console/console.h> +#include <cbfs.h> + +/* Offset to identify DRAM type. */ +#define SPD_DRAM_TYPE_OFF 2 +#define SPD_DRAM_DDR4 0x0c + +/* Length of SPD data. */ +#define SPD_LEN_DDR4 512 + +/* Fields that are common across different memory types. */ +#define SPD_DENSITY_BANKS_OFF 4 +#define SPD_ADDRESSING_OFF 5 +#define SPD_PART_LEN 18 + +/* Fields that are different depending upon memory type. */ +#define SPD_ORG_OFF_DDR4 12 +#define SPD_BUSW_OFF_DDR4 13 +#define SPD_PART_OFF_DDR4 329 + +static const struct dram_info { + const char *str; + uint16_t type_code; + uint16_t len; + uint16_t org_off; + uint16_t busw_off; + uint16_t part_off; +} spd_info = { + .str = "DDR4", + .type_code = SPD_DRAM_DDR4, + .len = SPD_LEN_DDR4, + .org_off = SPD_ORG_OFF_DDR4, + .busw_off = SPD_BUSW_OFF_DDR4, + .part_off = SPD_PART_OFF_DDR4, +}; + +static void mainboard_print_spd_info(const uint8_t *spd) +{ + const int spd_banks[10] = { 4, 8, -1, -1, 8, 16, -1, -1, 16, 32 }; + const int spd_capmb[10] = { 1, 2, 4, 8, 16, 32, 64, 128, 48, 96 }; + const int spd_rows[8] = { 12, 13, 14, 15, 16, 17, 18, -1 }; + const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 }; + const int spd_ranks[8] = { 1, 2, 3, 4, 5, 6, 7, 8 }; + const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 }; + const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; + char spd_name[SPD_PART_LEN+1] = { 0 }; + const struct dram_info *info = &spd_info; + + /* Module type */ + printk(BIOS_INFO, "SPD: module type is %s\n", info->str); + + int banks = spd_banks[(spd[SPD_DENSITY_BANKS_OFF] >> 4) & 7]; + int capmb = spd_capmb[spd[SPD_DENSITY_BANKS_OFF] & 7] * 256; + int rows = spd_rows[(spd[SPD_ADDRESSING_OFF] >> 3) & 7]; + int cols = spd_cols[spd[SPD_ADDRESSING_OFF] & 7]; + int ranks = spd_ranks[(spd[info->org_off] >> 3) & 7]; + int devw = spd_devw[spd[info->org_off] & 7]; + int busw = spd_busw[spd[info->busw_off] & 7]; + + /* Module Part Number */ + memcpy(spd_name, &spd[info->part_off], SPD_PART_LEN); + spd_name[SPD_PART_LEN] = 0; + printk(BIOS_INFO, "SPD: module part is %s\n", spd_name); + + printk(BIOS_INFO, + "SPD: banks %d, ranks %d, rows %d, columns %d, density %d Mb\n", + banks, ranks, rows, cols, capmb); + printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n", + devw, busw); + + if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) { + /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */ + printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n", + capmb / 8 * busw / devw * ranks); + } +} + +static void mainboard_debug_spd_data(void) +{ + char *spd_file; + size_t spd_file_len; + int spd_index; + const size_t spd_len = spd_info.len; + const char *spd_bin = "spd.bin"; + + spd_index = variant_memory_sku(); + + printk(BIOS_INFO, "SPD: index %d\n", spd_index); + + /* Load SPD data from CBFS */ + spd_file = cbfs_boot_map_with_leak(spd_bin, CBFS_TYPE_SPD, + &spd_file_len); + if (!spd_file) + die("SPD data not found."); + + /* make sure we have at least one SPD in the file. */ + if (spd_file_len < spd_len) + die("Missing SPD data."); + + /* Make sure we did not overrun the buffer */ + if (spd_file_len < ((spd_index + 1) * spd_len)) + die("Invalid SPD index."); + + spd_index *= spd_len; + mainboard_print_spd_info((uint8_t *)(spd_file + spd_index)); +} +#endif + static const struct cnl_mb_cfg memcfg = { /* Access memory info through SMBUS. */ .spd[0] = { @@ -58,6 +169,8 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) { wilco_ec_romstage_init(); - +#ifdef SPD_DEBUG + mainboard_debug_spd_data(); +#endif cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); } -- To view, visit https://review.coreboot.org/c/coreboot/+/35157 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8e448f6f53db4ea0fd2ffdc58699064716c1d57 Gerrit-Change-Number: 35157 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

2 11

Change in coreboot[master]: soc/intel/common/acpi/dptf: Add fan based active cooling for TSR sensors
by Sumeet R Pawnikar (Code Review) 03 Sep '19

03 Sep '19

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35127 ) Change subject: soc/intel/common/acpi/dptf: Add fan based active cooling for TSR sensors ...................................................................... soc/intel/common/acpi/dptf: Add fan based active cooling for TSR sensors Add fan based active cooling for TSR sensors temperature range. BUG=None BRANCH=None TEST=Verified Fan control functionality for TSR0/1 on Hatch. Change-Id: I957ae96cf6fa7d2467e73155d64f76a6bd652e31 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/soc/intel/common/acpi/dptf/thermal.asl 1 file changed, 78 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/35127/1 diff --git a/src/soc/intel/common/acpi/dptf/thermal.asl b/src/soc/intel/common/acpi/dptf/thermal.asl index ca128c9..534ab9b 100644 --- a/src/soc/intel/common/acpi/dptf/thermal.asl +++ b/src/soc/intel/common/acpi/dptf/thermal.asl @@ -155,6 +155,51 @@ { \_SB.PCI0.LPCB.EC0.PATD (TMPI) } + +#ifdef DPTF_ENABLE_FAN_CONTROL +#ifdef DPTF_TSR0_ACTIVE_AC0 + Method (_AC0) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC0)) + } +#endif +#ifdef DPTF_TSR0_ACTIVE_AC1 + Method (_AC1) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC1)) + } +#endif +#ifdef DPTF_TSR0_ACTIVE_AC2 + Method (_AC2) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC2)) + } +#endif +#ifdef DPTF_TSR0_ACTIVE_AC3 + Method (_AC3) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC3)) + } +#endif +#ifdef DPTF_TSR0_ACTIVE_AC4 + Method (_AC4) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC4)) + } +#endif +#ifdef DPTF_TSR0_ACTIVE_AC5 + Method (_AC5) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC5)) + } +#endif +#ifdef DPTF_TSR0_ACTIVE_AC6 + Method (_AC6) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC6)) + } +#endif +#endif } #endif @@ -219,6 +264,39 @@ { \_SB.PCI0.LPCB.EC0.PATD (TMPI) } + +#ifdef DPTF_ENABLE_FAN_CONTROL +#ifdef DPTF_TSR1_ACTIVE_AC0 + Method (_AC0) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC0)) + } +#endif +#ifdef DPTF_TSR1_ACTIVE_AC1 + Method (_AC1) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC1)) + } +#endif +#ifdef DPTF_TSR1_ACTIVE_AC2 + Method (_AC2) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC2)) + } +#endif +#ifdef DPTF_TSR1_ACTIVE_AC3 + Method (_AC3) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC3)) + } +#endif +#ifdef DPTF_TSR1_ACTIVE_AC4 + Method (_AC4) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC4)) + } +#endif +#endif } #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/35127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I957ae96cf6fa7d2467e73155d64f76a6bd652e31 Gerrit-Change-Number: 35127 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

3 13

Change in coreboot[master]: soc/skylake: prevent null pointer dereferences
by Angel Pons (Code Review) 02 Sep '19

02 Sep '19

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35173 ) Change subject: soc/skylake: prevent null pointer dereferences ...................................................................... soc/skylake: prevent null pointer dereferences Change-Id: Ide10223e7fc37a6c4bfa408234ef3efe1846236a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip_fsp20.c 2 files changed, 19 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/35173/1 diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index a7d5872..812572a 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -153,10 +153,7 @@ /* Enable ISH if device is on */ dev = pcidev_path_on_root(PCH_DEVFN_ISH); - if (dev) - params->IshEnable = dev->enabled; - else - params->IshEnable = 0; + params->IshEnable = (dev) ? dev->enabled : 0; params->EnableAzalia = config->EnableAzalia; params->IoBufferOwnership = config->IoBufferOwnership; @@ -210,23 +207,24 @@ * do the changes and then lock it back in coreboot * */ - if (config->HeciEnabled == 0) - params->PsfUnlock = 1; - else - params->PsfUnlock = 0; + params->PsfUnlock = !config->HeciEnabled; for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++) fill_vr_domain_config(params, i, &config->domain_vr_config[i]); /* Show SPI controller if enabled in devicetree.cb */ dev = pcidev_path_on_root(PCH_DEVFN_SPI); - params->ShowSpiController = dev->enabled; + params->ShowSpiController = (dev) ? dev->enabled : 0; /* Enable xDCI controller if enabled in devicetree and allowed */ dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); - if (!xdci_can_enable()) - dev->enabled = 0; - params->XdciEnable = dev->enabled; + if (dev) { + if (!xdci_can_enable()) + dev->enabled = 0; + params->XdciEnable = dev->enabled; + } else { + params->XdciEnable = 0; + } params->SendVrMbxCmd = config->SendVrMbxCmd; diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 064f71e..d594bbb 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -354,10 +354,7 @@ /* If ISH is enabled, enable ISH elements */ dev = pcidev_path_on_root(PCH_DEVFN_ISH); - if (dev) - params->PchIshEnable = dev->enabled; - else - params->PchIshEnable = 0; + params->PchIshEnable = (dev) ? dev->enabled : 0; params->PchHdaEnable = config->EnableAzalia; params->PchHdaIoBufferOwnership = config->IoBufferOwnership; @@ -433,13 +430,17 @@ /* Show SPI controller if enabled in devicetree.cb */ dev = pcidev_path_on_root(PCH_DEVFN_SPI); - params->ShowSpiController = dev->enabled; + params->ShowSpiController = (dev) ? dev->enabled : 0; /* Enable xDCI controller if enabled in devicetree and allowed */ dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); - if (!xdci_can_enable()) - dev->enabled = 0; - params->XdciEnable = dev->enabled; + if (dev) { + if (!xdci_can_enable()) + dev->enabled = 0; + params->XdciEnable = dev->enabled; + } else { + params->XdciEnable = 0; + } /* * Send VR specific mailbox commands: -- To view, visit https://review.coreboot.org/c/coreboot/+/35173 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide10223e7fc37a6c4bfa408234ef3efe1846236a Gerrit-Change-Number: 35173 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

4 8

Change in ...coreboot[master]: soc/intel/quark: Remove variable set but not used
by HAOUAS Elyes (Code Review) 02 Sep '19

02 Sep '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32912 Change subject: soc/intel/quark: Remove variable set but not used ...................................................................... soc/intel/quark: Remove variable set but not used Change-Id: I09292c2776309982cfb4d72012991bf7725b75fb Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/quark/i2c.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/32912/1 diff --git a/src/soc/intel/quark/i2c.c b/src/soc/intel/quark/i2c.c index 595c818..49ebaa2 100644 --- a/src/soc/intel/quark/i2c.c +++ b/src/soc/intel/quark/i2c.c @@ -117,7 +117,6 @@ int bytes_transferred; uint32_t cmd; int fifo_bytes; - uint8_t junk; I2C_REGS *regs; uint32_t status; @@ -128,7 +127,7 @@ /* Empty the FIFO */ status = regs->ic_status; while (status & IC_STATUS_RFNE) { - junk = (uint8_t)regs->ic_data_cmd; + (uint8_t)regs->ic_data_cmd; status = regs->ic_status; } -- To view, visit https://review.coreboot.org/c/coreboot/+/32912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09292c2776309982cfb4d72012991bf7725b75fb Gerrit-Change-Number: 32912 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 8

Change in ...coreboot[master]: ec/kontron/kempld: Select DRIVERS_UART_8250IO
by Thomas Heijligen (Code Review) 02 Sep '19

02 Sep '19

Hello Nico Huber, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31366 to review the following change. Change subject: ec/kontron/kempld: Select DRIVERS_UART_8250IO ...................................................................... ec/kontron/kempld: Select DRIVERS_UART_8250IO Change-Id: I1d0a46b6e4fc3aea403e2adce987de30703358c7 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/ec/kontron/kempld/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/31366/1 diff --git a/src/ec/kontron/kempld/Kconfig b/src/ec/kontron/kempld/Kconfig index 647bd12..08401c9 100644 --- a/src/ec/kontron/kempld/Kconfig +++ b/src/ec/kontron/kempld/Kconfig @@ -1,5 +1,6 @@ config EC_KONTRON_KEMPLD bool + select DRIVERS_UART_8250IO help Driver for Kontron's express module programmable logic device used on their COMexpress modules. -- To view, visit https://review.coreboot.org/c/coreboot/+/31366 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d0a46b6e4fc3aea403e2adce987de30703358c7 Gerrit-Change-Number: 31366 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

3 3

Change in ...libgfxinit[master]: gma display_probing: End probing after all ports failed
by Nico Huber (Code Review) 02 Sep '19

02 Sep '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/32728 Change subject: gma display_probing: End probing after all ports failed ...................................................................... gma display_probing: End probing after all ports failed In case of failure, we kept trying the last port in the list for further pipelines. Fix that. Change-Id: Id434492a7186f3b9431fd98dc16c0a7aa0e92501 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M common/hw-gfx-gma-display_probing.adb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/28/32728/1 diff --git a/common/hw-gfx-gma-display_probing.adb b/common/hw-gfx-gma-display_probing.adb index cd2a452..d21b277 100644 --- a/common/hw-gfx-gma-display_probing.adb +++ b/common/hw-gfx-gma-display_probing.adb @@ -1,5 +1,6 @@ -- -- Copyright (C) 2015-2016 secunet Security Networks AG +-- Copyright (C) 2019 Nico Huber <nico.h(a)gmx.de> -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -183,6 +184,7 @@ for Pipe in Pipe_Index range Pipe_Index'First .. Pipe_Index'Min (Max_Pipe, Config.Max_Pipe) loop + Success := False; while Ports (Port_Idx) /= Disabled loop if not Port_Configured (Configs, Ports (Port_Idx)) and (not Has_Sibling_Port (Ports (Port_Idx)) or @@ -198,6 +200,7 @@ exit when Success; end loop; + exit when not Success; end loop; -- Restore power settings -- To view, visit https://review.coreboot.org/c/libgfxinit/+/32728 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: Id434492a7186f3b9431fd98dc16c0a7aa0e92501 Gerrit-Change-Number: 32728 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

3 4

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit August 2019