coreboot-gerrit August 2019

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Change in coreboot[master]: [WIP] arch/x86: Refactor CAR_GLOBAL quirk for FSP1.0
by Kyösti Mälkki (Code Review) 10 Sep '19

10 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35140 ) Change subject: [WIP] arch/x86: Refactor CAR_GLOBAL quirk for FSP1.0 ...................................................................... [WIP] arch/x86: Refactor CAR_GLOBAL quirk for FSP1.0 These platforms return to romstage from FSP only after already having torn CAR down. A copy of the entire CAR region is available and discoverable via HOB. Previously, CBMEM console detected on-the-fly that CAR migration had happened and relocated cbmem_console_p accoringlin with car_sync_var(). However, if the CAR_GLOBAL pointing to another object inside CAR is a relative offset instead, we have a more generic solution that can be used with timestamps code as well. Change-Id: Ica877b47e68d56189e9d998b5630019d4328a419 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/arm/include/arch/early_variables.h M src/arch/arm64/include/arch/early_variables.h M src/arch/mips/include/arch/early_variables.h M src/arch/ppc64/include/arch/early_variables.h M src/arch/riscv/include/arch/early_variables.h M src/arch/x86/include/arch/early_variables.h M src/cpu/x86/car.c M src/lib/cbmem_console.c 8 files changed, 49 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/35140/1 diff --git a/src/arch/arm/include/arch/early_variables.h b/src/arch/arm/include/arch/early_variables.h index 9f06923..e559e9b 100644 --- a/src/arch/arm/include/arch/early_variables.h +++ b/src/arch/arm/include/arch/early_variables.h @@ -18,7 +18,9 @@ static inline void *car_get_var_ptr(void *var) { return var; } #define car_get_var(var) (var) -#define car_sync_var(var) (var) #define car_set_var(var, val) do { (var) = (val); } while (0) +#define car_get_reloc_ptr car_get_var +#define car_set_reloc_ptr car_set_var + #endif diff --git a/src/arch/arm64/include/arch/early_variables.h b/src/arch/arm64/include/arch/early_variables.h index 9f06923..e559e9b 100644 --- a/src/arch/arm64/include/arch/early_variables.h +++ b/src/arch/arm64/include/arch/early_variables.h @@ -18,7 +18,9 @@ static inline void *car_get_var_ptr(void *var) { return var; } #define car_get_var(var) (var) -#define car_sync_var(var) (var) #define car_set_var(var, val) do { (var) = (val); } while (0) +#define car_get_reloc_ptr car_get_var +#define car_set_reloc_ptr car_set_var + #endif diff --git a/src/arch/mips/include/arch/early_variables.h b/src/arch/mips/include/arch/early_variables.h index 8fc9c19..32f4b6b 100644 --- a/src/arch/mips/include/arch/early_variables.h +++ b/src/arch/mips/include/arch/early_variables.h @@ -19,7 +19,9 @@ static inline void *car_get_var_ptr(void *var) { return var; } #define car_get_var(var) (var) -#define car_sync_var(var) (var) #define car_set_var(var, val) { (var) = (val); } +#define car_get_reloc_ptr car_get_var +#define car_set_reloc_ptr car_set_var + #endif /* __MIPS_ARCH_EARLY_VARIABLES_H */ diff --git a/src/arch/ppc64/include/arch/early_variables.h b/src/arch/ppc64/include/arch/early_variables.h index 22c3750..539e7f9 100644 --- a/src/arch/ppc64/include/arch/early_variables.h +++ b/src/arch/ppc64/include/arch/early_variables.h @@ -19,8 +19,9 @@ #define CAR_MIGRATE(migrate_fn_) static inline void *car_get_var_ptr(void *var) { return var; } #define car_get_var(var) (var) -#define car_sync_var(var) (var) - #define car_set_var(var, val) do { (var) = (val); } while (0) +#define car_get_reloc_ptr car_get_var +#define car_set_reloc_ptr car_set_var + #endif diff --git a/src/arch/riscv/include/arch/early_variables.h b/src/arch/riscv/include/arch/early_variables.h index acc5ac3..69f5f56 100644 --- a/src/arch/riscv/include/arch/early_variables.h +++ b/src/arch/riscv/include/arch/early_variables.h @@ -21,7 +21,9 @@ #define CAR_MIGRATE(migrate_fn_) static inline void *car_get_var_ptr(void *var) { return var; } #define car_get_var(var) (var) -#define car_sync_var(var) (var) #define car_set_var(var, val) do { (var) = (val); } while (0) +#define car_get_reloc_ptr car_get_var +#define car_set_reloc_ptr car_set_var + #endif diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h index 3910a82..4b29fa3 100644 --- a/src/arch/x86/include/arch/early_variables.h +++ b/src/arch/x86/include/arch/early_variables.h @@ -33,19 +33,23 @@ /* Get the correct pointer for the CAR global variable. */ void *car_get_var_ptr(void *var); -/* Get and update a CAR_GLOBAL pointing elsewhere in car.global_data*/ -void *car_sync_var_ptr(void *var); - /* Return 1 when currently running with globals in Cache-as-RAM, 0 otherwise. */ int car_active(void); /* Get and set a primitive type global variable. */ #define car_get_var(var) \ (*(typeof(var) *)car_get_var_ptr(&(var))) -#define car_sync_var(var) \ - (*(typeof(var) *)car_sync_var_ptr(&(var))) #define car_set_var(var, val) car_get_var(var) = (val) +/* Get and set a CAR_GLOBAL pointing elsewhere inside CAR. */ +#if CONFIG(PLATFORM_USES_FSP1_0) +void *car_get_reloc_ptr(void *var); +void car_set_reloc_ptr(void *var, void *tgt); +#else +#define car_get_reloc_ptr car_get_var +#define car_set_reloc_ptr car_set_var +#endif + static inline size_t car_data_size(void) { size_t car_size = _car_relocatable_data_size; @@ -66,9 +70,11 @@ #define CAR_GLOBAL #define car_get_var(var) (var) -#define car_sync_var(var) (var) #define car_set_var(var, val) (var) = (val) +#define car_get_reloc_ptr car_get_var +#define car_set_reloc_ptr car_set_var + static inline void *car_get_var_ptr(void *var) { return var; diff --git a/src/cpu/x86/car.c b/src/cpu/x86/car.c index 6fc6168..285e29f 100644 --- a/src/cpu/x86/car.c +++ b/src/cpu/x86/car.c @@ -77,42 +77,31 @@ return &migrated_base[offset]; } +#if CONFIG(PLATFORM_USES_FSP1_0) /* - * Update a CAR_GLOBAL variable var, originally pointing to CAR region, - * with the address in migrated CAR region in DRAM. + * Pointers to CAR_GLOBALs use relative addressing, this way discovery + * of objects that are not CAR_GLOBALs themselves, remain discoverable + * after CAR migration has happened. */ -void *car_sync_var_ptr(void *var) +void car_set_reloc_ptr(void *var, void *dst) { - void **mig_var = car_get_var_ptr(var); - void *_car_start = _car_relocatable_data_start; - void *_car_end = _car_relocatable_data_end; - - /* Not moved or migrated yet. */ - if (mig_var == var) - return mig_var; - - /* - * Migrate the cbmem console pointer for FSP 1.0 platforms. Otherwise, - * keep console buffer in CAR until cbmemc_reinit() moves it. - */ - if (*mig_var == _preram_cbmem_console) { - if (CONFIG(PLATFORM_USES_FSP1_0)) - *mig_var += (char *)mig_var - (char *)var; - return mig_var; - } - - /* It's already pointing outside car.global_data. */ - if (*mig_var < _car_start || *mig_var > _car_end) - return mig_var; - - /* Move the pointer by the same amount the variable storing it was - * moved by. - */ - *mig_var += (char *)mig_var - (char *)var; - - return mig_var; + uintptr_t *mig_var = car_get_var_ptr(var); + if (dst) + *mig_var = (uintptr_t)dst - (uintptr_t)mig_var; + else + *mig_var = 0; } +void *car_get_reloc_ptr(void *var) +{ + uintptr_t *mig_var = car_get_var_ptr(var); + if (*mig_var) + return (void *)((uintptr_t)mig_var + *mig_var); + else + return NULL; +} +#endif + int car_active(void) { return !car_migrated; diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index df2d1ff..1987a99 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -73,12 +73,12 @@ static struct cbmem_console *current_console(void) { - return car_sync_var(cbmem_console_p); + return car_get_reloc_ptr(cbmem_console_p); } static void current_console_set(struct cbmem_console *new_console_p) { - car_set_var(cbmem_console_p, new_console_p); + car_set_reloc_ptr(cbmem_console_p, new_console_p); } static int buffer_valid(struct cbmem_console *cbm_cons_p, u32 total_space) -- To view, visit https://review.coreboot.org/c/coreboot/+/35140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica877b47e68d56189e9d998b5630019d4328a419 Gerrit-Change-Number: 35140 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/asrock/h110m: add missing pci devices to tree
by Maxim Polyakov (Code Review) 09 Sep '19

09 Sep '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35100 ) Change subject: mb/asrock/h110m: add missing pci devices to tree ...................................................................... mb/asrock/h110m: add missing pci devices to tree These devices turn on after initializing the Intel FSP Change-Id: I0a15537b6ba56fcf63267641ef2219f24d25d9c4 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/35100/1 diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 24409a1..f51f477 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -273,6 +273,8 @@ device pci 02.0 on # Integrated Graphics Device subsystemid 0x1849 0x1912 end + device pci 04.0 on # Thermal Subsystem + device pci 08.0 on # Gaussian Mixture Model device pci 14.0 on # USB xHCI subsystemid 0x1849 0xa131 end -- To view, visit https://review.coreboot.org/c/coreboot/+/35100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a15537b6ba56fcf63267641ef2219f24d25d9c4 Gerrit-Change-Number: 35100 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/asrock/h110m: disable unused sata ports
by Maxim Polyakov (Code Review) 09 Sep '19

09 Sep '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35071 ) Change subject: mb/asrock/h110m: disable unused sata ports ...................................................................... mb/asrock/h110m: disable unused sata ports Change-Id: I5b3ad372f1d6607cc7b4a78e3c59d2a5ae1d2cf5 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/35071/1 diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index f87ca45..24409a1 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -184,8 +184,8 @@ [3] = 1, \ [4] = 1, \ [5] = 1, \ - [6] = 1, \ - [7] = 1, \ + [6] = 0, \ + [7] = 0, \ }" # PCH UART, SPI, I2C -- To view, visit https://review.coreboot.org/c/coreboot/+/35071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b3ad372f1d6607cc7b4a78e3c59d2a5ae1d2cf5 Gerrit-Change-Number: 35071 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: mb/asrock/h110m: remove unsed i2c_voltage settings
by Maxim Polyakov (Code Review) 09 Sep '19

09 Sep '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35069 ) Change subject: mb/asrock/h110m: remove unsed i2c_voltage settings ...................................................................... mb/asrock/h110m: remove unsed i2c_voltage settings The string "register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" was mistakenly taken from the Intel KBL-RVP8 devicetree.cb. Remove it, since the i2c4 bus is disabled in the "SerialIoDevMode" register Change-Id: I44ecd5c22efd66b02a2851dc14a1a95421f39a71 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/35069/1 diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index bf718b8..934083a 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -146,8 +146,6 @@ }" register "EnableLan" = "0" - register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V - register "PmTimerDisabled" = "0" # USB -- To view, visit https://review.coreboot.org/c/coreboot/+/35069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44ecd5c22efd66b02a2851dc14a1a95421f39a71 Gerrit-Change-Number: 35069 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mb/asrock/h110m: use VR_CFG_AMP() macro to set PSI threshold
by Maxim Polyakov (Code Review) 09 Sep '19

09 Sep '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35068 ) Change subject: mb/asrock/h110m: use VR_CFG_AMP() macro to set PSI threshold ...................................................................... mb/asrock/h110m: use VR_CFG_AMP() macro to set PSI threshold Change-Id: Iafeb7f7689a16d3b16eb0564c4dd72919a8d1382 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/35068/1 diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 61d3e66..bf718b8 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -95,9 +95,9 @@ # * - is set automatically for the KBL-S/KBL-DT CPUs in the vr_config.c register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x10, \ - .psi3threshold = 0x4, \ + .psi1threshold = VR_CFG_AMP(20), \ + .psi2threshold = VR_CFG_AMP(4), \ + .psi3threshold = VR_CFG_AMP(1), \ .psi3enable = 1, \ .psi4enable = 1, \ .imon_slope = 0x0, \ @@ -108,9 +108,9 @@ register "domain_vr_config[VR_IA_CORE]" = "{ .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ + .psi1threshold = VR_CFG_AMP(20), \ + .psi2threshold = VR_CFG_AMP(5), \ + .psi3threshold = VR_CFG_AMP(1), \ .psi3enable = 1, \ .psi4enable = 1, \ .imon_slope = 0x0, \ @@ -121,9 +121,9 @@ register "domain_vr_config[VR_GT_UNSLICED]" = "{ .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ + .psi1threshold = VR_CFG_AMP(20), \ + .psi2threshold = VR_CFG_AMP(5), \ + .psi3threshold = VR_CFG_AMP(1), \ .psi3enable = 1, \ .psi4enable = 1, \ .imon_slope = 0x0, \ @@ -134,9 +134,9 @@ register "domain_vr_config[VR_GT_SLICED]" = "{ .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ + .psi1threshold = VR_CFG_AMP(20), \ + .psi2threshold = VR_CFG_AMP(5), \ + .psi3threshold = VR_CFG_AMP(1), \ .psi3enable = 1, \ .psi4enable = 1, \ .imon_slope = 0x0, \ -- To view, visit https://review.coreboot.org/c/coreboot/+/35068 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iafeb7f7689a16d3b16eb0564c4dd72919a8d1382 Gerrit-Change-Number: 35068 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: mb/asrock/h110m: fix VR Settings Configuration info
by Maxim Polyakov (Code Review) 09 Sep '19

09 Sep '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35067 ) Change subject: mb/asrock/h110m: fix VR Settings Configuration info ...................................................................... mb/asrock/h110m: fix VR Settings Configuration info In accordance with changes in the initialization code for Skylake/Kaby Lake CPU [1], the IccMax is set automatically in vr_config.c The patch adds a comment about this and fixes invalid parameter values in the VR settings information. [1] https://review.coreboot.org/c/coreboot/+/34937 Change-Id: I6e1aefde135ffce75a5d837348595aa20aff0513 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/35067/1 diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 3067ffe..61d3e66 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -89,9 +89,10 @@ #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | #| ImonSlope | 0 | 0 | 0 | 0 | 0 | #| ImonOffset | 0 | 0 | 0 | 0 | 0 | - #| IccMax | 7A | 34A | 34A | 35A | 35A | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | + #| IccMax* | 0 | 0 | 0 | 0 | 0 | + #| VrVoltageLimit | 0 | 0 | 0 | 0 | 0 | #+----------------+-------+-------+-------------+-------------+-------+ + # * - is set automatically for the KBL-S/KBL-DT CPUs in the vr_config.c register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ .vr_config_enable = 1, \ .psi1threshold = 0x50, \ -- To view, visit https://review.coreboot.org/c/coreboot/+/35067 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e1aefde135ffce75a5d837348595aa20aff0513 Gerrit-Change-Number: 35067 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: Add ability to disable Heci1
by Bora Guvendik (Code Review) 09 Sep '19

09 Sep '19

Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32992 Change subject: soc/intel/cannonlake: Add ability to disable Heci1 ...................................................................... soc/intel/cannonlake: Add ability to disable Heci1 Decide if HECI1 should be hidden prior to boot to OS. BUG=none TEST=Boot to OS, verify if Heci1 is disabled Change-Id: I7c63316c8b04fb101d34064daac5ba4fdc05a63c Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/cannonlake/romstage/fsp_params.c 3 files changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/32992/1 diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 0d51c1c..6bea8fe 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -421,6 +421,7 @@ * Bit 0: MISCCFG_GPDLCGEN */ uint8_t gpio_pm[TOTAL_GPIO_COMM]; + uint8_t Heci1Disabled; }; typedef struct soc_intel_cannonlake_config config_t; diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index dd93882..7dc1dd0 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -341,6 +341,7 @@ params->ScsUfsEnabled = dev->enabled; params->Heci3Enabled = config->Heci3Enabled; + params->Heci1Disabled = config->Heci1Disabled; params->Device4Enable = config->Device4Enable; /* VrConfig Settings for 5 domains diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 6e492bb..365fb9f 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -25,7 +25,6 @@ #include <vendorcode/google/chromeos/chromeos.h> #include "../chip.h" - static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) { unsigned int i; -- To view, visit https://review.coreboot.org/c/coreboot/+/32992 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c63316c8b04fb101d34064daac5ba4fdc05a63c Gerrit-Change-Number: 32992 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [WIP] ssdtgen for PNP devices
by Patrick Rudolph (Code Review) 08 Sep '19

08 Sep '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33033 Change subject: [WIP] ssdtgen for PNP devices ...................................................................... [WIP] ssdtgen for PNP devices Automatically create ACPI code for PNP devices. TODO: Add HID to devicetree. Change-Id: I2716ae0580d68e5d4fcc484cb1648a2cdc1f4ca0 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- A src/superio/common/chip.h A src/superio/common/ssdt.c A src/superio/common/ssdt.h 3 files changed, 386 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/33033/1 diff --git a/src/superio/common/chip.h b/src/superio/common/chip.h new file mode 100644 index 0000000..2d75c0f --- /dev/null +++ b/src/superio/common/chip.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 9elements Agency GmbH <patrick.rudolph(a)9elements.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SUPERIO_COMMON_CHIP_H__ +#define __SUPERIO_COMMON_CHIP_H__ + +struct common_superio_ldn_config { + const char *acpi_name; + const char *dos_device_name; + const char *acpi_hid; +}; + +#endif /* __SUPERIO_COMMON_CHIP_H__ */ diff --git a/src/superio/common/ssdt.c b/src/superio/common/ssdt.c new file mode 100644 index 0000000..0e2c59f --- /dev/null +++ b/src/superio/common/ssdt.c @@ -0,0 +1,334 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 9elements Agency GmbH <patrick.rudolph(a)9elements.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <superio/common/chip.h> +#include <superio/common/ssdt.h> + +#include <device/device.h> +#include <device/pnp.h> +#include <arch/acpigen.h> +#include <device/pnp_def.h> +#include <console/console.h> + +#define NUM_IO 4 +#define NUM_IRQ 2 + +struct superio_dev { + const char *acpi_hid; + u16 io_base[NUM_IO]; + u8 irq[NUM_IRQ]; +}; + +static const struct superio_dev superio_devs[] = { + {"PNP0700", {0x3f0, 0x3f2, 0x3f7}, {6, }}, + {"PNP0303", {60, 64, }, {1, }}, + {"PNP0F03", {60, 64, }, {12, }}, + {"PNP0501", {0x3f8, 0x2f8, 0x3e8, 0x2e8}, {4, 3}}, + {"PNP0400", {0x378, }, {7, }}, +}; + +static const u8 io_idx[NUM_IO] = {PNP_IDX_IO0, PNP_IDX_IO1, PNP_IDX_IO2, + PNP_IDX_IO3}; +static const u8 irq_idx[NUM_IRQ] = {PNP_IDX_IRQ0, PNP_IDX_IRQ1}; + + +static void superio_base_fill_ssdt_generator(struct device *dev) +{ + const char *scope = acpi_device_scope(dev); + const char *name = acpi_device_name(dev); + + if (!scope || !name) { + printk(BIOS_ERR, "%s: Missing ACPI path/scope\n", dev_path(dev)); + return; + } + + /* Device */ + acpigen_write_scope(scope); + acpigen_write_device(name); + + printk(BIOS_DEBUG, "%s.%s: %s\n", scope, name, dev_path(dev)); + + acpigen_write_name_string("_HID", "PNP0C02"); + acpigen_write_name_string("_DDN", dev_name(dev)); + + /* OperationRegion("IOID", SYSTEMIO, port, 2) */ + struct opregion opreg = OPREGION("IOID", SYSTEMIO, + dev->path.pnp.port, 2); + acpigen_write_opregion(&opreg); + + struct fieldlist l[] = { + FIELDLIST_OFFSET(0), + FIELDLIST_NAMESTR("INDX", 8), + FIELDLIST_NAMESTR("DATA", 8), + }; + + /* Field (IOID, AnyAcc, NoLock, Preserve) + * { + * Offset (0), + * INDX, 8, + * DATA, 8, + * } */ + acpigen_write_field(opreg.name, l, ARRAY_SIZE(l), FIELD_BYTEACC | + FIELD_NOLOCK | FIELD_PRESERVE); + + struct fieldlist i[] = { + FIELDLIST_OFFSET(0x07), + FIELDLIST_NAMESTR("LDN", 8), + FIELDLIST_OFFSET(0x21), + FIELDLIST_NAMESTR("SCF1", 8), + FIELDLIST_NAMESTR("SCF2", 8), + FIELDLIST_NAMESTR("SCF3", 8), + FIELDLIST_NAMESTR("SCF4", 8), + FIELDLIST_NAMESTR("SCF5", 8), + FIELDLIST_NAMESTR("SCF6", 8), + FIELDLIST_NAMESTR("SCF7", 8), + FIELDLIST_OFFSET(0x29), + FIELDLIST_NAMESTR("CKCF", 8), + FIELDLIST_OFFSET(0x2F), + FIELDLIST_NAMESTR("SCFF", 8), + FIELDLIST_NAMESTR("ACTR", 8), + FIELDLIST_OFFSET(0x60), + FIELDLIST_NAMESTR("IOAH", 8), + FIELDLIST_NAMESTR("IOAL", 8), + FIELDLIST_NAMESTR("IOH2", 8), + FIELDLIST_NAMESTR("IOL2", 8), + FIELDLIST_OFFSET(0x70), + FIELDLIST_NAMESTR("INTR", 4), + FIELDLIST_NAMESTR("INTT", 4), + FIELDLIST_OFFSET (0x74), + FIELDLIST_NAMESTR("DMCH", 8), + FIELDLIST_OFFSET(0xE0), + FIELDLIST_NAMESTR("RGE0", 8), + FIELDLIST_NAMESTR("RGE1", 8), + FIELDLIST_NAMESTR("RGE2", 8), + FIELDLIST_NAMESTR("RGE3", 8), + FIELDLIST_NAMESTR("RGE4", 8), + FIELDLIST_NAMESTR("RGE5", 8), + FIELDLIST_NAMESTR("RGE6", 8), + FIELDLIST_NAMESTR("RGE7", 8), + FIELDLIST_NAMESTR("RGE8", 8), + FIELDLIST_NAMESTR("RGE9", 8), + FIELDLIST_NAMESTR("RGEA", 8), + FIELDLIST_OFFSET(0xF0), + FIELDLIST_NAMESTR("OPT0", 8), + FIELDLIST_NAMESTR("OPT1", 8), + FIELDLIST_NAMESTR("OPT2", 8), + FIELDLIST_NAMESTR("OPT3", 8), + FIELDLIST_NAMESTR("OPT4", 8), + FIELDLIST_NAMESTR("OPT5", 8), + FIELDLIST_NAMESTR("OPT6", 8), + FIELDLIST_NAMESTR("OPT7", 8), + FIELDLIST_NAMESTR("OPT8", 8), + FIELDLIST_NAMESTR("OPT9", 8), + }; + + acpigen_write_indexfield("INDX", "DATA", i, ARRAY_SIZE(i), + FIELD_BYTEACC | FIELD_NOLOCK | FIELD_PRESERVE); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ +} + +static const char *superio_guess_hid(struct device *dev) +{ + for (size_t i = 0; i < ARRAY_SIZE(io_idx); i++) { + struct resource *res = probe_resource(dev, io_idx[i]); + if (!res || !res->base) + continue; + + for (size_t j = 0; j < ARRAY_SIZE(superio_devs); j++) { + for (size_t k = 0; k < NUM_IO; k++) { + if (!superio_devs[j].io_base[k]) + continue; + if (superio_devs[j].io_base[k] == res->base) + return superio_devs[j].acpi_hid; + } + } + } + for (size_t i = 0; i < ARRAY_SIZE(irq_idx); i++) { + struct resource *res = probe_resource(dev, irq_idx[i]); + if (!res || !res->size) + continue; + for (size_t j = 0; j < ARRAY_SIZE(superio_devs); j++) { + for (size_t k = 0; k < NUM_IRQ; k++) { + if (!superio_devs[j].irq[k]) + continue; + if (superio_devs[j].irq[k] == res->base) + return superio_devs[j].acpi_hid; + } + } + } + return NULL; +} + +static int ldn_resource_cnt(struct device *dev) +{ + int cnt = 0; + for (size_t i = 0; i < ARRAY_SIZE(io_idx); i++) { + struct resource *res = probe_resource(dev, io_idx[i]); + if (!res || !res->base) + continue; + cnt++; + } + for (size_t i = 0; i < NUM_IRQ; i++) { + struct resource *res = probe_resource(dev, irq_idx[i]); + if (!res || !res->size) + continue; + cnt++; + } + return cnt; +} + +/* Add IO and IRQ resources for _CRS or _PRS */ +static void ldn_gen_resources(struct device *dev) +{ + for (size_t i = 0; i < ARRAY_SIZE(io_idx); i++) { + struct resource *res = probe_resource(dev, io_idx[i]); + if (!res || !res->base) + continue; + resource_t base = res->base; + resource_t size = res->size; + while (size > 0) { + resource_t sz = size > 255 ? 255 : size; + acpigen_write_io16(base, base, 0, sz, 1); + size -= sz; + base += sz; + } + } + for (size_t i = 0; i < NUM_IRQ; i++) { + struct resource *res = probe_resource(dev, irq_idx[i]); + if (!res || !res->size) + continue; + acpigen_write_irq(res->base); + } +} + +/* Add resource base and size for additional SuperIO code */ +static void ldn_gen_resources_use(struct device *dev) +{ + char name[5]; + for (size_t i = 0; i < ARRAY_SIZE(io_idx); i++) { + struct resource *res = probe_resource(dev, io_idx[i]); + if (!res || !res->base || !res->size) + continue; + + snprintf(name, sizeof(name), "IO%XB", i); + name[4] = '\0'; + acpigen_write_name_integer(name, res->base); + + snprintf(name, sizeof(name), "IO%XS", i); + name[4] = '\0'; + acpigen_write_name_integer(name, res->size); + } +} + +static const char *ldn_acpi_name(const struct device *dev) +{ + u8 ldn = dev->path.pnp.device & 0xff; + u8 vldn = (dev->path.pnp.device >> 8) & 0x7; + static char name[5]; + + if (!vldn) + snprintf(name, sizeof(name), "LD%02X", ldn); + else + snprintf(name, sizeof(name), "VLD%X", vldn); + + name[4] = '\0'; + + return name; +} + + +void superio_common_fill_ssdt_generator(struct device *dev) +{ + struct common_superio_ldn_config *config = dev->chip_info; + const char *scope = acpi_device_path(dev); + const char *name = ldn_acpi_name(dev); + const char *hid = NULL; + const u8 ldn = dev->path.pnp.device & 0xff; + const u8 vldn = (dev->path.pnp.device >> 8) & 0x7; + bool has_resources; + + if (!scope || !name) { + printk(BIOS_ERR, "%s: Missing ACPI path/scope\n", dev_path(dev)); + return; + } + if (vldn) { + printk(BIOS_DEBUG, "%s: Ignoring virtual LDN\n", dev_path(dev)); + return; + } + + if (ldn == 0) + superio_base_fill_ssdt_generator(dev); + + printk(BIOS_DEBUG, "%s.%s: %s\n", scope, name, dev_path(dev)); + + /* Scope */ + acpigen_write_scope(scope); + + /* Device */ + acpigen_write_device(name); + + if (config && config->dos_device_name) + acpigen_write_name_string("_DDN", config->dos_device_name); + + acpigen_write_name_byte("_UID", 0); + acpigen_write_name_byte("LDN", ldn); + + acpigen_write_STA(dev->enabled ? 0xf : 0); + + if (!dev->enabled) { + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + return; + } + + has_resources = ldn_resource_cnt(dev); + + /* Resources - _CRS */ + if (has_resources) { + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + ldn_gen_resources(dev); + acpigen_write_resourcetemplate_footer(); + + /* Resources - _PRS */ + acpigen_write_name("_PRS"); + acpigen_write_resourcetemplate_header(); + ldn_gen_resources(dev); + acpigen_write_resourcetemplate_footer(); + + /* Resources base and size for 3rd party ACPI code */ + ldn_gen_resources_use(dev); + } + + if (config && config->acpi_hid) { + hid = config->acpi_hid; + } else { + printk(BIOS_WARNING, "%s: No HID set in devicetree\n", + dev_path(dev)); + + hid = superio_guess_hid(dev); + } + + if (hid) + acpigen_write_name_string("_HID", hid); + else + acpigen_write_name_string("_HID", "PNP0C02"); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ +} diff --git a/src/superio/common/ssdt.h b/src/superio/common/ssdt.h new file mode 100644 index 0000000..4d4e4b1 --- /dev/null +++ b/src/superio/common/ssdt.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 9elements Agency GmbH <patrick.rudolph(a)9elements.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SUPERIO_COMMON_SSDT_H__ +#define __SUPERIO_COMMON_SSDT_H__ + +#include <device/device.h> + +void superio_common_fill_ssdt_generator(struct device *dev); +const char *superio_common_acpi_name(const struct device *dev); +void superio_set_base_dev_ops(struct device *dev); + +#endif /* __SUPERIO_COMMON_SSDT_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/33033 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2716ae0580d68e5d4fcc484cb1648a2cdc1f4ca0 Gerrit-Change-Number: 33033 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/superio/aspeed/ast2400: Add Autogen ACPI Code
by Christian Walter (Code Review) 06 Sep '19

06 Sep '19

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33253 Change subject: src/superio/aspeed/ast2400: Add Autogen ACPI Code ...................................................................... src/superio/aspeed/ast2400: Add Autogen ACPI Code Once the Autogen ACPI Code is merged, we can use this to autogenerate the ACPI Code for the AST2400. This is WIP. Has been tested w/ AST2400. Change-Id: I2ef49bb6f733994b249ae46f0460234380b552b8 Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- M src/superio/aspeed/ast2400/Makefile.inc M src/superio/aspeed/ast2400/superio.c 2 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/33253/1 diff --git a/src/superio/aspeed/ast2400/Makefile.inc b/src/superio/aspeed/ast2400/Makefile.inc index a6f8b20..9a1a8f5 100644 --- a/src/superio/aspeed/ast2400/Makefile.inc +++ b/src/superio/aspeed/ast2400/Makefile.inc @@ -16,3 +16,4 @@ ## ramstage-$(CONFIG_SUPERIO_ASPEED_AST2400) += superio.c +ramstage-$(CONFIG_SUPERIO_ASPEED_AST2400) += ../../common/ssdt.c diff --git a/src/superio/aspeed/ast2400/superio.c b/src/superio/aspeed/ast2400/superio.c index dcb14fa..c4d0c72 100644 --- a/src/superio/aspeed/ast2400/superio.c +++ b/src/superio/aspeed/ast2400/superio.c @@ -22,6 +22,7 @@ #include <console/console.h> #include <string.h> #include <pc80/keyboard.h> +#include <superio/common/ssdt.h> #include "ast2400.h" static void ast2400_init(struct device *dev) @@ -36,6 +37,13 @@ } } +#if CONFIG(HAVE_ACPI_TABLES) +static const char *aspeed_ast2400_name(const struct device *dev) +{ + return "SIO0"; +} +#endif + static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, @@ -43,6 +51,10 @@ .enable = pnp_enable, .init = ast2400_init, .ops_pnp_mode = &pnp_conf_mode_a5a5_aa, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_fill_ssdt_generator = superio_common_fill_ssdt_generator, + .acpi_name = aspeed_ast2400_name, +#endif }; static struct pnp_info pnp_dev_info[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/33253 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ef49bb6f733994b249ae46f0460234380b552b8 Gerrit-Change-Number: 33253 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek: Fix USB enumeration issue
by Ran Bi (Code Review) 06 Sep '19

06 Sep '19

Ran Bi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35150 ) Change subject: soc/mediatek: Fix USB enumeration issue ...................................................................... soc/mediatek: Fix USB enumeration issue Some USB3.0 devices are failed to enumerate after USB reset, and xhci port status register show device is disconnected. After measure USB signal, we can find usb disconnect threshold is lower and disconnect event is triggered unexpectedly. USB designer suggest to change discth to 15. BUG=b:122047652 TEST=emerge-kukui coreboot chromeos-bootimage Change-Id: I0e8556035b49d693a42cbe1099a6882a1c0ed0d1 Signed-off-by: Changqi Hu <changqi.hu(a)mediatek.com> --- M src/soc/mediatek/common/include/soc/usb_common.h M src/soc/mediatek/common/usb.c 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/35150/1 diff --git a/src/soc/mediatek/common/include/soc/usb_common.h b/src/soc/mediatek/common/include/soc/usb_common.h old mode 100644 new mode 100755 index 8a36c6a..22704e7 --- a/src/soc/mediatek/common/include/soc/usb_common.h +++ b/src/soc/mediatek/common/include/soc/usb_common.h @@ -70,6 +70,8 @@ #define PA6_RG_U2_ISO_EN (0x1 << 31) #define PA6_RG_U2_BC11_SW_EN (0x1 << 23) #define PA6_RG_U2_OTG_VBUSCMP_EN (0x1 << 20) +#define PA6_RG_U2_DISCTH (0xf << 4) +#define PA6_RG_U2_DISCTH_VAL(x) ((0xf & (x)) << 4) #define PA6_RG_U2_SQTH (0xf << 0) #define PA6_RG_U2_SQTH_VAL(x) ((0xf & (x)) << 0) diff --git a/src/soc/mediatek/common/usb.c b/src/soc/mediatek/common/usb.c old mode 100644 new mode 100755 index dcb9307..f5263fb --- a/src/soc/mediatek/common/usb.c +++ b/src/soc/mediatek/common/usb.c @@ -76,6 +76,10 @@ /* Set USB 2.0 slew rate value */ clrsetbits_le32(&phy->u2phy.usbphyacr5, PA5_RG_U2_HSTX_SRCTRL, PA5_RG_U2_HSTX_SRCTRL_VAL(4)); + + /*Set USB 2.0 disconnect threshold*/ + clrsetbits_le32(&phy->u2phy.usbphyacr6, + PA6_RG_U2_DISCTH, PA6_RG_U2_DISCTH_VAL(15)); } static void u3phy_power_on(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/35150 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e8556035b49d693a42cbe1099a6882a1c0ed0d1 Gerrit-Change-Number: 35150 Gerrit-PatchSet: 1 Gerrit-Owner: Ran Bi <ran.bi(a)mediatek.com> Gerrit-MessageType: newchange

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