coreboot-gerrit August 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: arch/x86: Cache the TSEG region at the top of ram
by Subrata Banik (Code Review) 11 Sep '19

11 Sep '19

Hello Kyösti Mälkki, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/34995 to review the following change. Change subject: arch/x86: Cache the TSEG region at the top of ram ...................................................................... arch/x86: Cache the TSEG region at the top of ram This patch helps to save additional ~6ms of booting time in normal and s3 resume on CML-hatch. Change-Id: I59432c02e04af1b931d77de3f6652b0327ca82bb Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/arch/x86/postcar_loader.c 1 file changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/34995/1 diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index bceed6c..408d155 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -20,6 +20,7 @@ #include <cpu/cpu.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/smm.h> #include <program_loading.h> #include <rmodule.h> #include <romstage_handoff.h> @@ -149,6 +150,23 @@ set_var_mtrr(mtrr, base, size, MTRR_TYPE_WRPROT); } +/* + * Cache the TSEG region at the top of ram. This region is + * not restricted to SMM mode until SMM has been relocated. + * By setting the region to cacheable it provides faster access + * when relocating the SMM handler as well as using the TSEG + * region for other purposes. + */ +static void enable_tseg_cache(struct postcar_frame *pcf) +{ + uintptr_t smm_base; + size_t smm_size; + + smm_region(&smm_base, &smm_size); + postcar_frame_add_mtrr(pcf, smm_base, smm_size, + MTRR_TYPE_WRBACK); +} + void postcar_frame_setup_top_of_dram_usage(struct postcar_frame *pcf, uintptr_t addr, size_t size, int type) { @@ -159,6 +177,9 @@ */ if (!acpi_is_wakeup_s3()) enable_top_of_dram_cache(addr, size); + + enable_tseg_cache(pcf); + postcar_frame_add_mtrr(pcf, addr, size, type); } -- To view, visit https://review.coreboot.org/c/coreboot/+/34995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I59432c02e04af1b931d77de3f6652b0327ca82bb Gerrit-Change-Number: 34995 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/asrock/h110m: Add STX variant
by Maxim Polyakov (Code Review) 11 Sep '19

11 Sep '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34904 ) Change subject: mb/asrock/h110m: Add STX variant ...................................................................... mb/asrock/h110m: Add STX variant Change-Id: If95c7ec78b8bee10ed7ae761754ba7f7d548aa55 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/asrock/h110m/Kconfig M src/mainboard/asrock/h110m/Kconfig.name M src/mainboard/asrock/h110m/Makefile.inc M src/mainboard/asrock/h110m/bootblock.c M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/asrock/h110m/include/gpio.h M src/mainboard/asrock/h110m/ramstage.c A src/mainboard/asrock/h110m/variants/dvs/gpio.c R src/mainboard/asrock/h110m/variants/dvs/hda_verb.c A src/mainboard/asrock/h110m/variants/dvs/overridetree.cb A src/mainboard/asrock/h110m/variants/stx/gpio.c A src/mainboard/asrock/h110m/variants/stx/hda_verb.c A src/mainboard/asrock/h110m/variants/stx/overridetree.cb 13 files changed, 979 insertions(+), 440 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/34904/1 diff --git a/src/mainboard/asrock/h110m/Kconfig b/src/mainboard/asrock/h110m/Kconfig index eebce57..1b4e263 100644 --- a/src/mainboard/asrock/h110m/Kconfig +++ b/src/mainboard/asrock/h110m/Kconfig @@ -1,4 +1,4 @@ -if BOARD_ASROCK_H110M_DVS +if BOARD_ASROCK_H110M_DVS || BOARD_ASROCK_H110M_STX config BOARD_SPECIFIC_OPTIONS def_bool y @@ -11,11 +11,13 @@ select INTEL_INT15 select SOC_INTEL_KABYLAKE select SKYLAKE_SOC_PCH_H + select MAINBOARD_USES_FSP2_0 select GENERIC_SPD_BIN - select SUPERIO_NUVOTON_NCT6791D - select SUPERIO_NUVOTON_NCT6791D_COM_A - select REALTEK_8168_RESET - select RT8168_SET_LED_MODE + select MAINBOARD_USES_IFD_GBE_REGION if BOARD_ASROCK_H110M_STX + select SUPERIO_NUVOTON_NCT6791D if BOARD_ASROCK_H110M_DVS + select SUPERIO_NUVOTON_NCT6791D_COM_A if BOARD_ASROCK_H110M_DVS + select REALTEK_8168_RESET if BOARD_ASROCK_H110M_DVS + select RT8168_SET_LED_MODE if BOARD_ASROCK_H110M_DVS config IRQ_SLOT_COUNT int @@ -25,9 +27,15 @@ string default "asrock/h110m" +config VARIANT_DIR + string + default "dvs" if BOARD_ASROCK_H110M_DVS + default "stx" if BOARD_ASROCK_H110M_STX + config MAINBOARD_PART_NUMBER string - default "H110M" + default "H110M-DVS" if BOARD_ASROCK_H110M_DVS + default "H110M-STX" if BOARD_ASROCK_H110M_STX config MAX_CPUS int @@ -37,6 +45,10 @@ string default "devicetree.cb" +config OVERRIDE_DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" + config PRERAM_CBMEM_CONSOLE_SIZE hex default 0xd00 diff --git a/src/mainboard/asrock/h110m/Kconfig.name b/src/mainboard/asrock/h110m/Kconfig.name index 34c1a3c..c871b62 100644 --- a/src/mainboard/asrock/h110m/Kconfig.name +++ b/src/mainboard/asrock/h110m/Kconfig.name @@ -1,2 +1,5 @@ config BOARD_ASROCK_H110M_DVS bool "H110M-DVS" + +config BOARD_ASROCK_H110M_STX + bool "H110M-STX" diff --git a/src/mainboard/asrock/h110m/Makefile.inc b/src/mainboard/asrock/h110m/Makefile.inc index ce6cf80..be9995e 100644 --- a/src/mainboard/asrock/h110m/Makefile.inc +++ b/src/mainboard/asrock/h110m/Makefile.inc @@ -16,8 +16,10 @@ subdirs-y += spd bootblock-y += bootblock.c +bootblock-y += variants/$(VARIANT_DIR)/gpio.c ramstage-y += mainboard.c ramstage-y += ramstage.c -ramstage-y += hda_verb.c +ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c +ramstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asrock/h110m/bootblock.c b/src/mainboard/asrock/h110m/bootblock.c index 96ce205..d520996 100644 --- a/src/mainboard/asrock/h110m/bootblock.c +++ b/src/mainboard/asrock/h110m/bootblock.c @@ -16,22 +16,28 @@ #include <bootblock_common.h> #include <soc/gpio.h> -#include <superio/nuvoton/common/nuvoton.h> -#include <superio/nuvoton/nct6791d/nct6791d.h> #include "include/gpio.h" +#include <superio/nuvoton/nct6791d/nct6791d.h> +#include <superio/nuvoton/common/nuvoton.h> static void early_config_superio(void) { - const pnp_devfn_t serial_dev = PNP_DEV(0x2e, NCT6791D_SP1); - nuvoton_enable_serial(serial_dev, CONFIG_TTYS0_BASE); + if (CONFIG(BOARD_ASROCK_H110M_DVS)) { + const pnp_devfn_t serial_dev = PNP_DEV(0x2e, NCT6791D_SP1); + nuvoton_enable_serial(serial_dev, CONFIG_TTYS0_BASE); + } } static void early_config_gpio(void) { + const struct pad_config *pads; + size_t size; + /* This is a hack for FSP because it does things in MemoryInit() * which it shouldn't do. We have to prepare certain gpios here * because of the brokenness in FSP. */ - gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); + pads = get_early_gpio_table(&size); + gpio_configure_pads(pads, size); } void bootblock_mainboard_init(void) diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 3067ffe..9942233 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -145,119 +145,9 @@ }" register "EnableLan" = "0" - register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V register "PmTimerDisabled" = "0" - # USB - register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[2]" = "USB2_PORT_MID(OC4)" - register "usb2_ports[3]" = "USB2_PORT_MID(OC4)" - register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" - register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" - register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[8]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[10]" = "USB2_PORT_MID(OC1)" - register "usb2_ports[11]" = "USB2_PORT_MID(OC1)" - register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)" - register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" - register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)" - register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)" - register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)" - register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)" - - # SATA - register "EnableSata" = "1" - register "SataSalpSupport" = "1" - register "SataPortsEnable" = "{ \ - [0] = 1, \ - [1] = 1, \ - [2] = 1, \ - [3] = 1, \ - [4] = 1, \ - [5] = 1, \ - [6] = 1, \ - [7] = 1, \ - }" - - # PCH UART, SPI, I2C - register "SerialIoDevMode" = "{ \ - [PchSerialIoIndexI2C0] = PchSerialIoPci, \ - [PchSerialIoIndexI2C1] = PchSerialIoPci, \ - [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ - [PchSerialIoIndexSpi0] = PchSerialIoPci, \ - [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart0] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ - }" - - # Set params for PEG 0:1:0 - register "Peg0MaxLinkWidth" = "Peg0_x16" - # Configure PCIe clockgen in PCH - # PEG0 uses SRCCLKREQ0 and CLKSRC0 - register "PcieRpClkReqSupport[0]" = "1" - register "PcieRpClkReqNumber[0]" = "0" - register "PcieRpClkSrcNumber[0]" = "0" - - # Enable Root port 6(x1) for LAN. - register "PcieRpEnable[5]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[5]" = "1" - # Use SRCCLKREQ1# - register "PcieRpClkReqNumber[5]" = "1" - # Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[5]" = "1" - # Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[5]" = "1" - # Use CLK SRC 1 - register "PcieRpClkSrcNumber[5]" = "1" - - # Enable Root port 5 (x1) for PCIE slot. - register "PcieRpEnable[4]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[4]" = "1" - # Use SRCCLKREQ2# - register "PcieRpClkReqNumber[4]" = "2" - # Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[4]" = "1" - # Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[4]" = "1" - # Use CLK SRC 2 - register "PcieRpClkSrcNumber[4]" = "2" - # Use Hot Plug subsystem - register "PcieRpHotPlug[4]" = "1" - - # Enable Root port 7(x1) for PCIE slot. - register "PcieRpEnable[6]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[6]" = "1" - # Use SRCCLKREQ3# - register "PcieRpClkReqNumber[6]" = "3" - # Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[6]" = "1" - # Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[6]" = "1" - # Use CLK SRC 3 - register "PcieRpClkSrcNumber[6]" = "3" - # Use Hot Plug subsystem - register "PcieRpHotPlug[6]" = "1" - - # PL2 override 91W - register "tdp_pl2_override" = "91" - # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" @@ -298,13 +188,13 @@ device pci 19.0 off end # UART #2 device pci 19.1 off end # I2C #5 device pci 19.2 off end # I2C #4 - device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.0 off end # PCI Express Port 1 device pci 1c.1 off end # PCI Express Port 2 device pci 1c.2 off end # PCI Express Port 3 device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 on end # PCI Express Port 5 - device pci 1c.5 on end # PCI Express Port 6 - device pci 1c.6 on end # PCI Express Port 7 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 device pci 1d.0 off end # PCI Express Port 9 device pci 1d.1 off end # PCI Express Port 10 @@ -317,70 +207,7 @@ device pci 1e.4 off end # eMMC device pci 1e.5 off end # SDIO device pci 1e.6 off end # SDCard - device pci 1f.0 on # LPC bridge - subsystemid 0x1849 0x1a43 - chip superio/nuvoton/nct6791d - device pnp 2e.0 off end # Floppy - device pnp 2e.1 on # Parallel - # global - irq 0x1c = 0x10 - irq 0x27 = 0x10 - irq 0x2a = 0x64 - # parallel port - io 0x60 = 0x0378 - irq 0x70 = 7 - drq 0x74 = 4 # No DMA - irq 0xf0 = 0x3c # Printer mode - end - device pnp 2e.2 on # UART A - io 0x60 = 0x03f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # IR - io 0x60 = 0x02f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 KBC - io 0x60 = 0x0060 - io 0x62 = 0x0064 - irq 0x70 = 1 # Keyboard - irq 0x72 = 12 # Mouse - end - device pnp 2e.6 off end # CIR - device pnp 2e.7 off end # GPIO6 - device pnp 2e.107 off end # GPIO7 - device pnp 2e.207 off end # GPIO8 - device pnp 2e.8 off end # WDT - device pnp 2e.108 off end # GPIO0 - device pnp 2e.308 off end # GPIO base - device pnp 2e.408 off end # WDTMEM - device pnp 2e.708 off end # GPIO1 - device pnp 2e.9 off end # GPIO2 - device pnp 2e.109 off end # GPIO3 - device pnp 2e.209 off end # GPIO4 - device pnp 2e.309 off end # GPIO5 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HWM, LED - io 0x60 = 0x0290 - io 0x62 = 0 - irq 0x70 = 0 - end - device pnp 2e.d off end # BCLK, WDT2, WDT_MEM - device pnp 2e.e off end # CIR wake-up - device pnp 2e.f off end # GPIO PP/OD - device pnp 2e.14 off end # SVID, Port 80 UART - device pnp 2e.16 off end # DS5 - device pnp 2e.116 off end # DS3 - device pnp 2e.316 off end # PCHDSW - device pnp 2e.416 off end # DSWWOPT - device pnp 2e.516 off end # DS3OPT - device pnp 2e.616 off end # DSDSS - device pnp 2e.716 off end # DSPU - end # superio/nuvoton/nct6791d - chip drivers/pc80/tpm - device pnp 4e.0 on end # TPM module - end - end # LPC Interface + device pci 1f.0 on end # Chipset LPC/eSPI Controller device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller device pci 1f.3 on end # Intel HDA diff --git a/src/mainboard/asrock/h110m/include/gpio.h b/src/mainboard/asrock/h110m/include/gpio.h index 4ae9911..4cabfc5 100644 --- a/src/mainboard/asrock/h110m/include/gpio.h +++ b/src/mainboard/asrock/h110m/include/gpio.h @@ -13,260 +13,16 @@ * GNU General Public License for more details. */ -#ifndef _GPIO_DVS_H -#define _GPIO_DVS_H +#ifndef _PCH_GPIO_H +#define _PCH_GPIO_H #include <soc/gpe.h> #include <soc/gpio.h> -#define H110_PAD_DW0_DW1_CFG(val, config0, config1) \ +#define PCH_PAD_CFG(val, config0, config1) \ _PAD_CFG_STRUCT(val, config0, config1) -/* Pad configuration in ramstage. */ -static const struct pad_config gpio_table[] = { - /* GPIO Group GPP_A */ - H110_PAD_DW0_DW1_CFG(GPP_A0, 0x84000502, 0x00000018), /* RCIN# */ - H110_PAD_DW0_DW1_CFG(GPP_A1, 0x84000402, 0x00003019), /* LAD0 */ - H110_PAD_DW0_DW1_CFG(GPP_A2, 0x84000402, 0x0000301a), /* LAD1 */ - H110_PAD_DW0_DW1_CFG(GPP_A3, 0x84000402, 0x0000301b), /* LAD2 */ - H110_PAD_DW0_DW1_CFG(GPP_A4, 0x84000402, 0x0000301c), /* LAD3 */ - H110_PAD_DW0_DW1_CFG(GPP_A5, 0x84000600, 0x0000001d), /* LFRAME# */ - H110_PAD_DW0_DW1_CFG(GPP_A6, 0x84000402, 0x0000001e), /* SERIRQ */ - H110_PAD_DW0_DW1_CFG(GPP_A7, 0x84000102, 0x0000001f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A8, 0x84000500, 0x00000020), /* CLKRUN# */ - H110_PAD_DW0_DW1_CFG(GPP_A9, 0x84000600, 0x00001021), /* CLKOUT_LPC0 */ - H110_PAD_DW0_DW1_CFG(GPP_A10, 0x84000600, 0x00001022), /* CLKOUT_LPC1 */ - H110_PAD_DW0_DW1_CFG(GPP_A11, 0x84000102, 0x00000023), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A12, 0x84000102, 0x00000024), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A13, 0x44000600, 0x00000025), /* SUSWARN# */ - H110_PAD_DW0_DW1_CFG(GPP_A14, 0x44000600, 0x00000026), /* SUS_STAT# */ - H110_PAD_DW0_DW1_CFG(GPP_A15, 0x44000502, 0x00003027), /* SUS_ACK# */ - H110_PAD_DW0_DW1_CFG(GPP_A16, 0x84000102, 0x00000028), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A17, 0x84000102, 0x00000029), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A18, 0x84000102, 0x0000002a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A19, 0x84000102, 0x0000002b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A20, 0x84000100, 0x0000002c), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A21, 0x84000102, 0x0000002d), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A22, 0x84000102, 0x0000002e), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A23, 0x84000102, 0x0000002f), /* GPIO */ - /* GPIO Group GPP_B */ - H110_PAD_DW0_DW1_CFG(GPP_B0, 0x84000100, 0x00000030), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B1, 0x84000100, 0x00000031), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B2, 0x84000102, 0x00000032), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B3, 0x44000201, 0x00000033), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B4, 0x84000502, 0x00000034), /* CPU_GP3 */ - H110_PAD_DW0_DW1_CFG(GPP_B5, 0x84000102, 0x00000035), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B6, 0x84000102, 0x00000036), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B7, 0x44000300, 0x00000037), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B8, 0x84000102, 0x00002838), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B9, 0x84000100, 0x00000039), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B10, 0x84000102, 0x0000003a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B11, 0x04000000, 0x0000003b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B12, 0x44000600, 0x0000003c), /* SLP_S0# */ - H110_PAD_DW0_DW1_CFG(GPP_B13, 0x44000600, 0x0000003d), /* PLTRST# */ - H110_PAD_DW0_DW1_CFG(GPP_B14, 0x84000600, 0x0000103e), /* SPKR */ - H110_PAD_DW0_DW1_CFG(GPP_B15, 0x84000102, 0x0000003f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B16, 0x84000102, 0x00000040), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B17, 0x44000201, 0x00000041), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B18, 0x84000100, 0x00000042), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B19, 0x84000102, 0x00000043), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B20, 0x84000102, 0x00000044), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B21, 0x84000102, 0x00000045), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B22, 0x84000100, 0x00000046), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B23, 0x84000a01, 0x00001047), /* PCHHOT# */ - /* GPIO Group GPP_C */ - H110_PAD_DW0_DW1_CFG(GPP_C0, 0x44000502, 0x00000048), /* SMBCLK */ - H110_PAD_DW0_DW1_CFG(GPP_C1, 0x44000502, 0x00000049), /* SMBDATA */ - H110_PAD_DW0_DW1_CFG(GPP_C2, 0x44000201, 0x0000004a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C3, 0x44000502, 0x0000004b), /* SML0CLK */ - H110_PAD_DW0_DW1_CFG(GPP_C4, 0x44000502, 0x0000004c), /* SML0DATA */ - H110_PAD_DW0_DW1_CFG(GPP_C5, 0x84000100, 0x0000004d), /* GPIO */ - /* GPP_C6 - RESERVED */ - /* GPP_C7 - RESERVED */ - H110_PAD_DW0_DW1_CFG(GPP_C8, 0x84000502, 0x00000050), /* UART0_RXD */ - H110_PAD_DW0_DW1_CFG(GPP_C9, 0x84000600, 0x00000051), /* UART0_TXD */ - H110_PAD_DW0_DW1_CFG(GPP_C10, 0x84000600, 0x00000052), /* UART0_RTS# */ - H110_PAD_DW0_DW1_CFG(GPP_C11, 0x84000502, 0x00000053), /* UART0_CTS# */ - H110_PAD_DW0_DW1_CFG(GPP_C12, 0x84000102, 0x00000054), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C13, 0x84000102, 0x00000055), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C14, 0x84000102, 0x00000056), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C15, 0x84000102, 0x00000057), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C16, 0x84000102, 0x00000058), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C17, 0x84000102, 0x00000059), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C18, 0x84000102, 0x0000005a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C19, 0x84000102, 0x0000005b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C20, 0x84000502, 0x0000005c), /* UART2_RXD */ - H110_PAD_DW0_DW1_CFG(GPP_C21, 0x84000600, 0x0000005d), /* UART2_TXD */ - H110_PAD_DW0_DW1_CFG(GPP_C22, 0x84000600, 0x0000005e), /* UART2_RTS# */ - H110_PAD_DW0_DW1_CFG(GPP_C23, 0x40880102, 0x0000005f), /* GPIO */ - /* GPIO Group GPP_D */ - H110_PAD_DW0_DW1_CFG(GPP_D0, 0x84000102, 0x00000060), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D1, 0x84000102, 0x00000061), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D2, 0x84000102, 0x00000062), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D3, 0x84000102, 0x00000063), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D4, 0x84000102, 0x00000064), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D5, 0x84000402, 0x00000065), /* I2S_SFRM */ - H110_PAD_DW0_DW1_CFG(GPP_D6, 0x84000600, 0x00000066), /* I2S_TXD */ - H110_PAD_DW0_DW1_CFG(GPP_D7, 0x84000502, 0x00000067), /* I2S_RXD */ - H110_PAD_DW0_DW1_CFG(GPP_D8, 0x84000402, 0x00000068), /* I2S_SCLK */ - H110_PAD_DW0_DW1_CFG(GPP_D9, 0x84000102, 0x00000069), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D10, 0x84000102, 0x0000006a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D11, 0x84000102, 0x0000006b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D12, 0x84000102, 0x0000006c), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D13, 0x84000102, 0x0000006d), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D14, 0x84000100, 0x0000006e), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D15, 0x84000100, 0x0000006f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D16, 0x84000102, 0x00000070), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D17, 0x84000102, 0x00000071), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D18, 0x84000102, 0x00000072), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D19, 0x84000500, 0x00003073), /* DMIC_CLK0 */ - H110_PAD_DW0_DW1_CFG(GPP_D20, 0x84000500, 0x00003074), /* DMIC_DATA0 */ - H110_PAD_DW0_DW1_CFG(GPP_D21, 0x84000102, 0x00000075), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D22, 0x84000102, 0x00000076), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D23, 0x84000102, 0x00000077), /* GPIO */ - /* GPIO Group GPP_E */ - H110_PAD_DW0_DW1_CFG(GPP_E0, 0x84000502, 0x00003018), /* SATAXPCIE0 */ - H110_PAD_DW0_DW1_CFG(GPP_E1, 0x84000502, 0x00003019), /* SATAXPCIE1 */ - H110_PAD_DW0_DW1_CFG(GPP_E2, 0x84000502, 0x0000301a), /* SATAXPCIE2 */ - H110_PAD_DW0_DW1_CFG(GPP_E3, 0x84000500, 0x0000001b), /* CPU_GP0 */ - /* SATA_DEVSLP0 */ - H110_PAD_DW0_DW1_CFG(GPP_E4, 0x84000500, 0x0000001c), - /* SATA_DEVSLP1 */ - H110_PAD_DW0_DW1_CFG(GPP_E5, 0x84000500, 0x0000001d), - /* SATA_DEVSLP2 */ - H110_PAD_DW0_DW1_CFG(GPP_E6, 0x84000500, 0x0000001e), - H110_PAD_DW0_DW1_CFG(GPP_E7, 0x84000102, 0x0000001f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_E8, 0x84000600, 0x00000020), /* SATA_LED# */ - H110_PAD_DW0_DW1_CFG(GPP_E9, 0x44000502, 0x00000021), /* USB_OC0# */ - H110_PAD_DW0_DW1_CFG(GPP_E10, 0x44000502, 0x00000022), /* USB_OC1# */ - H110_PAD_DW0_DW1_CFG(GPP_E11, 0x44000502, 0x00000023), /* USB_OC2# */ - H110_PAD_DW0_DW1_CFG(GPP_E12, 0x44000502, 0x00000024), /* USB_OC3# */ - /* GPIO Group GPP_F */ - H110_PAD_DW0_DW1_CFG(GPP_F0, 0x84000102, 0x00000025), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F1, 0x84000502, 0x00003026), /* SATAXPCIE4 */ - H110_PAD_DW0_DW1_CFG(GPP_F2, 0x44000300, 0x00000027), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F3, 0x84000102, 0x00000028), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F4, 0x84000102, 0x00000029), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F5, 0x84000102, 0x0000002a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F6, 0x84000102, 0x0000002b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F7, 0x84000102, 0x0000002c), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F8, 0x84000102, 0x0000002d), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F9, 0x84000102, 0x0000002e), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F10, 0x80100102, 0x0000002f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F11, 0x84000102, 0x00000030), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F12, 0x80900102, 0x00000031), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F13, 0x80100102, 0x00000032), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F14, 0x40900102, 0x00000033), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F15, 0x44000502, 0x00000034), /* USB_OC4# */ - H110_PAD_DW0_DW1_CFG(GPP_F16, 0x44000502, 0x00000035), /* USB_OC5# */ - H110_PAD_DW0_DW1_CFG(GPP_F17, 0x44000502, 0x00000036), /* USB_OC6# */ - H110_PAD_DW0_DW1_CFG(GPP_F18, 0x84000201, 0x00000037), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F19, 0x84000100, 0x00000038), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F20, 0x84000102, 0x00000039), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F21, 0x84000102, 0x0000003a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F22, 0x84000102, 0x0000003b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F23, 0x84000102, 0x0000003c), /* GPIO */ - /* GPIO Group GPP_G */ - H110_PAD_DW0_DW1_CFG(GPP_G0, 0xc4000102, 0x0000003d), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G1, 0xc4000102, 0x0000003e), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G2, 0xc4000100, 0x0000003f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G3, 0xc4000100, 0x00000040), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G4, 0x44000200, 0x00000041), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G5, 0xc4000102, 0x00000042), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G6, 0xc0800102, 0x00000043), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G7, 0xc4000102, 0x00000044), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G8, 0x84000100, 0x00000045), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G9, 0x84000100, 0x00000046), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G10, 0x84000102, 0x00000047), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G11, 0x84000100, 0x00000048), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G12, 0x80800102, 0x00000049), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G13, 0x84000201, 0x0000004a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G14, 0x80800102, 0x0000004b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G15, 0x84000200, 0x0000004c), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G16, 0x84000201, 0x0000104d), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G17, 0x84000102, 0x0000004e), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G18, 0x80100102, 0x0000004f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G19, 0x84000500, 0x00000050), /* SMI# */ - H110_PAD_DW0_DW1_CFG(GPP_G20, 0x84000102, 0x00000051), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G21, 0x84000102, 0x00000052), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G22, 0x84000102, 0x00000053), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G23, 0x84000102, 0x00000054), /* GPIO */ - /* GPIO Group GPP_H */ - H110_PAD_DW0_DW1_CFG(GPP_H0, 0x84000102, 0x00000055), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H1, 0x44000300, 0x00000056), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H2, 0x84000102, 0x00000057), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H3, 0x84000102, 0x00000058), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H4, 0x84000102, 0x00000059), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H5, 0x84000102, 0x0000005a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H6, 0x84000102, 0x0000005b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H7, 0x84000102, 0x0000005c), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H8, 0x84000100, 0x0000005d), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H9, 0x84000102, 0x0000005e), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H10, 0x84000102, 0x0000005f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H11, 0x84000102, 0x00000060), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H12, 0x84000100, 0x00000061), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H13, 0x80100102, 0x00000062), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H14, 0x80100102, 0x00000063), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H15, 0x80100100, 0x00000064), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H16, 0x80000102, 0x00000065), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H17, 0x84000201, 0x00000066), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H18, 0x84000102, 0x00000067), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H19, 0x84000102, 0x00000068), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H20, 0x84000102, 0x00000069), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H21, 0x84000102, 0x0000006a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H22, 0x84000102, 0x0000006b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H23, 0x04000100, 0x0000006c), /* GPIO */ - /* GPIO Group GPD */ - H110_PAD_DW0_DW1_CFG(GPD0, 0x84000102, 0x00000018), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPD1, 0x04000200, 0x00000019), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPD2, 0x00000602, 0x00003c1a), /* LAN_WAKE# */ - H110_PAD_DW0_DW1_CFG(GPD3, 0x04000502, 0x0000301b), /* PWRBTN# */ - H110_PAD_DW0_DW1_CFG(GPD4, 0x04000600, 0x0000001c), /* SLP_S3# */ - H110_PAD_DW0_DW1_CFG(GPD5, 0x04000600, 0x0000001d), /* SLP_S4# */ - H110_PAD_DW0_DW1_CFG(GPD6, 0x84000102, 0x0000001e), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPD7, 0x84000103, 0x0000001f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPD8, 0x04000600, 0x00000020), /* SUSCLK */ - H110_PAD_DW0_DW1_CFG(GPD9, 0x04000600, 0x00000021), /* SLP_WLAN# */ - H110_PAD_DW0_DW1_CFG(GPD10, 0x04000600, 0x00000022), /* SLP_S5# */ - H110_PAD_DW0_DW1_CFG(GPD11, 0x04000200, 0x00000023), /* GPIO */ - /* GPIO Group GPP_I */ - H110_PAD_DW0_DW1_CFG(GPP_I0, 0x84000502, 0x0000006d), /* DDPB_HPD0 */ - H110_PAD_DW0_DW1_CFG(GPP_I1, 0x84000502, 0x0000006e), /* DDPC_HPD1 */ - H110_PAD_DW0_DW1_CFG(GPP_I2, 0x84000500, 0x0000006f), /* DDPD_HPD2 */ - H110_PAD_DW0_DW1_CFG(GPP_I3, 0x84000502, 0x00000070), /* DDPE_HPD3 */ - H110_PAD_DW0_DW1_CFG(GPP_I4, 0x84000100, 0x00000071), /* GPIO */ - /* DDPB_CTRLCLK */ - H110_PAD_DW0_DW1_CFG(GPP_I5, 0x84000500, 0x00000072), - /* DDPB_CTRLDATA */ - H110_PAD_DW0_DW1_CFG(GPP_I6, 0x84000500, 0x00001073), - /* DDPC_CTRLCLK */ - H110_PAD_DW0_DW1_CFG(GPP_I7, 0x84000500, 0x00000074), - /* DDPC_CTRLDATA */ - H110_PAD_DW0_DW1_CFG(GPP_I8, 0x84000500, 0x00001075), - /* DDPD_CTRLCLK */ - H110_PAD_DW0_DW1_CFG(GPP_I9, 0x84000500, 0x00000076), - /* DDPD_CTRLDATA */ - H110_PAD_DW0_DW1_CFG(GPP_I10, 0x84000500, 0x00001077), -}; - -/* Early pad configuration in romstage. */ -static const struct pad_config early_gpio_table[] = { - /* GPIO Group GPP_A */ - H110_PAD_DW0_DW1_CFG(GPP_A0, 0x84000502, 0x00000018), /* RCIN# */ - H110_PAD_DW0_DW1_CFG(GPP_A1, 0x84000402, 0x00003019), /* LAD0 */ - H110_PAD_DW0_DW1_CFG(GPP_A2, 0x84000402, 0x0000301a), /* LAD1 */ - H110_PAD_DW0_DW1_CFG(GPP_A3, 0x84000402, 0x0000301b), /* LAD2 */ - H110_PAD_DW0_DW1_CFG(GPP_A4, 0x84000402, 0x0000301c), /* LAD3 */ - H110_PAD_DW0_DW1_CFG(GPP_A5, 0x84000600, 0x0000001d), /* LFRAME# */ - H110_PAD_DW0_DW1_CFG(GPP_A6, 0x84000402, 0x0000001e), /* SERIRQ */ - H110_PAD_DW0_DW1_CFG(GPP_A8, 0x84000500, 0x00000020), /* CLKRUN# */ - H110_PAD_DW0_DW1_CFG(GPP_A9, 0x84000600, 0x00001021), /* CLKOUT_LPC0 */ - H110_PAD_DW0_DW1_CFG(GPP_A10, 0x84000600, 0x00001022), /* CLKOUT_LPC1 */ - /* ---- */ - /* SUSWARN#/SUSPWRDNACK */ - H110_PAD_DW0_DW1_CFG(GPP_A13, 0x44000600, 0x00000025), - H110_PAD_DW0_DW1_CFG(GPP_A14, 0x44000600, 0x00000026), /* SUS_STAT# */ - H110_PAD_DW0_DW1_CFG(GPP_A15, 0x44000502, 0x00003027), /* SUS_ACK# */ -}; +const struct pad_config *get_gpio_table(size_t *num); +const struct pad_config *get_early_gpio_table(size_t *num); #endif diff --git a/src/mainboard/asrock/h110m/ramstage.c b/src/mainboard/asrock/h110m/ramstage.c index c93e84c..eab6290 100644 --- a/src/mainboard/asrock/h110m/ramstage.c +++ b/src/mainboard/asrock/h110m/ramstage.c @@ -19,9 +19,12 @@ void mainboard_silicon_init_params(FSP_SIL_UPD *params) { + const struct pad_config *pads; + size_t size; /* Configure pads prior to SiliconInit() in case there's any * dependencies during hardware initialization. */ - gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + pads = get_gpio_table(&size); + gpio_configure_pads(pads, size); params->CdClock = 3; /* Enable Virtual Channel 1 */ diff --git a/src/mainboard/asrock/h110m/variants/dvs/gpio.c b/src/mainboard/asrock/h110m/variants/dvs/gpio.c new file mode 100644 index 0000000..f695d0e --- /dev/null +++ b/src/mainboard/asrock/h110m/variants/dvs/gpio.c @@ -0,0 +1,266 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Maxim Polyakov <max.senia.poliak(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <commonlib/helpers.h> +#include "../../include/gpio.h" + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { + /* GPIO Group GPP_A */ + PCH_PAD_CFG(GPP_A0, 0x84000502, 0x00000018), /* RCIN# */ + PCH_PAD_CFG(GPP_A1, 0x84000402, 0x00003019), /* LAD0 */ + PCH_PAD_CFG(GPP_A2, 0x84000402, 0x0000301a), /* LAD1 */ + PCH_PAD_CFG(GPP_A3, 0x84000402, 0x0000301b), /* LAD2 */ + PCH_PAD_CFG(GPP_A4, 0x84000402, 0x0000301c), /* LAD3 */ + PCH_PAD_CFG(GPP_A5, 0x84000600, 0x0000001d), /* LFRAME# */ + PCH_PAD_CFG(GPP_A6, 0x84000402, 0x0000001e), /* SERIRQ */ + PCH_PAD_CFG(GPP_A7, 0x84000102, 0x0000001f), /* GPIO */ + PCH_PAD_CFG(GPP_A8, 0x84000500, 0x00000020), /* CLKRUN# */ + PCH_PAD_CFG(GPP_A9, 0x84000600, 0x00001021), /* CLKOUT_LPC0 */ + PCH_PAD_CFG(GPP_A10, 0x84000600, 0x00001022), /* CLKOUT_LPC1 */ + PCH_PAD_CFG(GPP_A11, 0x84000102, 0x00000023), /* GPIO */ + PCH_PAD_CFG(GPP_A12, 0x84000102, 0x00000024), /* GPIO */ + PCH_PAD_CFG(GPP_A13, 0x44000600, 0x00000025), /* SUSWARN# */ + PCH_PAD_CFG(GPP_A14, 0x44000600, 0x00000026), /* SUS_STAT# */ + PCH_PAD_CFG(GPP_A15, 0x44000502, 0x00003027), /* SUS_ACK# */ + PCH_PAD_CFG(GPP_A16, 0x84000102, 0x00000028), /* GPIO */ + PCH_PAD_CFG(GPP_A17, 0x84000102, 0x00000029), /* GPIO */ + PCH_PAD_CFG(GPP_A18, 0x84000102, 0x0000002a), /* GPIO */ + PCH_PAD_CFG(GPP_A19, 0x84000102, 0x0000002b), /* GPIO */ + PCH_PAD_CFG(GPP_A20, 0x84000100, 0x0000002c), /* GPIO */ + PCH_PAD_CFG(GPP_A21, 0x84000102, 0x0000002d), /* GPIO */ + PCH_PAD_CFG(GPP_A22, 0x84000102, 0x0000002e), /* GPIO */ + PCH_PAD_CFG(GPP_A23, 0x84000102, 0x0000002f), /* GPIO */ + /* GPIO Group GPP_B */ + PCH_PAD_CFG(GPP_B0, 0x84000100, 0x00000030), /* GPIO */ + PCH_PAD_CFG(GPP_B1, 0x84000100, 0x00000031), /* GPIO */ + PCH_PAD_CFG(GPP_B2, 0x84000102, 0x00000032), /* GPIO */ + PCH_PAD_CFG(GPP_B3, 0x44000201, 0x00000033), /* GPIO */ + PCH_PAD_CFG(GPP_B4, 0x84000502, 0x00000034), /* CPU_GP3 */ + PCH_PAD_CFG(GPP_B5, 0x84000102, 0x00000035), /* GPIO */ + PCH_PAD_CFG(GPP_B6, 0x84000102, 0x00000036), /* GPIO */ + PCH_PAD_CFG(GPP_B7, 0x44000300, 0x00000037), /* GPIO */ + PCH_PAD_CFG(GPP_B8, 0x84000102, 0x00002838), /* GPIO */ + PCH_PAD_CFG(GPP_B9, 0x84000100, 0x00000039), /* GPIO */ + PCH_PAD_CFG(GPP_B10, 0x84000102, 0x0000003a), /* GPIO */ + PCH_PAD_CFG(GPP_B11, 0x04000000, 0x0000003b), /* GPIO */ + PCH_PAD_CFG(GPP_B12, 0x44000600, 0x0000003c), /* SLP_S0# */ + PCH_PAD_CFG(GPP_B13, 0x44000600, 0x0000003d), /* PLTRST# */ + PCH_PAD_CFG(GPP_B14, 0x84000600, 0x0000103e), /* SPKR */ + PCH_PAD_CFG(GPP_B15, 0x84000102, 0x0000003f), /* GPIO */ + PCH_PAD_CFG(GPP_B16, 0x84000102, 0x00000040), /* GPIO */ + PCH_PAD_CFG(GPP_B17, 0x44000201, 0x00000041), /* GPIO */ + PCH_PAD_CFG(GPP_B18, 0x84000100, 0x00000042), /* GPIO */ + PCH_PAD_CFG(GPP_B19, 0x84000102, 0x00000043), /* GPIO */ + PCH_PAD_CFG(GPP_B20, 0x84000102, 0x00000044), /* GPIO */ + PCH_PAD_CFG(GPP_B21, 0x84000102, 0x00000045), /* GPIO */ + PCH_PAD_CFG(GPP_B22, 0x84000100, 0x00000046), /* GPIO */ + PCH_PAD_CFG(GPP_B23, 0x84000a01, 0x00001047), /* PCHHOT# */ + /* GPIO Group GPP_C */ + PCH_PAD_CFG(GPP_C0, 0x44000502, 0x00000048), /* SMBCLK */ + PCH_PAD_CFG(GPP_C1, 0x44000502, 0x00000049), /* SMBDATA */ + PCH_PAD_CFG(GPP_C2, 0x44000201, 0x0000004a), /* GPIO */ + PCH_PAD_CFG(GPP_C3, 0x44000502, 0x0000004b), /* SML0CLK */ + PCH_PAD_CFG(GPP_C4, 0x44000502, 0x0000004c), /* SML0DATA */ + PCH_PAD_CFG(GPP_C5, 0x84000100, 0x0000004d), /* GPIO */ + /* GPP_C6 - RESERVED */ + /* GPP_C7 - RESERVED */ + PCH_PAD_CFG(GPP_C8, 0x84000502, 0x00000050), /* UART0_RXD */ + PCH_PAD_CFG(GPP_C9, 0x84000600, 0x00000051), /* UART0_TXD */ + PCH_PAD_CFG(GPP_C10, 0x84000600, 0x00000052), /* UART0_RTS# */ + PCH_PAD_CFG(GPP_C11, 0x84000502, 0x00000053), /* UART0_CTS# */ + PCH_PAD_CFG(GPP_C12, 0x84000102, 0x00000054), /* GPIO */ + PCH_PAD_CFG(GPP_C13, 0x84000102, 0x00000055), /* GPIO */ + PCH_PAD_CFG(GPP_C14, 0x84000102, 0x00000056), /* GPIO */ + PCH_PAD_CFG(GPP_C15, 0x84000102, 0x00000057), /* GPIO */ + PCH_PAD_CFG(GPP_C16, 0x84000102, 0x00000058), /* GPIO */ + PCH_PAD_CFG(GPP_C17, 0x84000102, 0x00000059), /* GPIO */ + PCH_PAD_CFG(GPP_C18, 0x84000102, 0x0000005a), /* GPIO */ + PCH_PAD_CFG(GPP_C19, 0x84000102, 0x0000005b), /* GPIO */ + PCH_PAD_CFG(GPP_C20, 0x84000502, 0x0000005c), /* UART2_RXD */ + PCH_PAD_CFG(GPP_C21, 0x84000600, 0x0000005d), /* UART2_TXD */ + PCH_PAD_CFG(GPP_C22, 0x84000600, 0x0000005e), /* UART2_RTS# */ + PCH_PAD_CFG(GPP_C23, 0x40880102, 0x0000005f), /* GPIO */ + /* GPIO Group GPP_D */ + PCH_PAD_CFG(GPP_D0, 0x84000102, 0x00000060), /* GPIO */ + PCH_PAD_CFG(GPP_D1, 0x84000102, 0x00000061), /* GPIO */ + PCH_PAD_CFG(GPP_D2, 0x84000102, 0x00000062), /* GPIO */ + PCH_PAD_CFG(GPP_D3, 0x84000102, 0x00000063), /* GPIO */ + PCH_PAD_CFG(GPP_D4, 0x84000102, 0x00000064), /* GPIO */ + PCH_PAD_CFG(GPP_D5, 0x84000402, 0x00000065), /* I2S_SFRM */ + PCH_PAD_CFG(GPP_D6, 0x84000600, 0x00000066), /* I2S_TXD */ + PCH_PAD_CFG(GPP_D7, 0x84000502, 0x00000067), /* I2S_RXD */ + PCH_PAD_CFG(GPP_D8, 0x84000402, 0x00000068), /* I2S_SCLK */ + PCH_PAD_CFG(GPP_D9, 0x84000102, 0x00000069), /* GPIO */ + PCH_PAD_CFG(GPP_D10, 0x84000102, 0x0000006a), /* GPIO */ + PCH_PAD_CFG(GPP_D11, 0x84000102, 0x0000006b), /* GPIO */ + PCH_PAD_CFG(GPP_D12, 0x84000102, 0x0000006c), /* GPIO */ + PCH_PAD_CFG(GPP_D13, 0x84000102, 0x0000006d), /* GPIO */ + PCH_PAD_CFG(GPP_D14, 0x84000100, 0x0000006e), /* GPIO */ + PCH_PAD_CFG(GPP_D15, 0x84000100, 0x0000006f), /* GPIO */ + PCH_PAD_CFG(GPP_D16, 0x84000102, 0x00000070), /* GPIO */ + PCH_PAD_CFG(GPP_D17, 0x84000102, 0x00000071), /* GPIO */ + PCH_PAD_CFG(GPP_D18, 0x84000102, 0x00000072), /* GPIO */ + PCH_PAD_CFG(GPP_D19, 0x84000500, 0x00003073), /* DMIC_CLK0 */ + PCH_PAD_CFG(GPP_D20, 0x84000500, 0x00003074), /* DMIC_DATA0 */ + PCH_PAD_CFG(GPP_D21, 0x84000102, 0x00000075), /* GPIO */ + PCH_PAD_CFG(GPP_D22, 0x84000102, 0x00000076), /* GPIO */ + PCH_PAD_CFG(GPP_D23, 0x84000102, 0x00000077), /* GPIO */ + /* GPIO Group GPP_E */ + PCH_PAD_CFG(GPP_E0, 0x84000502, 0x00003018), /* SATAXPCIE0 */ + PCH_PAD_CFG(GPP_E1, 0x84000502, 0x00003019), /* SATAXPCIE1 */ + PCH_PAD_CFG(GPP_E2, 0x84000502, 0x0000301a), /* SATAXPCIE2 */ + PCH_PAD_CFG(GPP_E3, 0x84000500, 0x0000001b), /* CPU_GP0 */ + PCH_PAD_CFG(GPP_E4, 0x84000500, 0x0000001c), /* SATA_DEVSLP0 */ + PCH_PAD_CFG(GPP_E5, 0x84000500, 0x0000001d), /* SATA_DEVSLP1 */ + PCH_PAD_CFG(GPP_E6, 0x84000500, 0x0000001e), /* SATA_DEVSLP2 */ + PCH_PAD_CFG(GPP_E7, 0x84000102, 0x0000001f), /* GPIO */ + PCH_PAD_CFG(GPP_E8, 0x84000600, 0x00000020), /* SATA_LED# */ + PCH_PAD_CFG(GPP_E9, 0x44000502, 0x00000021), /* USB_OC0# */ + PCH_PAD_CFG(GPP_E10, 0x44000502, 0x00000022), /* USB_OC1# */ + PCH_PAD_CFG(GPP_E11, 0x44000502, 0x00000023), /* USB_OC2# */ + PCH_PAD_CFG(GPP_E12, 0x44000502, 0x00000024), /* USB_OC3# */ + /* GPIO Group GPP_F */ + PCH_PAD_CFG(GPP_F0, 0x84000102, 0x00000025), /* GPIO */ + PCH_PAD_CFG(GPP_F1, 0x84000502, 0x00003026), /* SATAXPCIE4 */ + PCH_PAD_CFG(GPP_F2, 0x44000300, 0x00000027), /* GPIO */ + PCH_PAD_CFG(GPP_F3, 0x84000102, 0x00000028), /* GPIO */ + PCH_PAD_CFG(GPP_F4, 0x84000102, 0x00000029), /* GPIO */ + PCH_PAD_CFG(GPP_F5, 0x84000102, 0x0000002a), /* GPIO */ + PCH_PAD_CFG(GPP_F6, 0x84000102, 0x0000002b), /* GPIO */ + PCH_PAD_CFG(GPP_F7, 0x84000102, 0x0000002c), /* GPIO */ + PCH_PAD_CFG(GPP_F8, 0x84000102, 0x0000002d), /* GPIO */ + PCH_PAD_CFG(GPP_F9, 0x84000102, 0x0000002e), /* GPIO */ + PCH_PAD_CFG(GPP_F10, 0x80100102, 0x0000002f), /* GPIO */ + PCH_PAD_CFG(GPP_F11, 0x84000102, 0x00000030), /* GPIO */ + PCH_PAD_CFG(GPP_F12, 0x80900102, 0x00000031), /* GPIO */ + PCH_PAD_CFG(GPP_F13, 0x80100102, 0x00000032), /* GPIO */ + PCH_PAD_CFG(GPP_F14, 0x40900102, 0x00000033), /* GPIO */ + PCH_PAD_CFG(GPP_F15, 0x44000502, 0x00000034), /* USB_OC4# */ + PCH_PAD_CFG(GPP_F16, 0x44000502, 0x00000035), /* USB_OC5# */ + PCH_PAD_CFG(GPP_F17, 0x44000502, 0x00000036), /* USB_OC6# */ + PCH_PAD_CFG(GPP_F18, 0x84000201, 0x00000037), /* GPIO */ + PCH_PAD_CFG(GPP_F19, 0x84000100, 0x00000038), /* GPIO */ + PCH_PAD_CFG(GPP_F20, 0x84000102, 0x00000039), /* GPIO */ + PCH_PAD_CFG(GPP_F21, 0x84000102, 0x0000003a), /* GPIO */ + PCH_PAD_CFG(GPP_F22, 0x84000102, 0x0000003b), /* GPIO */ + PCH_PAD_CFG(GPP_F23, 0x84000102, 0x0000003c), /* GPIO */ + /* GPIO Group GPP_G */ + PCH_PAD_CFG(GPP_G0, 0xc4000102, 0x0000003d), /* GPIO */ + PCH_PAD_CFG(GPP_G1, 0xc4000102, 0x0000003e), /* GPIO */ + PCH_PAD_CFG(GPP_G2, 0xc4000100, 0x0000003f), /* GPIO */ + PCH_PAD_CFG(GPP_G3, 0xc4000100, 0x00000040), /* GPIO */ + PCH_PAD_CFG(GPP_G4, 0x44000200, 0x00000041), /* GPIO */ + PCH_PAD_CFG(GPP_G5, 0xc4000102, 0x00000042), /* GPIO */ + PCH_PAD_CFG(GPP_G6, 0xc0800102, 0x00000043), /* GPIO */ + PCH_PAD_CFG(GPP_G7, 0xc4000102, 0x00000044), /* GPIO */ + PCH_PAD_CFG(GPP_G8, 0x84000100, 0x00000045), /* GPIO */ + PCH_PAD_CFG(GPP_G9, 0x84000100, 0x00000046), /* GPIO */ + PCH_PAD_CFG(GPP_G10, 0x84000102, 0x00000047), /* GPIO */ + PCH_PAD_CFG(GPP_G11, 0x84000100, 0x00000048), /* GPIO */ + PCH_PAD_CFG(GPP_G12, 0x80800102, 0x00000049), /* GPIO */ + PCH_PAD_CFG(GPP_G13, 0x84000201, 0x0000004a), /* GPIO */ + PCH_PAD_CFG(GPP_G14, 0x80800102, 0x0000004b), /* GPIO */ + PCH_PAD_CFG(GPP_G15, 0x84000200, 0x0000004c), /* GPIO */ + PCH_PAD_CFG(GPP_G16, 0x84000201, 0x0000104d), /* GPIO */ + PCH_PAD_CFG(GPP_G17, 0x84000102, 0x0000004e), /* GPIO */ + PCH_PAD_CFG(GPP_G18, 0x80100102, 0x0000004f), /* GPIO */ + PCH_PAD_CFG(GPP_G19, 0x84000500, 0x00000050), /* SMI# */ + PCH_PAD_CFG(GPP_G20, 0x84000102, 0x00000051), /* GPIO */ + PCH_PAD_CFG(GPP_G21, 0x84000102, 0x00000052), /* GPIO */ + PCH_PAD_CFG(GPP_G22, 0x84000102, 0x00000053), /* GPIO */ + PCH_PAD_CFG(GPP_G23, 0x84000102, 0x00000054), /* GPIO */ + /* GPIO Group GPP_H */ + PCH_PAD_CFG(GPP_H0, 0x84000102, 0x00000055), /* GPIO */ + PCH_PAD_CFG(GPP_H1, 0x44000300, 0x00000056), /* GPIO */ + PCH_PAD_CFG(GPP_H2, 0x84000102, 0x00000057), /* GPIO */ + PCH_PAD_CFG(GPP_H3, 0x84000102, 0x00000058), /* GPIO */ + PCH_PAD_CFG(GPP_H4, 0x84000102, 0x00000059), /* GPIO */ + PCH_PAD_CFG(GPP_H5, 0x84000102, 0x0000005a), /* GPIO */ + PCH_PAD_CFG(GPP_H6, 0x84000102, 0x0000005b), /* GPIO */ + PCH_PAD_CFG(GPP_H7, 0x84000102, 0x0000005c), /* GPIO */ + PCH_PAD_CFG(GPP_H8, 0x84000100, 0x0000005d), /* GPIO */ + PCH_PAD_CFG(GPP_H9, 0x84000102, 0x0000005e), /* GPIO */ + PCH_PAD_CFG(GPP_H10, 0x84000102, 0x0000005f), /* GPIO */ + PCH_PAD_CFG(GPP_H11, 0x84000102, 0x00000060), /* GPIO */ + PCH_PAD_CFG(GPP_H12, 0x84000100, 0x00000061), /* GPIO */ + PCH_PAD_CFG(GPP_H13, 0x80100102, 0x00000062), /* GPIO */ + PCH_PAD_CFG(GPP_H14, 0x80100102, 0x00000063), /* GPIO */ + PCH_PAD_CFG(GPP_H15, 0x80100100, 0x00000064), /* GPIO */ + PCH_PAD_CFG(GPP_H16, 0x80000102, 0x00000065), /* GPIO */ + PCH_PAD_CFG(GPP_H17, 0x84000201, 0x00000066), /* GPIO */ + PCH_PAD_CFG(GPP_H18, 0x84000102, 0x00000067), /* GPIO */ + PCH_PAD_CFG(GPP_H19, 0x84000102, 0x00000068), /* GPIO */ + PCH_PAD_CFG(GPP_H20, 0x84000102, 0x00000069), /* GPIO */ + PCH_PAD_CFG(GPP_H21, 0x84000102, 0x0000006a), /* GPIO */ + PCH_PAD_CFG(GPP_H22, 0x84000102, 0x0000006b), /* GPIO */ + PCH_PAD_CFG(GPP_H23, 0x04000100, 0x0000006c), /* GPIO */ + /* GPIO Group GPD */ + PCH_PAD_CFG(GPD0, 0x84000102, 0x00000018), /* GPIO */ + PCH_PAD_CFG(GPD1, 0x04000200, 0x00000019), /* GPIO */ + PCH_PAD_CFG(GPD2, 0x00000602, 0x00003c1a), /* LAN_WAKE# */ + PCH_PAD_CFG(GPD3, 0x04000502, 0x0000301b), /* PWRBTN# */ + PCH_PAD_CFG(GPD4, 0x04000600, 0x0000001c), /* SLP_S3# */ + PCH_PAD_CFG(GPD5, 0x04000600, 0x0000001d), /* SLP_S4# */ + PCH_PAD_CFG(GPD6, 0x84000102, 0x0000001e), /* GPIO */ + PCH_PAD_CFG(GPD7, 0x84000103, 0x0000001f), /* GPIO */ + PCH_PAD_CFG(GPD8, 0x04000600, 0x00000020), /* SUSCLK */ + PCH_PAD_CFG(GPD9, 0x04000600, 0x00000021), /* SLP_WLAN# */ + PCH_PAD_CFG(GPD10, 0x04000600, 0x00000022), /* SLP_S5# */ + PCH_PAD_CFG(GPD11, 0x04000200, 0x00000023), /* GPIO */ + /* GPIO Group GPP_I */ + PCH_PAD_CFG(GPP_I0, 0x84000502, 0x0000006d), /* DDPB_HPD0 */ + PCH_PAD_CFG(GPP_I1, 0x84000502, 0x0000006e), /* DDPC_HPD1 */ + PCH_PAD_CFG(GPP_I2, 0x84000500, 0x0000006f), /* DDPD_HPD2 */ + PCH_PAD_CFG(GPP_I3, 0x84000502, 0x00000070), /* DDPE_HPD3 */ + PCH_PAD_CFG(GPP_I4, 0x84000100, 0x00000071), /* GPIO */ + PCH_PAD_CFG(GPP_I5, 0x84000500, 0x00000072), /* DDPB_CTRLCLK */ + PCH_PAD_CFG(GPP_I6, 0x84000500, 0x00001073), /* DDPB_CTRLDATA */ + PCH_PAD_CFG(GPP_I7, 0x84000500, 0x00000074), /* DDPC_CTRLCLK */ + PCH_PAD_CFG(GPP_I8, 0x84000500, 0x00001075), /* DDPC_CTRLDATA */ + PCH_PAD_CFG(GPP_I9, 0x84000500, 0x00000076), /* DDPD_CTRLCLK */ + PCH_PAD_CFG(GPP_I10, 0x84000500, 0x00001077), /* DDPD_CTRLDATA */ +}; + +/* Early pad configuration in romstage. */ +static const struct pad_config early_gpio_table[] = { + /* GPIO Group GPP_A */ + PCH_PAD_CFG(GPP_A0, 0x84000502, 0x00000018), /* RCIN# */ + PCH_PAD_CFG(GPP_A1, 0x84000402, 0x00003019), /* LAD0 */ + PCH_PAD_CFG(GPP_A2, 0x84000402, 0x0000301a), /* LAD1 */ + PCH_PAD_CFG(GPP_A3, 0x84000402, 0x0000301b), /* LAD2 */ + PCH_PAD_CFG(GPP_A4, 0x84000402, 0x0000301c), /* LAD3 */ + PCH_PAD_CFG(GPP_A5, 0x84000600, 0x0000001d), /* LFRAME# */ + PCH_PAD_CFG(GPP_A6, 0x84000402, 0x0000001e), /* SERIRQ */ + PCH_PAD_CFG(GPP_A8, 0x84000500, 0x00000020), /* CLKRUN# */ + PCH_PAD_CFG(GPP_A9, 0x84000600, 0x00001021), /* CLKOUT_LPC0 */ + PCH_PAD_CFG(GPP_A10, 0x84000600, 0x00001022), /* CLKOUT_LPC1 */ + /* ---- */ + PCH_PAD_CFG(GPP_A13, 0x44000600, 0x00000025), /* SUSWARN#/SUSPWRDNACK */ + PCH_PAD_CFG(GPP_A14, 0x44000600, 0x00000026), /* SUS_STAT# */ + PCH_PAD_CFG(GPP_A15, 0x44000502, 0x00003027), /* SUS_ACK# */ +}; + +const struct pad_config *get_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *get_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} \ No newline at end of file diff --git a/src/mainboard/asrock/h110m/hda_verb.c b/src/mainboard/asrock/h110m/variants/dvs/hda_verb.c similarity index 100% rename from src/mainboard/asrock/h110m/hda_verb.c rename to src/mainboard/asrock/h110m/variants/dvs/hda_verb.c diff --git a/src/mainboard/asrock/h110m/variants/dvs/overridetree.cb b/src/mainboard/asrock/h110m/variants/dvs/overridetree.cb new file mode 100644 index 0000000..aad1374 --- /dev/null +++ b/src/mainboard/asrock/h110m/variants/dvs/overridetree.cb @@ -0,0 +1,207 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2017 Intel Corporation. +## Copyright (C) 2019 Maxim Polyakov <max.senia.poliak(a)gmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +chip soc/intel/skylake + + # USB + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[2]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[3]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[8]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[10]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[11]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)" + + # SATA + register "EnableSata" = "1" + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ \ + [0] = 1, \ + [1] = 1, \ + [2] = 1, \ + [3] = 1, \ + [4] = 1, \ + [5] = 1, \ + [6] = 1, \ + [7] = 1, \ + }" + + register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V + + # PCH UART, SPI, I2C + register "SerialIoDevMode" = "{ \ + [PchSerialIoIndexI2C0] = PchSerialIoPci, \ + [PchSerialIoIndexI2C1] = PchSerialIoPci, \ + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi0] = PchSerialIoPci, \ + [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart0] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ + }" + + # Set params for PEG 0:1:0 + register "Peg0MaxLinkWidth" = "Peg0_x16" + # Configure PCIe clockgen in PCH + # PEG0 uses SRCCLKREQ0 and CLKSRC0 + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "0" + register "PcieRpClkSrcNumber[0]" = "0" + + # Enable Root port 5 (x1) for PCIE slot. + register "PcieRpEnable[4]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[4]" = "1" + # Use SRCCLKREQ2# + register "PcieRpClkReqNumber[4]" = "2" + # Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[4]" = "1" + # Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[4]" = "1" + # Use CLK SRC 2 + register "PcieRpClkSrcNumber[4]" = "2" + # Use Hot Plug subsystem + register "PcieRpHotPlug[4]" = "1" + + # Enable Root port 6 (x1) for LAN. + register "PcieRpEnable[5]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[5]" = "1" + # Use SRCCLKREQ1# + register "PcieRpClkReqNumber[5]" = "1" + # Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[5]" = "1" + # Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[5]" = "1" + # Use CLK SRC 1 + register "PcieRpClkSrcNumber[5]" = "1" + + # Enable Root port 7 (x1) for PCIE slot. + register "PcieRpEnable[6]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[6]" = "1" + # Use SRCCLKREQ3# + register "PcieRpClkReqNumber[6]" = "3" + # Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[6]" = "1" + # Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[6]" = "1" + # Use CLK SRC 3 + register "PcieRpClkSrcNumber[6]" = "3" + # Use Hot Plug subsystem + register "PcieRpHotPlug[6]" = "1" + + # PL2 override 91W + register "tdp_pl2_override" = "91" + + device domain 0 on + device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 on end # PCI Express Port 5 + device pci 1c.5 on end # PCI Express Port 6 + device pci 1c.6 on end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1f.0 on # Chipset LPC/eSPI Controller + subsystemid 0x1849 0x1a43 + chip superio/nuvoton/nct6791d + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # Parallel + # global + irq 0x1c = 0x10 + irq 0x27 = 0x10 + irq 0x2a = 0x64 + # parallel port + io 0x60 = 0x0378 + irq 0x70 = 7 + drq 0x74 = 4 # No DMA + irq 0xf0 = 0x3c # Printer mode + end + device pnp 2e.2 on # UART A + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # IR + io 0x60 = 0x02f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 KBC + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # Keyboard + irq 0x72 = 12 # Mouse + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6 + device pnp 2e.107 off end # GPIO7 + device pnp 2e.207 off end # GPIO8 + device pnp 2e.8 off end # WDT + device pnp 2e.108 off end # GPIO0 + device pnp 2e.308 off end # GPIO base + device pnp 2e.408 off end # WDTMEM + device pnp 2e.708 off end # GPIO1 + device pnp 2e.9 off end # GPIO2 + device pnp 2e.109 off end # GPIO3 + device pnp 2e.209 off end # GPIO4 + device pnp 2e.309 off end # GPIO5 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HWM, LED + io 0x60 = 0x0290 + io 0x62 = 0 + irq 0x70 = 0 + end + device pnp 2e.d off end # BCLK, WDT2, WDT_MEM + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID, Port 80 UART + device pnp 2e.16 off end # DS5 + device pnp 2e.116 off end # DS3 + device pnp 2e.316 off end # PCHDSW + device pnp 2e.416 off end # DSWWOPT + device pnp 2e.516 off end # DS3OPT + device pnp 2e.616 off end # DSDSS + device pnp 2e.716 off end # DSPU + end # superio/nuvoton/nct6791d + chip drivers/pc80/tpm + device pnp 4e.0 on end # TPM module + end + end # LPC Interface + end +end diff --git a/src/mainboard/asrock/h110m/variants/stx/gpio.c b/src/mainboard/asrock/h110m/variants/stx/gpio.c new file mode 100644 index 0000000..472db6c --- /dev/null +++ b/src/mainboard/asrock/h110m/variants/stx/gpio.c @@ -0,0 +1,268 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Maxim Polyakov <max.senia.poliak(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <commonlib/helpers.h> +#include "../../include/gpio.h" + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + /* ------- GPIO Group GPP_A ------- */ + PCH_PAD_CFG(GPP_A0, 0x84000502, 0x00000000), /* RCIN# */ + PCH_PAD_CFG(GPP_A1, 0x84000402, 0x00003000), /* LAD0 */ + PCH_PAD_CFG(GPP_A2, 0x84000402, 0x00003000), /* LAD1 */ + PCH_PAD_CFG(GPP_A3, 0x84000402, 0x00003000), /* LAD2 */ + PCH_PAD_CFG(GPP_A4, 0x84000402, 0x00003000), /* LAD3 */ + PCH_PAD_CFG(GPP_A5, 0x84000600, 0x00000000), /* LFRAME# */ + PCH_PAD_CFG(GPP_A6, 0x84000400, 0x00000000), /* SERIRQ */ + PCH_PAD_CFG(GPP_A7, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_A8, 0x84000500, 0x00000000), /* CLKRUN# */ + PCH_PAD_CFG(GPP_A9, 0x84000600, 0x00001000), /* CLKOUT_LPC0 */ + PCH_PAD_CFG(GPP_A10, 0x84000600, 0x00001000), /* CLKOUT_LPC1 */ + PCH_PAD_CFG(GPP_A11, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_A12, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_A13, 0x44000600, 0x00000000), /* SUSWARN#/SUSPWRDNACK */ + PCH_PAD_CFG(GPP_A14, 0x44000600, 0x00000000), /* SUS_STAT# */ + PCH_PAD_CFG(GPP_A15, 0x44000502, 0x00003000), /* SUS_ACK# */ + PCH_PAD_CFG(GPP_A16, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_A17, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_A18, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_A19, 0x44000300, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_A20, 0x44000300, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_A21, 0x44000300, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_A22, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_A23, 0x84000102, 0x00000000), /* GPIO */ + /* ------- GPIO Group GPP_B ------- */ + PCH_PAD_CFG(GPP_B0, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B1, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B2, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B3, 0x44000201, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B4, 0x84000502, 0x00000000), /* CPU_GP3 */ + PCH_PAD_CFG(GPP_B5, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B6, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B7, 0x44000300, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B8, 0x44000300, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B9, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B10, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B11, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B12, 0x44000600, 0x00000000), /* SLP_S0# */ + PCH_PAD_CFG(GPP_B13, 0x44000600, 0x00000000), /* PLTRST# */ + PCH_PAD_CFG(GPP_B14, 0x84000600, 0x00001000), /* SPKR */ + PCH_PAD_CFG(GPP_B15, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B16, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B17, 0x44000201, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B18, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B19, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B20, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B21, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B22, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B23, 0x84000a01, 0x00001000), /* PCHHOT# */ + /* ------- GPIO Group GPP_C ------- */ + PCH_PAD_CFG(GPP_C0, 0x44000502, 0x00000000), /* SMBCLK */ + PCH_PAD_CFG(GPP_C1, 0x44000502, 0x00000000), /* SMBDATA */ + PCH_PAD_CFG(GPP_C2, 0x44000201, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_C3, 0x44000502, 0x00000000), /* SML0CLK */ + PCH_PAD_CFG(GPP_C4, 0x44000502, 0x00000000), /* SML0DATA */ + PCH_PAD_CFG(GPP_C5, 0x84000100, 0x00000000), /* GPIO */ + /* GPP_C6 - RESERVED */ + /* GPP_C7 - RESERVED */ + PCH_PAD_CFG(GPP_C8, 0x84000502, 0x00000000), /* UART0_RXD */ + PCH_PAD_CFG(GPP_C9, 0x84000600, 0x00000000), /* UART0_TXD */ + PCH_PAD_CFG(GPP_C10, 0x84000600, 0x00000000), /* UART0_RTS# */ + PCH_PAD_CFG(GPP_C11, 0x84000502, 0x00000000), /* UART0_CTS# */ + PCH_PAD_CFG(GPP_C12, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_C13, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_C14, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_C15, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_C16, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_C17, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_C18, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_C19, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_C20, 0x84000502, 0x00000000), /* UART2_RXD */ + PCH_PAD_CFG(GPP_C21, 0x84000600, 0x00000000), /* UART2_TXD */ + PCH_PAD_CFG(GPP_C22, 0x84000600, 0x00000000), /* UART2_RTS# */ + PCH_PAD_CFG(GPP_C23, 0x40880102, 0x00000000), /* GPIO */ + /* ------- GPIO Group GPP_D ------- */ + PCH_PAD_CFG(GPP_D0, 0xc4000200, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D1, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D2, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D3, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D4, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D5, 0x84000402, 0x00000000), /* I2S_SFRM */ + PCH_PAD_CFG(GPP_D6, 0x84000600, 0x00000000), /* I2S_TXD */ + PCH_PAD_CFG(GPP_D7, 0x84000502, 0x00000000), /* I2S_RXD */ + PCH_PAD_CFG(GPP_D8, 0x84000402, 0x00000000), /* I2S_SCLK */ + PCH_PAD_CFG(GPP_D9, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D10, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D11, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D12, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D13, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D14, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D15, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D16, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D17, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D18, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D19, 0x84000500, 0x00003000), /* DMIC_CLK0 */ + PCH_PAD_CFG(GPP_D20, 0x84000500, 0x00003000), /* DMIC_DATA0 */ + PCH_PAD_CFG(GPP_D21, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D22, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D23, 0x84000102, 0x00000000), /* GPIO */ + /* ------- GPIO Group GPP_E ------- */ + PCH_PAD_CFG(GPP_E0, 0x84000502, 0x00003000), /* SATAXPCIE0 */ + PCH_PAD_CFG(GPP_E1, 0x84000502, 0x00003000), /* SATAXPCIE1 */ + PCH_PAD_CFG(GPP_E2, 0x84000502, 0x00003000), /* SATAXPCIE2 */ + PCH_PAD_CFG(GPP_E3, 0x84000502, 0x00000000), /* CPU_GP0 */ + PCH_PAD_CFG(GPP_E4, 0x84000500, 0x00000000), /* SATA_DEVSLP0 */ + PCH_PAD_CFG(GPP_E5, 0x84000500, 0x00000000), /* SATA_DEVSLP1 */ + PCH_PAD_CFG(GPP_E6, 0x84000500, 0x00000000), /* SATA_DEVSLP2 */ + PCH_PAD_CFG(GPP_E7, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_E8, 0x84000600, 0x00000000), /* SATA_LED# */ + PCH_PAD_CFG(GPP_E9, 0x44000502, 0x00000000), /* USB_OC0# */ + PCH_PAD_CFG(GPP_E10, 0x44000502, 0x00000000), /* USB_OC1# */ + PCH_PAD_CFG(GPP_E11, 0x44000502, 0x00000000), /* USB_OC2# */ + PCH_PAD_CFG(GPP_E12, 0x44000502, 0x00000000), /* USB_OC3# */ + /* ------- GPIO Group GPP_F ------- */ + PCH_PAD_CFG(GPP_F0, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F1, 0x84000502, 0x00003000), /* SATAXPCIE4 */ + PCH_PAD_CFG(GPP_F2, 0x44000300, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F3, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F4, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F5, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F6, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F7, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F8, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F9, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F10, 0x80100102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F11, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F12, 0x80900102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F13, 0x80100102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F14, 0x40900102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F15, 0x44000502, 0x00000000), /* USB_OC4# */ + PCH_PAD_CFG(GPP_F16, 0x44000502, 0x00000000), /* USB_OC5# */ + PCH_PAD_CFG(GPP_F17, 0x44000502, 0x00000000), /* USB_OC6# */ + PCH_PAD_CFG(GPP_F18, 0x84000201, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F19, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F20, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F21, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F22, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F23, 0x84000100, 0x00000000), /* GPIO */ + /* ------- GPIO Group GPP_G ------- */ + PCH_PAD_CFG(GPP_G0, 0x44000300, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G1, 0x44000300, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G2, 0x80800102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G3, 0x80800102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G4, 0x44000200, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G5, 0x44000300, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G6, 0x80800102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G7, 0x44000300, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G8, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G9, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G10, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G11, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G12, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G13, 0x84000201, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G14, 0x80800100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G15, 0x84000200, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G16, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G17, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G18, 0x80100102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G19, 0x84000500, 0x00000000), /* SMI# */ + PCH_PAD_CFG(GPP_G20, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G21, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G22, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G23, 0x84000102, 0x00000000), /* GPIO */ + /* ------- GPIO Group GPP_H ------- */ + PCH_PAD_CFG(GPP_H0, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H1, 0x44000300, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H2, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H3, 0x44000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H4, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H5, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H6, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H7, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H8, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H9, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H10, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H11, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H12, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H13, 0x80100102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H14, 0x80100102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H15, 0x80100102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H16, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H17, 0x84000201, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H18, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H19, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H20, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H21, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H22, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H23, 0x04000102, 0x00000000), /* GPIO */ + /* -------- GPIO Group GPD -------- */ + PCH_PAD_CFG(GPD0, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPD1, 0x04000200, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPD2, 0x00080602, 0x00003c00), /* LAN_WAKE# */ + PCH_PAD_CFG(GPD3, 0x04000502, 0x00003000), /* PWRBTN# */ + PCH_PAD_CFG(GPD4, 0x04000600, 0x00000000), /* SLP_S3# */ + PCH_PAD_CFG(GPD5, 0x04000600, 0x00000000), /* SLP_S4# */ + PCH_PAD_CFG(GPD6, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPD7, 0x84000103, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPD8, 0x04000600, 0x00000000), /* SUSCLK */ + PCH_PAD_CFG(GPD9, 0x04000600, 0x00000000), /* SLP_WLAN# */ + PCH_PAD_CFG(GPD10, 0x04000600, 0x00000000), /* SLP_S5# */ + PCH_PAD_CFG(GPD11, 0x04000600, 0x00000000), /* LANPHYPC */ + /* ------- GPIO Group GPP_I ------- */ + PCH_PAD_CFG(GPP_I0, 0x84000500, 0x00000000), /* DDPB_HPD0 */ + PCH_PAD_CFG(GPP_I1, 0x84000502, 0x00000000), /* DDPC_HPD1 */ + PCH_PAD_CFG(GPP_I2, 0x84000502, 0x00000000), /* DDPD_HPD2 */ + PCH_PAD_CFG(GPP_I3, 0x84000500, 0x00000000), /* DDPE_HPD3 */ + PCH_PAD_CFG(GPP_I4, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_I5, 0x84000502, 0x00000000), /* DDPB_CTRLCLK */ + PCH_PAD_CFG(GPP_I6, 0x84000502, 0x00001000), /* DDPB_CTRLDATA */ + PCH_PAD_CFG(GPP_I7, 0x84000500, 0x00000000), /* DDPC_CTRLCLK */ + PCH_PAD_CFG(GPP_I8, 0x84000500, 0x00001000), /* DDPC_CTRLDATA */ + PCH_PAD_CFG(GPP_I9, 0x84000500, 0x00000000), /* DDPD_CTRLCLK */ + PCH_PAD_CFG(GPP_I10, 0x84000500, 0x00001000), /* DDPD_CTRLDATA */ +}; + +/* Early pad configuration in romstage */ +static const struct pad_config early_gpio_table[] = { + PCH_PAD_CFG(GPP_A0, 0x84000502, 0x00000000), /* RCIN# */ + PCH_PAD_CFG(GPP_A1, 0x84000402, 0x00003000), /* LAD0 */ + PCH_PAD_CFG(GPP_A2, 0x84000402, 0x00003000), /* LAD1 */ + PCH_PAD_CFG(GPP_A3, 0x84000402, 0x00003000), /* LAD2 */ + PCH_PAD_CFG(GPP_A4, 0x84000402, 0x00003000), /* LAD3 */ + PCH_PAD_CFG(GPP_A5, 0x84000600, 0x00000000), /* LFRAME# */ + PCH_PAD_CFG(GPP_A6, 0x84000400, 0x00000000), /* SERIRQ */ + PCH_PAD_CFG(GPP_A7, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_A8, 0x84000500, 0x00000000), /* CLKRUN# */ + PCH_PAD_CFG(GPP_A9, 0x84000600, 0x00001000), /* CLKOUT_LPC0 */ + PCH_PAD_CFG(GPP_A10, 0x84000600, 0x00001000), /* CLKOUT_LPC1 */ + PCH_PAD_CFG(GPP_A11, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_A12, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_A13, 0x44000600, 0x00000000), /* SUSWARN#/SUSPWRDNACK */ + PCH_PAD_CFG(GPP_A14, 0x44000600, 0x00000000), /* SUS_STAT# */ + PCH_PAD_CFG(GPP_A15, 0x44000502, 0x00003000), /* SUS_ACK# */ +}; + +const struct pad_config *get_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *get_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/asrock/h110m/variants/stx/hda_verb.c b/src/mainboard/asrock/h110m/variants/stx/hda_verb.c new file mode 100644 index 0000000..52e3039 --- /dev/null +++ b/src/mainboard/asrock/h110m/variants/stx/hda_verb.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation + * (Written by Naresh G Solanki <naresh.solanki(a)intel.com> for Intel Corp.) + * Copyright (C) 2019 Maxim Polyakov <max.senia.poliak(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* ALC283 coreboot specific header */ + 0x10ec0283, /* Codec Vendor / Device ID: Realtek */ + 0x18491283, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0x0, 0x18491283), + AZALIA_PIN_CFG(0x0, 0x12, 0x40000000), + AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x1a, 0x02a19020), + AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x1d, 0x40559c05), + AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x21, 0x0221101f), + + /* Intel Kaby Lake HDA coreboot specific header */ + 0x8086280b, /* Codec Vendor / Device ID */ + 0x80860101, + 0x00000004, + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ + AZALIA_SUBVENDOR(0x2, 0x80860101), + + /* Pin Complex (NID 0x05) Digital Out at Int HDMI */ + AZALIA_PIN_CFG(0x2, 0x05, 0x18560010), + + /* Pin Complex (NID 0x06) Digital Out at Int HDMI */ + AZALIA_PIN_CFG(0x2, 0x06, 0x18560020), + + /* Pin Complex (NID 0x07) Digital Out at Int HDMI */ + AZALIA_PIN_CFG(0x2, 0x07, 0x18560030) +}; + +const u32 pc_beep_verbs[] = { +}; +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asrock/h110m/variants/stx/overridetree.cb b/src/mainboard/asrock/h110m/variants/stx/overridetree.cb new file mode 100644 index 0000000..45403c8 --- /dev/null +++ b/src/mainboard/asrock/h110m/variants/stx/overridetree.cb @@ -0,0 +1,133 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2017 Intel Corporation. +## Copyright (C) 2019 Maxim Polyakov <max.senia.poliak(a)gmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +chip soc/intel/skylake + + # FSP Configuration + register "EnableLan" = "1" + + # USB 2.0 + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port Front Panel + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-C Port Front Panel + register "usb2_ports[2]" = "USB2_PORT_MID(OC4)" # USB3/2 Type A Front Panel + register "usb2_ports[3]" = "USB2_PORT_MID(OC4)" # USB3/2 Type A Back panel + register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" # USB3/2 Type A Back panel + register "usb2_ports[5]" = "USB2_PORT_EMPTY" + register "usb2_ports[6]" = "USB2_PORT_EMPTY" + register "usb2_ports[7]" = "USB2_PORT_EMPTY" + register "usb2_ports[8]" = "USB2_PORT_EMPTY" + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth + register "usb2_ports[10]" = "USB2_PORT_EMPTY" + register "usb2_ports[11]" = "USB2_PORT_EMPTY" + register "usb2_ports[12]" = "USB2_PORT_EMPTY" + register "usb2_ports[13]" = "USB2_PORT_EMPTY" + + # USB 3.0 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A Front Panel + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A Back panel + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A Back panel + register "usb3_ports[5]" = "USB3_PORT_EMPTY" + register "usb3_ports[6]" = "USB3_PORT_EMPTY" + register "usb3_ports[7]" = "USB3_PORT_EMPTY" + register "usb3_ports[8]" = "USB3_PORT_EMPTY" + register "usb3_ports[9]" = "USB3_PORT_EMPTY" + + # SATA + # SATA0 - Unused + # SATA1 - Bottom left connector + # SATA2 - Bottom right connector + # SATA3 - Top side connector + register "EnableSata" = "1" + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ \ + [0] = 0, \ + [1] = 1, \ + [2] = 1, \ + [3] = 1, \ + [4] = 0, \ + [5] = 0, \ + [6] = 0, \ + [7] = 0, \ + }" + + # PCH UART, SPI, I2C + register "SerialIoDevMode" = "{ \ + [PchSerialIoIndexI2C0] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi0] = PchSerialIoPci, \ + [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart0] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ + }" + + # PEG 0:1:0 is used for NVMe x4 2280 M.2 + register "Peg0MaxLinkWidth" = "Peg0_x4" + # Configure PCH PCIe clockgen for PEG0: SRCCLKREQ7 and CLKSRC7 + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "7" + register "PcieRpClkSrcNumber[0]" = "7" + + # Root port 4 (x1) is used for I219V LAN device + register "PcieRpEnable[3]" = "1" + # Use SRCCLKREQ13 and CLKSRC10 + register "PcieRpClkReqSupport[3]" = "1" + register "PcieRpClkReqNumber[3]" = "13" + register "PcieRpClkSrcNumber[3]" = "10" + # Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[3]" = "1" + # Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[3]" = "1" + + # Root port 7(x1) is used for 2242 M.2 PCIE slot + register "PcieRpEnable[6]" = "1" + # Use SRCCLKREQ1 and CLKSRC1 + register "PcieRpClkReqSupport[6]" = "1" + register "PcieRpClkReqNumber[6]" = "1" + register "PcieRpClkSrcNumber[6]" = "1" + # Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[6]" = "1" + # Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[6]" = "1" + # Use Hot Plug subsystem + register "PcieRpHotPlug[6]" = "1" + + # PL2 override 65W + register "tdp_pl2_override" = "65" + + device domain 0 on + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 on end # PCI Express Port 5 + device pci 1c.5 on end # PCI Express Port 6 + device pci 1c.6 on end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1f.0 on # Chipset LPC/eSPI Controller + subsystemid 0x1849 0x1a43 + end # LPC Interface + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/34904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If95c7ec78b8bee10ed7ae761754ba7f7d548aa55 Gerrit-Change-Number: 34904 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: arch/x86: Fix .bss section in CAR
by Kyösti Mälkki (Code Review) 11 Sep '19

11 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35034 ) Change subject: arch/x86: Fix .bss section in CAR ...................................................................... arch/x86: Fix .bss section in CAR Fix clearing CAR region, 'stosl' stores 4 bytes at a time. Restrict the use of symbol names _car_global_[start|end] to be used exclusively with CAR_GLOBAL_MIGRATION=y. They just alias the start and end of .bss section in CAR. Change-Id: I36c858a4f181516d4c61f9fd1d5005c7d2c06057 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/assembly_entry.S M src/arch/x86/car.ld M src/arch/x86/include/arch/early_variables.h M src/arch/x86/include/arch/symbols.h M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S M src/soc/intel/quark/romstage/fsp2_0.c 6 files changed, 38 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/35034/1 diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S index 4ead9ea..b3871d6 100644 --- a/src/arch/x86/assembly_entry.S +++ b/src/arch/x86/assembly_entry.S @@ -35,12 +35,13 @@ /* reset stack pointer to CAR stack */ mov $_car_stack_end, %esp - /* clear CAR_GLOBAL area as it is not shared */ + /* clear .bss section as it is not shared */ cld xor %eax, %eax - movl $(_car_global_end), %ecx - movl $(_car_global_start), %edi + movl $(_ebss), %ecx + movl $(_bss), %edi sub %edi, %ecx + shrl $2, %ecx rep stosl #if ((ENV_VERSTAGE && CONFIG(VERSTAGE_DEBUG_SPINLOOP)) \ diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 822f7fd..bc0090b 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -68,11 +68,13 @@ . += 80; _car_ehci_dbg_info_end = .; - /* _car_global_start and _car_global_end provide symbols to per-stage + /* _bss and _ebss provide symbols to per-stage * variables that are not shared like the timestamp and the pre-ram * cbmem console. This is useful for clearing this area on a per-stage * basis when more than one stage uses cache-as-ram for CAR_GLOBALs. */ - _car_global_start = .; + + . = ALIGN(ARCH_POINTER_ALIGN_SIZE); + _bss = .; #if ENV_STAGE_HAS_BSS_SECTION /* Allow global uninitialized variables for stages without CAR teardown. */ *(.bss) @@ -80,10 +82,12 @@ *(.sbss) *(.sbss.*) #else + _car_global_start = .; *(.car.global_data); + _car_global_end = .; #endif . = ALIGN(ARCH_POINTER_ALIGN_SIZE); - _car_global_end = .; + _ebss = .; #if CONFIG(CAR_GLOBAL_MIGRATION) _car_stack_start = .; diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h index b5db194..9e0441c 100644 --- a/src/arch/x86/include/arch/early_variables.h +++ b/src/arch/x86/include/arch/early_variables.h @@ -22,6 +22,15 @@ #if ENV_ROMSTAGE && CONFIG(CAR_GLOBAL_MIGRATION) +/* + * The _car_global_[start|end]symbols cover CAR data which is relocatable + * once memory comes online. Variables with CAR_GLOBAL decoration + * reside within this region. + */ +extern char _car_global_start[]; +extern char _car_global_end[]; +#define _car_global_size (_car_global_end - _car_global_start) + asm(".section .car.global_data,\"w\",@nobits"); asm(".previous"); #ifdef __clang__ diff --git a/src/arch/x86/include/arch/symbols.h b/src/arch/x86/include/arch/symbols.h index 5d65a7b..3f2e978 100644 --- a/src/arch/x86/include/arch/symbols.h +++ b/src/arch/x86/include/arch/symbols.h @@ -27,25 +27,26 @@ #define _car_region_size (_car_region_end - _car_region_start) /* - * This is the stack used under CONFIG_C_ENVIRONMENT_BOOTBLOCK for - * all stages that execute when cache-as-ram is up. + * This is the stack area used for all stages that execute when cache-as-ram + * is up. Area is not cleared in between stages. */ extern char _car_stack_start[]; extern char _car_stack_end[]; #define _car_stack_size (_car_stack_end - _car_stack_start) +/* + * This is the .bss section cleared between each stage. It is not + * available in romstage if CAR_GLOBAL_MIGRATION is enabled. + */ +extern char _bss[]; +extern char _ebss[]; +#define _bss_size (_ebss - _bss) + +extern char _car_unallocated_start; + extern char _car_ehci_dbg_info_start[]; extern char _car_ehci_dbg_info_end[]; #define _car_ehci_dbg_info_size \ (_car_ehci_dbg_info_end - _car_ehci_dbg_info_start) -/* - * The _car_global_[start|end]symbols cover CAR data which is relocatable - * once memory comes online. Variables with CAR_GLOBAL decoration - * reside within this region. - */ -extern char _car_global_start[]; -extern char _car_global_end[]; -#define _car_global_size (_car_global_end - _car_global_start) - #endif diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index 9a8ab5b..091fc4a 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -89,11 +89,11 @@ /* Setup bootblock stack */ mov %edx, %esp - /* clear CAR_GLOBAL area as it is not shared */ + /* clear .bss section as it is not shared */ cld xor %eax, %eax - movl $(_car_global_end), %ecx - movl $(_car_global_start), %edi + movl $(_ebss), %ecx + movl $(_bss), %edi sub %edi, %ecx shrl $2, %ecx rep stosl diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index e6da5dd..0cf2d80 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -14,6 +14,7 @@ */ #include <arch/cpu.h> +#include <arch/early_variables.h> #include <arch/romstage.h> #include <arch/symbols.h> #include <console/console.h> @@ -142,10 +143,10 @@ aupd->StackBase); printk(BIOS_SPEW, "| |\n"); printk(BIOS_SPEW, "+-------------------+ 0x%p\n", - _car_global_end); + _bss); printk(BIOS_SPEW, "| coreboot data |\n"); printk(BIOS_SPEW, "+-------------------+ 0x%p\n", - _car_stack_end); + _car_stack_start); printk(BIOS_SPEW, "| coreboot stack |\n"); printk(BIOS_SPEW, "+-------------------+ 0x80000000 - ESRAM start\n\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/35034 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36c858a4f181516d4c61f9fd1d5005c7d2c06057 Gerrit-Change-Number: 35034 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: arch/x86: Drop _car_relocatable_data symbols
by Kyösti Mälkki (Code Review) 11 Sep '19

11 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35033 ) Change subject: arch/x86: Drop _car_relocatable_data symbols ...................................................................... arch/x86: Drop _car_relocatable_data symbols These have become aliases to _car_global_[start|end]. Change-Id: Ibdcaaafdc0e4c6df4a795474903768230d41680d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/car.ld M src/arch/x86/include/arch/early_variables.h M src/arch/x86/include/arch/symbols.h M src/cpu/amd/car/post_cache_as_ram.c M src/cpu/x86/car.c M src/drivers/intel/fsp2_0/memory_init.c M src/soc/intel/quark/romstage/fsp2_0.c 7 files changed, 18 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/35033/1 diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 25b667c..822f7fd 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -68,8 +68,6 @@ . += 80; _car_ehci_dbg_info_end = .; - _car_relocatable_data_start = .; - /* _car_global_start and _car_global_end provide symbols to per-stage * variables that are not shared like the timestamp and the pre-ram * cbmem console. This is useful for clearing this area on a per-stage @@ -82,18 +80,18 @@ *(.sbss) *(.sbss.*) #else - /* .car.global_data objects only around when - * CONFIG_CAR_GLOBAL_MIGRATION is employed. */ *(.car.global_data); #endif . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _car_global_end = .; - _car_relocatable_data_end = .; #if CONFIG(CAR_GLOBAL_MIGRATION) _car_stack_start = .; _car_stack_end = _car_region_end; +#else + _car_unallocated_start = .; #endif + _car_region_end = . + CONFIG_DCACHE_RAM_SIZE - (. - _car_region_start); } diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h index 3910a82..b5db194 100644 --- a/src/arch/x86/include/arch/early_variables.h +++ b/src/arch/x86/include/arch/early_variables.h @@ -48,13 +48,13 @@ static inline size_t car_data_size(void) { - size_t car_size = _car_relocatable_data_size; - return ALIGN_UP(car_size, 64); + size_t car_size = _car_global_size; + return ALIGN(car_size, 64); } static inline size_t car_object_offset(void *ptr) { - return (char *)ptr - &_car_relocatable_data_start[0]; + return (char *)ptr - &_car_global_start[0]; } #else diff --git a/src/arch/x86/include/arch/symbols.h b/src/arch/x86/include/arch/symbols.h index 97a07c0..5d65a7b 100644 --- a/src/arch/x86/include/arch/symbols.h +++ b/src/arch/x86/include/arch/symbols.h @@ -40,16 +40,10 @@ (_car_ehci_dbg_info_end - _car_ehci_dbg_info_start) /* - * The _car_relocatable_data_[start|end] symbols cover CAR data which is - * relocatable once memory comes online. Variables with CAR_GLOBAL decoration - * reside within this region. The _car_global_[start|end] is a subset of the - * relocatable region which excludes the timestamp region because of - * intricacies in the timestamp code. + * The _car_global_[start|end]symbols cover CAR data which is relocatable + * once memory comes online. Variables with CAR_GLOBAL decoration + * reside within this region. */ -extern char _car_relocatable_data_start[]; -extern char _car_relocatable_data_end[]; -#define _car_relocatable_data_size \ - (_car_relocatable_data_end - _car_relocatable_data_start) extern char _car_global_start[]; extern char _car_global_end[]; #define _car_global_size (_car_global_end - _car_global_start) diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index dfa4c3d..bf701ff 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -107,11 +107,11 @@ void *migrated_car = (void *)(CONFIG_RAMTOP - car_size); print_car_debug("Copying data from cache to RAM..."); - memcpy_(migrated_car, _car_relocatable_data_start, car_size); + memcpy_(migrated_car, _car_global_start, car_size); print_car_debug(" Done\n"); print_car_debug("Verifying data integrity in RAM..."); - if (memcmp_(migrated_car, _car_relocatable_data_start, car_size) == 0) + if (memcmp_(migrated_car, _car_global_start, car_size) == 0) print_car_debug(" Done\n"); else print_car_debug(" FAILED\n"); diff --git a/src/cpu/x86/car.c b/src/cpu/x86/car.c index 6fc6168..62ab83b 100644 --- a/src/cpu/x86/car.c +++ b/src/cpu/x86/car.c @@ -46,8 +46,8 @@ { char *migrated_base = NULL; int offset; - void *_car_start = _car_relocatable_data_start; - void *_car_end = _car_relocatable_data_end; + void *_car_start = _car_global_start; + void *_car_end = _car_global_end; /* If the cache-as-ram has not been migrated return the pointer * passed in. */ @@ -84,8 +84,8 @@ void *car_sync_var_ptr(void *var) { void **mig_var = car_get_var_ptr(var); - void *_car_start = _car_relocatable_data_start; - void *_car_end = _car_relocatable_data_end; + void *_car_start = _car_global_start; + void *_car_end = _car_global_end; /* Not moved or migrated yet. */ if (mig_var == var) @@ -134,7 +134,7 @@ return; } - memcpy(migrated_base, _car_relocatable_data_start, car_size); + memcpy(migrated_base, _car_global_start, car_size); /* Mark that the data has been moved. */ car_migrated = ~0; diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 0797c2e..17686c8 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -404,7 +404,7 @@ /* Build up memory map of romstage address space including CAR. */ memranges_init_empty(&memmap, &freeranges[0], ARRAY_SIZE(freeranges)); memranges_insert(&memmap, (uintptr_t)_car_region_start, - _car_relocatable_data_end - _car_region_start, 0); + _car_unallocated_start - _car_region_start, 0); memranges_insert(&memmap, (uintptr_t)_program, REGION_SIZE(program), 0); if (!CONFIG(FSP_M_XIP)) diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index 0489621..e6da5dd 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -142,7 +142,7 @@ aupd->StackBase); printk(BIOS_SPEW, "| |\n"); printk(BIOS_SPEW, "+-------------------+ 0x%p\n", - _car_relocatable_data_end); + _car_global_end); printk(BIOS_SPEW, "| coreboot data |\n"); printk(BIOS_SPEW, "+-------------------+ 0x%p\n", _car_stack_end); -- To view, visit https://review.coreboot.org/c/coreboot/+/35033 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdcaaafdc0e4c6df4a795474903768230d41680d Gerrit-Change-Number: 35033 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: timestamps: Make ENV_ROMSTAGE_OR_BEFORE improvements
by Kyösti Mälkki (Code Review) 11 Sep '19

11 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35032 ) Change subject: timestamps: Make ENV_ROMSTAGE_OR_BEFORE improvements ...................................................................... timestamps: Make ENV_ROMSTAGE_OR_BEFORE improvements Keep track of the active timestamp table location using a CAR_GLOBAL variable. Done this way, the entire table can be located outside _car_relocatable_data and we just switch the pointer to CBMEM and copy the data before CAR gets torn down. TBD: This probably breaks FSP1_0 which returns to coreboot proper only after tearing down CAR. I have an idea how to fix it though. Change-Id: I87370f62db23318069b6fd56ba0d1171d619cb8a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/car.ld M src/include/timestamp.h M src/lib/timestamp.c 3 files changed, 24 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/35032/1 diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index d19818c..25b667c 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -60,17 +60,16 @@ . += 32; _epdpt = .; #endif - _car_relocatable_data_start = .; - /* The timestamp implementation relies on this storage to be around - * after migration. One of the fields indicates not to use it as the - * backing store once cbmem comes online. Therefore, this data needs - * to reside in the migrated area (between _car_relocatable_data_start - * and _car_relocatable_data_end). */ + TIMESTAMP(., 0x200) + _car_ehci_dbg_info_start = .; /* Reserve sizeof(struct ehci_dbg_info). */ . += 80; _car_ehci_dbg_info_end = .; + + _car_relocatable_data_start = .; + /* _car_global_start and _car_global_end provide symbols to per-stage * variables that are not shared like the timestamp and the pre-ram * cbmem console. This is useful for clearing this area on a per-stage diff --git a/src/include/timestamp.h b/src/include/timestamp.h index 04d5c12..1fa568c 100644 --- a/src/include/timestamp.h +++ b/src/include/timestamp.h @@ -22,11 +22,10 @@ #if CONFIG(COLLECT_TIMESTAMPS) /* * timestamp_init() needs to be called once for each of these cases: - * 1. __PRE_RAM__ (bootblock, romstage, verstage, etc) and - * 2. !__PRE_RAM__ (ramstage) + * 1. ENV_ROMSTAGE_OR_BEFORE (bootblock, romstage, verstage, etc) and + * 2. ENV_RAMSTAGE (ramstage) * The latter is taken care of by the generic coreboot infrastructure so - * it's up to the chipset/arch to call timestamp_init() in *one* of - * the __PRE_RAM__ stages. If multiple calls are made timestamps will be lost. + * it's up to the chipset/arch to call timestamp_init() in the former stages. */ void timestamp_init(uint64_t base); /* diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index 89152fd..3e9914e 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -41,7 +41,7 @@ DECLARE_OPTIONAL_REGION(timestamp); -#if defined(__PRE_RAM__) +#if ENV_ROMSTAGE_OR_BEFORE #define USE_TIMESTAMP_REGION (REGION_SIZE(timestamp) > 0) #else #define USE_TIMESTAMP_REGION 0 @@ -58,6 +58,10 @@ */ static struct timestamp_cache timestamp_cache; +/* This points to the active timestamp_table and can change within a stage. + as CBMEM comes available. */ +static struct timestamp_table *glob_ts_table CAR_GLOBAL; + enum { TIMESTAMP_CACHE_UNINITIALIZED = 0, TIMESTAMP_CACHE_INITIALIZED, @@ -87,7 +91,7 @@ } else if (USE_TIMESTAMP_REGION) { if (REGION_SIZE(timestamp) < sizeof(*ts_cache)) BUG(); - ts_cache = car_get_var_ptr((void *)_timestamp); + ts_cache = (void *)_timestamp; } return ts_cache; @@ -128,30 +132,21 @@ static struct timestamp_table *timestamp_table_get(void) { - MAYBE_STATIC_BSS struct timestamp_table *ts_table = NULL; + struct timestamp_table *ts_table; struct timestamp_cache *ts_cache; + ts_table = car_get_var(glob_ts_table); if (ts_table != NULL) return ts_table; ts_cache = timestamp_cache_get(); + if (ts_cache) + ts_table = &ts_cache->table; - if (ts_cache == NULL) { - if (HAS_CBMEM) - ts_table = cbmem_find(CBMEM_ID_TIMESTAMP); - return ts_table; - } + if (ts_table == NULL && HAS_CBMEM) + ts_table = cbmem_find(CBMEM_ID_TIMESTAMP); - /* Cache is required. */ - if (ts_cache->cache_state != TIMESTAMP_CACHE_NOT_NEEDED) - return &ts_cache->table; - - /* Cache shouldn't be used but there's no backing store. */ - if (!HAS_CBMEM) - return NULL; - - ts_table = cbmem_find(CBMEM_ID_TIMESTAMP); - + car_set_var(glob_ts_table, ts_table); return ts_table; } @@ -237,7 +232,7 @@ uint32_t i; struct timestamp_cache *ts_cache; struct timestamp_table *ts_cache_table; - struct timestamp_table *ts_cbmem_table = NULL; + struct timestamp_table *ts_cbmem_table; if (!timestamp_should_run()) return; @@ -270,6 +265,7 @@ if (ts_cbmem_table == NULL) { printk(BIOS_ERR, "ERROR: No timestamp table allocated\n"); + car_set_var(glob_ts_table, ts_cbmem_table); return; } @@ -309,6 +305,7 @@ ts_cbmem_table->tick_freq_mhz = timestamp_tick_freq_mhz(); /* Cache no longer required. */ + car_set_var(glob_ts_table, ts_cbmem_table); ts_cache_table->num_entries = 0; ts_cache->cache_state = TIMESTAMP_CACHE_NOT_NEEDED; } -- To view, visit https://review.coreboot.org/c/coreboot/+/35032 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87370f62db23318069b6fd56ba0d1171d619cb8a Gerrit-Change-Number: 35032 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

6 25

Change in coreboot[master]: src: Remobe unneeded include <arch/interrupt.h>
by HAOUAS Elyes (Code Review) 11 Sep '19

11 Sep '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34933 ) Change subject: src: Remobe unneeded include <arch/interrupt.h> ...................................................................... src: Remobe unneeded include <arch/interrupt.h> Change-Id: I3323d25b72dab2f9bc8a575ba41faf059ee1ffc4 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/intel/gma/intel_ddi.c M src/include/device/azalia_device.h M src/mainboard/apple/macbook21/mainboard.c M src/mainboard/google/beltino/mainboard.c M src/mainboard/google/butterfly/mainboard.c M src/mainboard/google/parrot/mainboard.c M src/mainboard/google/slippy/mainboard.c M src/mainboard/google/stout/mainboard.c M src/mainboard/intel/baskingridge/mainboard.c M src/mainboard/intel/bayleybay_fsp/mainboard.c M src/mainboard/intel/camelbackmountain_fsp/mainboard.c M src/mainboard/intel/emeraldlake2/mainboard.c M src/mainboard/intel/wtm2/mainboard.c M src/mainboard/kontron/986lcd-m/mainboard.c M src/mainboard/packardbell/ms2290/mainboard.c M src/mainboard/roda/rk886ex/mainboard.c M src/mainboard/samsung/lumpy/mainboard.c M src/mainboard/siemens/mc_bdx1/mainboard.c M src/mainboard/siemens/mc_tcu3/mainboard.c 19 files changed, 0 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/34933/1 diff --git a/src/drivers/intel/gma/intel_ddi.c b/src/drivers/intel/gma/intel_ddi.c index 471a5d2..3ab0022 100644 --- a/src/drivers/intel/gma/intel_ddi.c +++ b/src/drivers/intel/gma/intel_ddi.c @@ -33,7 +33,6 @@ #include <device/pci_ops.h> #include <console/console.h> #include <arch/acpi.h> -#include <arch/interrupt.h> #include <boot/coreboot_tables.h> #include <smbios.h> #include <device/pci.h> diff --git a/src/include/device/azalia_device.h b/src/include/device/azalia_device.h index 343e261..cbc5b4e 100644 --- a/src/include/device/azalia_device.h +++ b/src/include/device/azalia_device.h @@ -19,7 +19,6 @@ #include <types.h> #include <arch/acpi.h> #include <device/mmio.h> -#include <arch/interrupt.h> #include <device/device.h> void azalia_audio_init(struct device *dev); diff --git a/src/mainboard/apple/macbook21/mainboard.c b/src/mainboard/apple/macbook21/mainboard.c index 798fc12..52b4f04 100644 --- a/src/mainboard/apple/macbook21/mainboard.c +++ b/src/mainboard/apple/macbook21/mainboard.c @@ -18,7 +18,6 @@ #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#include <arch/interrupt.h> #include <northbridge/intel/i945/i945.h> #include <arch/acpigen.h> #include <drivers/intel/gma/int15.h> diff --git a/src/mainboard/google/beltino/mainboard.c b/src/mainboard/google/beltino/mainboard.c index 7bda2f6..fd74a6e 100644 --- a/src/mainboard/google/beltino/mainboard.c +++ b/src/mainboard/google/beltino/mainboard.c @@ -17,7 +17,6 @@ #include <types.h> #include <arch/acpi.h> #include <arch/io.h> -#include <arch/interrupt.h> #include <boot/coreboot_tables.h> #include <device/device.h> #include <device/pci_def.h> diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c index c298689..067ea4e 100644 --- a/src/mainboard/google/butterfly/mainboard.c +++ b/src/mainboard/google/butterfly/mainboard.c @@ -24,7 +24,6 @@ #include <fmap.h> #include <arch/acpi.h> #include <arch/io.h> -#include <arch/interrupt.h> #include <boot/coreboot_tables.h> #include "onboard.h" #include "ec.h" diff --git a/src/mainboard/google/parrot/mainboard.c b/src/mainboard/google/parrot/mainboard.c index 8c3ad63..533eb23 100644 --- a/src/mainboard/google/parrot/mainboard.c +++ b/src/mainboard/google/parrot/mainboard.c @@ -21,7 +21,6 @@ #include <drivers/intel/gma/int15.h> #include <arch/acpi.h> #include <arch/io.h> -#include <arch/interrupt.h> #include <boot/coreboot_tables.h> #include "onboard.h" #include "ec.h" diff --git a/src/mainboard/google/slippy/mainboard.c b/src/mainboard/google/slippy/mainboard.c index b98fc8a..e40d722 100644 --- a/src/mainboard/google/slippy/mainboard.c +++ b/src/mainboard/google/slippy/mainboard.c @@ -22,7 +22,6 @@ #include <drivers/intel/gma/int15.h> #include <arch/acpi.h> #include <arch/io.h> -#include <arch/interrupt.h> #include <boot/coreboot_tables.h> #include <southbridge/intel/lynxpoint/pch.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/google/stout/mainboard.c b/src/mainboard/google/stout/mainboard.c index 05de8cb..ac35602 100644 --- a/src/mainboard/google/stout/mainboard.c +++ b/src/mainboard/google/stout/mainboard.c @@ -20,7 +20,6 @@ #include <device/pci_ops.h> #include <drivers/intel/gma/int15.h> #include <arch/acpi.h> -#include <arch/interrupt.h> #include <boot/coreboot_tables.h> #include <southbridge/intel/bd82x6x/pch.h> #include <device/pci.h> diff --git a/src/mainboard/intel/baskingridge/mainboard.c b/src/mainboard/intel/baskingridge/mainboard.c index 49e66bf..6b10bb4 100644 --- a/src/mainboard/intel/baskingridge/mainboard.c +++ b/src/mainboard/intel/baskingridge/mainboard.c @@ -21,7 +21,6 @@ #include <drivers/intel/gma/int15.h> #include <arch/acpi.h> #include <arch/io.h> -#include <arch/interrupt.h> #include <boot/coreboot_tables.h> #include <southbridge/intel/lynxpoint/pch.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/intel/bayleybay_fsp/mainboard.c b/src/mainboard/intel/bayleybay_fsp/mainboard.c index 16c1844..991e851a 100644 --- a/src/mainboard/intel/bayleybay_fsp/mainboard.c +++ b/src/mainboard/intel/bayleybay_fsp/mainboard.c @@ -21,7 +21,6 @@ #if CONFIG(VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif -#include <arch/interrupt.h> #include <boot/coreboot_tables.h> /* diff --git a/src/mainboard/intel/camelbackmountain_fsp/mainboard.c b/src/mainboard/intel/camelbackmountain_fsp/mainboard.c index ee9f36e..4bd71bf 100644 --- a/src/mainboard/intel/camelbackmountain_fsp/mainboard.c +++ b/src/mainboard/intel/camelbackmountain_fsp/mainboard.c @@ -21,7 +21,6 @@ #if CONFIG(VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif -#include <arch/interrupt.h> #include <boot/coreboot_tables.h> /* diff --git a/src/mainboard/intel/emeraldlake2/mainboard.c b/src/mainboard/intel/emeraldlake2/mainboard.c index d07da83..848f6de 100644 --- a/src/mainboard/intel/emeraldlake2/mainboard.c +++ b/src/mainboard/intel/emeraldlake2/mainboard.c @@ -20,7 +20,6 @@ #include <device/pci_ops.h> #include <drivers/intel/gma/int15.h> #include <arch/acpi.h> -#include <arch/interrupt.h> #include <boot/coreboot_tables.h> #include <southbridge/intel/bd82x6x/pch.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/intel/wtm2/mainboard.c b/src/mainboard/intel/wtm2/mainboard.c index 4bfd039..21321ac 100644 --- a/src/mainboard/intel/wtm2/mainboard.c +++ b/src/mainboard/intel/wtm2/mainboard.c @@ -21,7 +21,6 @@ #include <drivers/intel/gma/int15.h> #include <arch/acpi.h> #include <arch/io.h> -#include <arch/interrupt.h> #include <boot/coreboot_tables.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/kontron/986lcd-m/mainboard.c b/src/mainboard/kontron/986lcd-m/mainboard.c index 73d5997..85b704e 100644 --- a/src/mainboard/kontron/986lcd-m/mainboard.c +++ b/src/mainboard/kontron/986lcd-m/mainboard.c @@ -21,7 +21,6 @@ #include <drivers/intel/gma/int15.h> #include <pc80/mc146818rtc.h> #include <arch/io.h> -#include <arch/interrupt.h> /* Hardware Monitor */ diff --git a/src/mainboard/packardbell/ms2290/mainboard.c b/src/mainboard/packardbell/ms2290/mainboard.c index 785e6e8..508488a 100644 --- a/src/mainboard/packardbell/ms2290/mainboard.c +++ b/src/mainboard/packardbell/ms2290/mainboard.c @@ -25,7 +25,6 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <ec/acpi/ec.h> #include <drivers/intel/gma/int15.h> -#include <arch/interrupt.h> #include <pc80/keyboard.h> #include <cpu/x86/lapic.h> #include <device/pci.h> diff --git a/src/mainboard/roda/rk886ex/mainboard.c b/src/mainboard/roda/rk886ex/mainboard.c index 91c11d5..922eba2 100644 --- a/src/mainboard/roda/rk886ex/mainboard.c +++ b/src/mainboard/roda/rk886ex/mainboard.c @@ -17,7 +17,6 @@ #include <console/console.h> #include <device/device.h> #include <arch/io.h> -#include <arch/interrupt.h> #include <drivers/intel/gma/int15.h> #include <ec/acpi/ec.h> diff --git a/src/mainboard/samsung/lumpy/mainboard.c b/src/mainboard/samsung/lumpy/mainboard.c index 8664217..893830e 100644 --- a/src/mainboard/samsung/lumpy/mainboard.c +++ b/src/mainboard/samsung/lumpy/mainboard.c @@ -21,7 +21,6 @@ #include <device/pci_ops.h> #include <drivers/intel/gma/int15.h> #include <arch/acpi.h> -#include <arch/interrupt.h> #include <boot/coreboot_tables.h> #include <ec/smsc/mec1308/ec.h> #include "ec.h" diff --git a/src/mainboard/siemens/mc_bdx1/mainboard.c b/src/mainboard/siemens/mc_bdx1/mainboard.c index 2bb9852..5cef53c 100644 --- a/src/mainboard/siemens/mc_bdx1/mainboard.c +++ b/src/mainboard/siemens/mc_bdx1/mainboard.c @@ -27,7 +27,6 @@ #include <x86emu/x86emu.h> #endif #include <device/mmio.h> -#include <arch/interrupt.h> #include <boot/coreboot_tables.h> #include <hwilib.h> #include <i210.h> diff --git a/src/mainboard/siemens/mc_tcu3/mainboard.c b/src/mainboard/siemens/mc_tcu3/mainboard.c index 169b04d..a50a53e 100644 --- a/src/mainboard/siemens/mc_tcu3/mainboard.c +++ b/src/mainboard/siemens/mc_tcu3/mainboard.c @@ -22,7 +22,6 @@ #if CONFIG(VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif -#include <arch/interrupt.h> #include <boot/coreboot_tables.h> #include <hwilib.h> #include <i210.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/34933 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3323d25b72dab2f9bc8a575ba41faf059ee1ffc4 Gerrit-Change-Number: 34933 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mediatek/mt8183: support get current DRAM type
by huayang duan (Code Review) 10 Sep '19

10 Sep '19

huayang duan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34433 ) Change subject: mediatek/mt8183: support get current DRAM type ...................................................................... mediatek/mt8183: support get current DRAM type read the ramid to get the DRAM type of current platform BUG=b:80501386 BRANCH=none TEST=Memory test pass on EMCP platform Change-Id: Icf875427347418f796cbf193070bf047844d2267 Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/emi.h 2 files changed, 30 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/34433/1 diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index 937d06d..084a7a3 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <boardid.h> #include <device/mmio.h> #include <soc/emi.h> #include <soc/infracfg.h> @@ -42,6 +43,30 @@ return read32(&mt8183_infracfg->dramc_wbr); } +int get_dram_type(void) +{ + uint32_t ramcode = ram_code(); + uint32_t dram_type; + + switch (ramcode) { + case 0: + case 1: + case 2: + dram_type = DRAM_TYPE_DISCRETE; + break; + case 3: + case 4: + case 5: + case 6: + case 7: + default: + dram_type = DRAM_TYPE_EMCP; + break; + } + + return dram_type; +} + static u64 get_ch_rank_size(u8 chn, u8 rank) { u32 shift_for_16bit = 1; diff --git a/src/soc/mediatek/mt8183/include/soc/emi.h b/src/soc/mediatek/mt8183/include/soc/emi.h index 2c04a50..f075429 100644 --- a/src/soc/mediatek/mt8183/include/soc/emi.h +++ b/src/soc/mediatek/mt8183/include/soc/emi.h @@ -33,6 +33,10 @@ u16 delay_cell_unit; }; +enum { + DRAM_TYPE_DISCRETE, + DRAM_TYPE_EMCP, +}; extern const u8 phy_mapping[CHANNEL_MAX][16]; int complex_mem_test(u8 *start, unsigned int len); @@ -41,5 +45,6 @@ void enable_emi_dcm(void); void mt_set_emi(const struct sdram_params *params); void mt_mem_init(const struct sdram_params *params); +int get_dram_type(void); #endif /* SOC_MEDIATEK_MT8183_EMI_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/34433 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf875427347418f796cbf193070bf047844d2267 Gerrit-Change-Number: 34433 Gerrit-PatchSet: 1 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-MessageType: newchange

9 56

Change in coreboot[master]: mediatek/mt8183: Add new config for EMCP DDR
by huayang duan (Code Review) 10 Sep '19

10 Sep '19

huayang duan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34989 ) Change subject: mediatek/mt8183: Add new config for EMCP DDR ...................................................................... mediatek/mt8183: Add new config for EMCP DDR Devices using eMCP may run in a high DRAM frequency (e.g., 3600Mbs) while discrete DRAM can only run at 3200Mbps. A new Kconfig is introduced so mainboard can select right config if the board support eMCP or not. BUG=b:80501386 BRANCH=none TEST=Boots correctly and stress test pass on Kukui. Change-Id: I9b73c8b512db5104896ea0d330d56e63eb50a44b Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/soc/mediatek/mt8183/Kconfig 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/34989/1 diff --git a/src/soc/mediatek/mt8183/Kconfig b/src/soc/mediatek/mt8183/Kconfig index c60cdea..a2f7a04 100644 --- a/src/soc/mediatek/mt8183/Kconfig +++ b/src/soc/mediatek/mt8183/Kconfig @@ -22,6 +22,12 @@ help This option enables additional DRAM related debug messages. +config MT8183_DRAM_EMCP + bool + default n + help + The EMCP platform should select this config for using different DRAM frequency. + config MEMORY_TEST bool default y -- To view, visit https://review.coreboot.org/c/coreboot/+/34989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b73c8b512db5104896ea0d330d56e63eb50a44b Gerrit-Change-Number: 34989 Gerrit-PatchSet: 1 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: huayang duan <huayangduan(a)gmail.com> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: crossgcc: Upgrade CMake to 3.15.2
by HAOUAS Elyes (Code Review) 10 Sep '19

10 Sep '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34895 ) Change subject: crossgcc: Upgrade CMake to 3.15.2 ...................................................................... crossgcc: Upgrade CMake to 3.15.2 Changes: https://cmake.org/cmake/help/v3.15/release/3.15.html "In CMake 3.15.0 and 3.15.1 the CMAKE_FIND_PACKAGE_PREFER_CONFIG variable caused the find_package() command to fail on a missing package even without the REQUIRED option. This has been fixed." Change-Id: Id3283b4a091a5a8afd76235059636bba1c238f0f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/sum/cmake-3.15.0.tar.gz.cksum A util/crossgcc/sum/cmake-3.15.2.tar.gz.cksum 3 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/34895/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index c7f63c3b..5754b09 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -60,7 +60,7 @@ # CLANG version number CLANG_VERSION=8.0.0 MAKE_VERSION=4.2.1 -CMAKE_VERSION=3.15.0 +CMAKE_VERSION=3.15.2 NASM_VERSION=2.14.02 # GCC toolchain archive locations diff --git a/util/crossgcc/sum/cmake-3.15.0.tar.gz.cksum b/util/crossgcc/sum/cmake-3.15.0.tar.gz.cksum deleted file mode 100644 index 3ec1605..0000000 --- a/util/crossgcc/sum/cmake-3.15.0.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -0a1c3870d566061da8b9ed02bbfe17a39c7bf3cd tarballs/cmake-3.15.0.tar.gz diff --git a/util/crossgcc/sum/cmake-3.15.2.tar.gz.cksum b/util/crossgcc/sum/cmake-3.15.2.tar.gz.cksum new file mode 100644 index 0000000..55f5572 --- /dev/null +++ b/util/crossgcc/sum/cmake-3.15.2.tar.gz.cksum @@ -0,0 +1 @@ +7561a018f41d6adc0efbdd399904172abb4968ec tarballs/cmake-3.15.2.tar.gz -- To view, visit https://review.coreboot.org/c/coreboot/+/34895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3283b4a091a5a8afd76235059636bba1c238f0f Gerrit-Change-Number: 34895 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 4

Change in em100[master]: Automatically select the right FPGA firmware for 1.8/3.3V
by Martin Roth (Code Review) 10 Sep '19

10 Sep '19

Hello Raul Rangel, I'd like you to do a code review. Please visit https://review.coreboot.org/c/em100/+/34830 to review the following change. Change subject: Automatically select the right FPGA firmware for 1.8/3.3V ...................................................................... Automatically select the right FPGA firmware for 1.8/3.3V With the -G2 variant we can automatically select the right voltage. Do this instead of just giving up. For the original em100 this will produce an error, with a 2s delay. Success (new unit): will emulate 'W25Q128FW' MCU version: 3.03 FPGA version: 2.10 (3.3V) Serial number: DP142535 SPI flash database: 4.3.01 EM100Pro currently stopped EM100Pro hold pin currently low Stopped EM100Pro Sending flash chip configuration Voltage set to 1.8 Chip set to W25Q128FW Hold pin state set to low Sent 2097152 bytes of 16777216 ... Failure (old unit): will emulate 'GD25Q32B' MCU version: 2.27 FPGA version: 0.85 (1.8V) Serial number: DP142073 SPI flash database: 4.3.01 EM100Pro currently running EM100Pro hold pin currently low Stopped EM100Pro Sending flash chip configuration Invalid voltage response: 0x12 (expected 0x21) Error: The current FPGA firmware (1.8V) does not support GigaDevice GD25Q32B (3.3V) Failed configuring chip type. Change-Id: I55596b9857c1f340d532acf5d261800a654068c6 Signed-off-by: Simon Glass <sjg(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1395949 Reviewed-by: Raul E Rangel <rrangel(a)chromium.org> --- M em100.c 1 file changed, 12 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/30/34830/1 diff --git a/em100.c b/em100.c index 01fe761..fcd7bcd 100644 --- a/em100.c +++ b/em100.c @@ -510,7 +510,8 @@ */ int result = 0; int i; - int fpga_voltage, chip_voltage = 0, wrong_voltage = 0; + int fpga_voltage, chip_voltage = 0; + int req_voltage = 0; printf("Sending flash chip configuration\n"); @@ -528,22 +529,25 @@ case 1601: /* 1.65V-2V */ case 1800: if (fpga_voltage == 3300) - wrong_voltage = 1; + req_voltage = 18; break; case 2500: /* supported by both 1.8V and 3.3V FPGA */ break; case 3300: if (fpga_voltage == 1800) - wrong_voltage = 1; + req_voltage = 33; } break; } - if (wrong_voltage) { - printf("Error: The current FPGA firmware (%.1fV) does not " - "support %s %s (%.1fV)\n", (float)fpga_voltage/1000, - desc->vendor, desc->name, (float)chip_voltage/1000); - return 0; + if (req_voltage) { + if (!set_fpga_voltage(em100, req_voltage)) { + printf("Error: The current FPGA firmware (%.1fV) does " + "not support %s %s (%.1fV)\n", + (float)fpga_voltage / 1000, desc->vendor, + desc->name, (float)chip_voltage / 1000); + return 0; + } } for (i = 0; i < desc->init_len; i++) { -- To view, visit https://review.coreboot.org/c/em100/+/34830 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: I55596b9857c1f340d532acf5d261800a654068c6 Gerrit-Change-Number: 34830 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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