coreboot-gerrit August 2019

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Change in ...coreboot[master]: mb/lenovo/t430s: Open PCIe port #5 for Thunderbolt controller
by Bill XIE (Code Review) 17 Sep '19

17 Sep '19

Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31631 Change subject: mb/lenovo/t430s: Open PCIe port #5 for Thunderbolt controller ...................................................................... mb/lenovo/t430s: Open PCIe port #5 for Thunderbolt controller Some T430s variants has a Thunderbolt controller wired to PCIe port #5, so it had better be left on for T430s. (T431s do not have that) The controller hotplugs itself to the chipset when a downstream device is hotplugged into it, so the hotplug capability should be enabled on PCIe port #5. Change-Id: I61f41db100f398069e50e2da8a378b3a8d1c84bf Signed-off-by: Bill XIE <persmule(a)gmail.com> --- M src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/31631/1 diff --git a/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb b/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb index ff30702..ee94979 100644 --- a/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb +++ b/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb @@ -1,6 +1,11 @@ chip northbridge/intel/sandybridge device domain 0 on chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + # Enable hotplug on Port 5 for Thunderbolt controller + register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 1, 0, 0, 0 }" + device pci 1c.4 on + subsystemid 0x17aa 0x21fb + end # PCIe Port #5 Thunderbolt controller device pci 1f.0 on chip ec/lenovo/h8 register "has_bdc_detection" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/31631 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61f41db100f398069e50e2da8a378b3a8d1c84bf Gerrit-Change-Number: 31631 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [WIP] binaryPI: Drop PSP Secure OS from build
by Kyösti Mälkki (Code Review) 17 Sep '19

17 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31075 Change subject: [WIP] binaryPI: Drop PSP Secure OS from build ...................................................................... [WIP] binaryPI: Drop PSP Secure OS from build For pcengines/apu2 variants we do not even send DRAM ready message to PSP. Possibly some GFX/DRM depends of running PSP but these devices are headless. And we don't support fTPM inside PSP either. Reduces blob footprint in SPI from 466 KiB to 234KiB. Change-Id: I803722171cba9b3601fb0b4a2c0e984566f435ab Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/amd/pi/hudson/Makefile.inc 1 file changed, 7 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/31075/1 diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index e990f9d..81fe7ff 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -85,13 +85,12 @@ FIRMWARE_TYPE= PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader.Bypass.sbin -PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecovery.sbin -PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs.sbin -PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATE)/trustlets.bin -TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/Trustlet.tkn.cert +#PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecovery.sbin +#PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs.sbin +#PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATE)/trustlets.bin +#TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/Trustlet.tkn.cert endif - ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) FIRMWARE_LOCATE=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE))) FIRMWARE_TYPE=CZ @@ -104,12 +103,12 @@ SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_CZ.sbin endif -PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RtmPubSigned$(FIRMWARE_TYPE).key -PSPNVRAM_FILE=$(top)/$(FIRMWARE_LOCATE)/PspNvram$(FIRMWARE_TYPE).bin +#PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RtmPubSigned$(FIRMWARE_TYPE).key +#PSPNVRAM_FILE=$(top)/$(FIRMWARE_LOCATE)/PspNvram$(FIRMWARE_TYPE).bin SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware$(FIRMWARE_TYPE).sbin SMUFWM_FN_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware$(FIRMWARE_TYPE)_FN.sbin SMUSCS_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuScs$(FIRMWARE_TYPE).bin -PSPSECUREDEBUG_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureDebug$(FIRMWARE_TYPE).Key +#PSPSECUREDEBUG_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureDebug$(FIRMWARE_TYPE).Key endif -- To view, visit https://review.coreboot.org/c/coreboot/+/31075 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I803722171cba9b3601fb0b4a2c0e984566f435ab Gerrit-Change-Number: 31075 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [WIP] binaryPI: Move Hudson firmware higher in CBFS
by Kyösti Mälkki (Code Review) 17 Sep '19

17 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31074 Change subject: [WIP] binaryPI: Move Hudson firmware higher in CBFS ...................................................................... [WIP] binaryPI: Move Hudson firmware higher in CBFS Move it above 'AGESA' to increase the maximum continuous free space in CBFS from 5.3 MiB to 5.8 MiB. Also fixes build for cases where CBFS_SIZE < ROM_SIZE, thus allowing FMAP regions. NOTE: Due to off-by-one error in binaryPI, offset 0xFFFA0000 that amdfwtool advertises fails for xHCI firmware loading. Change-Id: Ic78520f4248f0943769e66a8825911c0ddcc368c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/amd/pi/hudson/Makefile.inc 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/31074/1 diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 22e38c7..e990f9d 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -72,7 +72,11 @@ # # EC ROM should be 64K aligned. +ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) HUDSON_FWM_POSITION=$(call int-add, $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) 0x20000 1) +else +HUDSON_FWM_POSITION=0xfff20000 +endif ifeq ($(CONFIG_HUDSON_PSP), y) @@ -191,6 +195,7 @@ $(OPT_2SMUFIRMWARE2_FN_FILE) \ $(OPT_2SMUSCS_FILE) \ --flashsize $(CONFIG_ROM_SIZE) \ + --location $(HUDSON_FWM_POSITION) \ --output $@ ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) -- To view, visit https://review.coreboot.org/c/coreboot/+/31074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic78520f4248f0943769e66a8825911c0ddcc368c Gerrit-Change-Number: 31074 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [WIP] binaryPI: Refactor Makefile for PSP directory
by Kyösti Mälkki (Code Review) 17 Sep '19

17 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31073 Change subject: [WIP] binaryPI: Refactor Makefile for PSP directory ...................................................................... [WIP] binaryPI: Refactor Makefile for PSP directory Change-Id: I3c2d528519ac26b24159a46400f232d6acd629e9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/amd/pi/hudson/Makefile.inc 1 file changed, 15 insertions(+), 53 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/31073/1 diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index c7cd757..22e38c7 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -74,77 +74,39 @@ HUDSON_FWM_POSITION=$(call int-add, $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) 0x20000 1) -## ifeq ($(CONFIG_HUDSON_PSP), y) -## -### 0 -## ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) FIRMWARE_LOCATE=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE))) FIRMWARE_TYPE= + +PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader.Bypass.sbin +PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecovery.sbin +PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs.sbin +PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATE)/trustlets.bin +TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/Trustlet.tkn.cert endif -## + + ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) FIRMWARE_LOCATE=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE))) FIRMWARE_TYPE=CZ + +PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader_prod_CZ.sbin +PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecoveryBootLoader_prod_CZ.sbin +PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs_prod_CZ.csbin +PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspTrustlets_prod_CZ.cbin +TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/TrustletKey_prod_CZ.sbin +SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_CZ.sbin endif -###5 PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RtmPubSigned$(FIRMWARE_TYPE).key -###1 -ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) -PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader$(FIRMWARE_TYPE).Bypass.sbin -else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) -PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader_prod_$(FIRMWARE_TYPE).sbin -endif - -###3 -ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) -PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecovery$(FIRMWARE_TYPE).sbin -else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) -PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecoveryBootLoader_prod_$(FIRMWARE_TYPE).sbin -endif - -###2 -ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) -PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs$(FIRMWARE_TYPE).sbin -else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) -PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs_prod_$(FIRMWARE_TYPE).csbin -endif - -###4 PSPNVRAM_FILE=$(top)/$(FIRMWARE_LOCATE)/PspNvram$(FIRMWARE_TYPE).bin - -###8 SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware$(FIRMWARE_TYPE).sbin SMUFWM_FN_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware$(FIRMWARE_TYPE)_FN.sbin - -###95 SMUSCS_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuScs$(FIRMWARE_TYPE).bin - -###9 PSPSECUREDEBUG_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureDebug$(FIRMWARE_TYPE).Key -###12 -ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) -PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATE)/trustlets.bin -else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) -PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspTrustlets_prod_$(FIRMWARE_TYPE).cbin -endif - -###13 -ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) -TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/Trustlet.tkn.cert -else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) -TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/TrustletKey_prod_$(FIRMWARE_TYPE).sbin -endif - -###18 -ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) -SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_$(FIRMWARE_TYPE).sbin -endif - endif add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) -- To view, visit https://review.coreboot.org/c/coreboot/+/31073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c2d528519ac26b24159a46400f232d6acd629e9 Gerrit-Change-Number: 31073 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: google/kukui: Pass reset gpio parameter to BL31
by Tristan Hsieh (Code Review) 17 Sep '19

17 Sep '19

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31605 Change subject: google/kukui: Pass reset gpio parameter to BL31 ...................................................................... google/kukui: Pass reset gpio parameter to BL31 To support gpio reset SoC, we need to pass the reset gpio parameter to BL31. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui and ATF(BL31) can get this parameter. Change-Id: Iefa70dc0714a9283a79f97d475b07ac047f5f3b0 Signed-off-by: Tristan Shieh <tristan.shieh(a)mediatek.com> --- M src/mainboard/google/kukui/mainboard.c 1 file changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/31605/1 diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index e1d8f5f..489762d 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -14,10 +14,13 @@ */ #include <device/device.h> +#include <soc/bl31_plat_params.h> #include <soc/gpio.h> #include <soc/mmu_operations.h> #include <soc/usb.h> +#include "gpio.h" + static void configure_emmc(void) { const gpio_t emmc_pin[] = { @@ -37,10 +40,28 @@ setup_usb_host(); } +static void register_reset_to_bl31(void) +{ + static struct bl31_gpio_param param_reset = { + .h = { + .type = PARAM_RESET, + }, + .gpio = { + .polarity = BL31_GPIO_LEVEL_HIGH, + .direction = BL31_GPIO_DIR_OUT, + }, + }; + + param_reset.gpio.index = GPIO_RESET.id; + register_bl31_param(&param_reset.h); +} + static void mainboard_init(struct device *dev) { configure_emmc(); configure_usb(); + + register_reset_to_bl31(); } static void mainboard_enable(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/31605 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iefa70dc0714a9283a79f97d475b07ac047f5f3b0 Gerrit-Change-Number: 31605 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/Kconfig: increase size if using flattened image tree
by Marty E. Plummer (Code Review) 16 Sep '19

16 Sep '19

Marty E. Plummer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32392 Change subject: src/Kconfig: increase size if using flattened image tree ...................................................................... src/Kconfig: increase size if using flattened image tree FIT support takes more heap memory than most coreboot payloads. Change-Id: Id17f25e94d97e937b0e9a9cee3dd1a8aef1d525d Signed-off-by: Marty E. Plummer <hanetzer(a)startmail.com> --- M src/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/32392/1 diff --git a/src/Kconfig b/src/Kconfig index 62b3818..90c724e 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -428,6 +428,7 @@ config HEAP_SIZE hex + default 0x100000 if FLATTENED_DEVICE_TREE default 0x4000 config STACK_SIZE -- To view, visit https://review.coreboot.org/c/coreboot/+/32392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id17f25e94d97e937b0e9a9cee3dd1a8aef1d525d Gerrit-Change-Number: 32392 Gerrit-PatchSet: 1 Gerrit-Owner: Marty E. Plummer <hanetzer(a)startmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/intel/i82801ix: Allow to compile with flashconsole
by Nico Huber (Code Review) 16 Sep '19

16 Sep '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31269 Change subject: sb/intel/i82801ix: Allow to compile with flashconsole ...................................................................... sb/intel/i82801ix: Allow to compile with flashconsole Change-Id: Ib8c5a1853b21fc0b70b688f6176ee2edaf4dbdaa Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/southbridge/intel/i82801ix/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/31269/1 diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index 571778a..0787c94 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -26,6 +26,7 @@ select HAVE_USBDEBUG_OPTIONS select SOUTHBRIDGE_INTEL_COMMON_GPIO select SOUTHBRIDGE_INTEL_COMMON_SMM + select SOUTHBRIDGE_INTEL_COMMON_SPI if CONSOLE_SPI_FLASH select INTEL_DESCRIPTOR_MODE_CAPABLE select ACPI_INTEL_HARDWARE_SLEEP_VALUES -- To view, visit https://review.coreboot.org/c/coreboot/+/31269 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8c5a1853b21fc0b70b688f6176ee2edaf4dbdaa Gerrit-Change-Number: 31269 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: 3rdparty/chromeec: Update to latest master
by Nico Huber (Code Review) 16 Sep '19

16 Sep '19

Hello HAOUAS Elyes, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30679 to review the following change. Change subject: 3rdparty/chromeec: Update to latest master ...................................................................... 3rdparty/chromeec: Update to latest master It's been some time and there are 1420 new commits. Including one that allows reproducible builds \o/ and one that breaks building with empty $(CC) :-/ Change-Id: I5e81d5a2f1018481b9103fc5a1f4b8c72fb9deec Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M 3rdparty/chromeec M src/ec/google/chromeec/Makefile.inc 2 files changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/30679/1 diff --git a/3rdparty/chromeec b/3rdparty/chromeec index 11bd4c0..860fe29 160000 --- a/3rdparty/chromeec +++ b/3rdparty/chromeec @@ -1 +1 @@ -Subproject commit 11bd4c0f4d11357ab830982d7dec164813c886dd +Subproject commit 860fe2962d40ee901369d1dc67f4aa7a7a42ba4d diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc index 85e2599..f005cbc 100644 --- a/src/ec/google/chromeec/Makefile.inc +++ b/src/ec/google/chromeec/Makefile.inc @@ -62,6 +62,8 @@ $(obj)/mainboard/$(MAINBOARDDIR)/ecrw: $(MAKE) -C $(CHROMEEC_SOURCE) $(if $(CONFIG_CCACHE),,CCACHE=) \ out=$(abspath $(obj)/external/chromeec/$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDNAME)) \ + REPRODUCIBLE_BUILD=1 \ + CC=$(GCC_CC_arm) \ CROSS_COMPILE=$(subst -cpp,-,$(CPP_arm)) \ HOST_CROSS_COMPILE= \ BOARD=$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDNAME) \ @@ -99,6 +101,8 @@ $(obj)/mainboard/$(MAINBOARDDIR)/pdrw: $(MAKE) -C $(CHROMEEC_SOURCE) $(if $(CONFIG_CCACHE),,CCACHE=) \ out=$(abspath $(obj)/external/chromeec/$(CONFIG_EC_GOOGLE_CHROMEEC_PD_BOARDNAME)) \ + REPRODUCIBLE_BUILD=1 \ + CC=$(GCC_CC_arm) \ CROSS_COMPILE=$(subst -cpp,-,$(CPP_arm)) \ HOST_CROSS_COMPILE= \ BOARD=$(CONFIG_EC_GOOGLE_CHROMEEC_PD_BOARDNAME) \ -- To view, visit https://review.coreboot.org/c/coreboot/+/30679 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e81d5a2f1018481b9103fc5a1f4b8c72fb9deec Gerrit-Change-Number: 30679 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/up/squared: Do RAM config based on SKU ID
by Felix Singer (Code Review) 16 Sep '19

16 Sep '19

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34838 ) Change subject: mb/up/squared: Do RAM config based on SKU ID ...................................................................... mb/up/squared: Do RAM config based on SKU ID Change-Id: Ic121652213d5b1f65cff2f3096e919a3cf88db72 Signed-off-by: Felix Singer <felix.singer(a)9elements.com> --- M src/mainboard/up/squared/romstage.c A src/mainboard/up/squared/romstage.h 2 files changed, 109 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/34838/1 diff --git a/src/mainboard/up/squared/romstage.c b/src/mainboard/up/squared/romstage.c index 2cfaa00..c1c52ad 100644 --- a/src/mainboard/up/squared/romstage.c +++ b/src/mainboard/up/squared/romstage.c @@ -15,10 +15,20 @@ #include <string.h> #include <soc/romstage.h> +#include <soc/gpio_apl.h> #include <fsp/api.h> #include <FspmUpd.h> #include <console/console.h> +#include <gpio.h> #include "gpio.h" +#include "romstage.h" + +/* + * Offsets: + * - GPIO_27: 0xd8 + * - GPIO_28: 0xe0 + */ +const uint8_t memory_skuid_pads[] = { GPIO_27, GPIO_28 }; static const uint8_t ch0_bit_swizzling[] = { 0x0D, 0x0A, 0x08, 0x0B, 0x0C, 0x0F, 0x0E, 0x09, @@ -48,49 +58,101 @@ 0x19, 0x1F, 0x1D, 0x1B, 0x1E, 0x18, 0x1C, 0x1A }; - void mainboard_memory_init_params(FSPM_UPD *memupd) { printk(BIOS_DEBUG, "MAINBOARD: %s/%s called\n", __FILE__, __func__); + FSP_M_CONFIG *config = &memupd->FspmConfig; + + uint8_t memory_skuid = get_memory_skuid(); + + switch (memory_skuid) { + case 0: /* 2GB */ + config->DualRankSupportEnable = 0; + config->Ch0_RankEnable = 1; + config->Ch0_DramDensity = 2; + config->Ch1_RankEnable = 1; + config->Ch1_DramDensity = 2; + config->Ch2_RankEnable = 0; + config->Ch3_RankEnable = 0; + break; + case 1: /* 4GB */ + config->DualRankSupportEnable = 1; + config->Ch0_RankEnable = 1; + config->Ch0_DramDensity = 2; + config->Ch1_RankEnable = 1; + config->Ch1_DramDensity = 2; + config->Ch2_RankEnable = 1; + config->Ch2_DramDensity = 2; + config->Ch3_RankEnable = 1; + config->Ch3_DramDensity = 2; + break; + case 2: /* 8GB */ + config->DualRankSupportEnable = 1; + config->Ch0_RankEnable = 3; + config->Ch0_DramDensity = 2; + config->Ch1_RankEnable = 3; + config->Ch1_DramDensity = 2; + config->Ch2_RankEnable = 3; + config->Ch2_DramDensity = 2; + config->Ch3_RankEnable = 3; + config->Ch3_DramDensity = 2; + break; + default: + break; + } + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); - memupd->FspmConfig.Package = 0x1; // 0x0 - memupd->FspmConfig.Profile = 0xB; // 0x19 - memupd->FspmConfig.MemoryDown = 0x1; // 0x0 - memupd->FspmConfig.DDR3LPageSize = 0x0; // 0x1 - memupd->FspmConfig.DIMM0SPDAddress = 0x0; // 0xa0 - memupd->FspmConfig.DIMM1SPDAddress = 0x0; // 0xa4 - memupd->FspmConfig.RmtCheckRun = 0x3; // 0x0 - memupd->FspmConfig.RmtMarginCheckScaleHighThreshold = 0xC8; // 0x0 - memupd->FspmConfig.EnhancePort8xhDecoding = 0x0; // 0x1 - memupd->FspmConfig.NpkEn = 0x0; // 0x3 - memupd->FspmConfig.PrimaryVideoAdaptor = 0x2; // 0x0 + config->Package = 0x1; // 0x0 + config->Profile = 0xB; // 0x19 + config->MemoryDown = 0x1; // 0x0 + config->DDR3LPageSize = 0x0; // 0x1 + config->DIMM0SPDAddress = 0x0; // 0xa0 + config->DIMM1SPDAddress = 0x0; // 0xa4 + config->RmtCheckRun = 0x3; // 0x0 + config->RmtMarginCheckScaleHighThreshold = 0xC8; // 0x0 + config->EnhancePort8xhDecoding = 0x0; // 0x1 + config->NpkEn = 0x0; // 0x3 + config->PrimaryVideoAdaptor = 0x2; // 0x0 - memupd->FspmConfig.Ch0_RankEnable = 0x1; // 0x0 - memupd->FspmConfig.Ch0_DeviceWidth = 0x1; // 0x0 - memupd->FspmConfig.Ch0_DramDensity = 0x2; // 0x0 - memupd->FspmConfig.Ch0_Option = 0x3; // 0x0 - memupd->FspmConfig.Ch1_RankEnable = 0x1; // 0x0 - memupd->FspmConfig.Ch1_DeviceWidth = 0x1; // 0x0 - memupd->FspmConfig.Ch1_DramDensity = 0x2; // 0x0 - memupd->FspmConfig.Ch1_Option = 0x3; // 0x0 - memupd->FspmConfig.Ch2_RankEnable = 0x1; // 0x0 - memupd->FspmConfig.Ch2_DeviceWidth = 0x1; // 0x0 - memupd->FspmConfig.Ch2_DramDensity = 0x2; // 0x0 - memupd->FspmConfig.Ch2_Option = 0x3; // 0x0 - memupd->FspmConfig.Ch3_RankEnable = 0x1; // 0x0 - memupd->FspmConfig.Ch3_DeviceWidth = 0x1; // 0x0 - memupd->FspmConfig.Ch3_DramDensity = 0x2; // 0x0 - memupd->FspmConfig.Ch3_Option = 0x3; // 0x0 - memupd->FspmConfig.StartTimerTickerOfPfetAssert = 0x4E20; // 0x0 + config->Ch0_RankEnable = 0x1; // 0x0 + config->Ch0_DeviceWidth = 0x1; // 0x0 + config->Ch0_DramDensity = 0x2; // 0x0 + config->Ch0_Option = 0x3; // 0x0 + config->Ch1_RankEnable = 0x1; // 0x0 + config->Ch1_DeviceWidth = 0x1; // 0x0 + config->Ch1_DramDensity = 0x2; // 0x0 + config->Ch1_Option = 0x3; // 0x0 + config->Ch2_RankEnable = 0x1; // 0x0 + config->Ch2_DeviceWidth = 0x1; // 0x0 + config->Ch2_DramDensity = 0x2; // 0x0 + config->Ch2_Option = 0x3; // 0x0 + config->Ch3_RankEnable = 0x1; // 0x0 + config->Ch3_DeviceWidth = 0x1; // 0x0 + config->Ch3_DramDensity = 0x2; // 0x0 + config->Ch3_Option = 0x3; // 0x0 + config->StartTimerTickerOfPfetAssert = 0x4E20; // 0x0 - memcpy(memupd->FspmConfig.Ch0_Bit_swizzling, &ch0_bit_swizzling, + memcpy(config->Ch0_Bit_swizzling, &ch0_bit_swizzling, sizeof(ch0_bit_swizzling)); - memcpy(memupd->FspmConfig.Ch1_Bit_swizzling, &ch1_bit_swizzling, + memcpy(config->Ch1_Bit_swizzling, &ch1_bit_swizzling, sizeof(ch1_bit_swizzling)); - memcpy(memupd->FspmConfig.Ch2_Bit_swizzling, &ch2_bit_swizzling, + memcpy(config->Ch2_Bit_swizzling, &ch2_bit_swizzling, sizeof(ch2_bit_swizzling)); - memcpy(memupd->FspmConfig.Ch3_Bit_swizzling, &ch3_bit_swizzling, + memcpy(config->Ch3_Bit_swizzling, &ch3_bit_swizzling, sizeof(ch3_bit_swizzling)); } + +uint8_t get_memory_skuid(void) +{ + uint8_t memory_skuid = 0; + + for (uint8_t i = 0; i < ARRAY_SIZE(memory_skuid_pads); i++) { + uint32_t gpio_value = gpio_get(memory_skuid_pads[i]); + uint8_t rx_state = gpio_value & 0x2; + memory_skuid |= rx_state << i; + } + memory_skuid = memory_skuid & 0x3; + return memory_skuid; +} diff --git a/src/mainboard/up/squared/romstage.h b/src/mainboard/up/squared/romstage.h new file mode 100644 index 0000000..5c0f4ba --- /dev/null +++ b/src/mainboard/up/squared/romstage.h @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +uint8_t get_memory_skuid(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/34838 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic121652213d5b1f65cff2f3096e919a3cf88db72 Gerrit-Change-Number: 34838 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

5 26

Change in ...coreboot[master]: src/mainboard: Remove unused include <device/pci_ops.h>
by HAOUAS Elyes (Code Review) 16 Sep '19

16 Sep '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33528 Change subject: src/mainboard: Remove unused include <device/pci_ops.h> ...................................................................... src/mainboard: Remove unused include <device/pci_ops.h> Change-Id: Icdbccb3af294dd97ba1835f034669198094a3661 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/advansus/a785e-i/romstage.c M src/mainboard/amd/bimini_fam10/romstage.c M src/mainboard/apple/macbook21/mainboard.c M src/mainboard/asus/kcma-d8/bootblock.c M src/mainboard/asus/kgpe-d16/bootblock.c M src/mainboard/asus/m5a88-v/romstage.c M src/mainboard/avalue/eax-785e/romstage.c M src/mainboard/google/beltino/mainboard.c M src/mainboard/google/butterfly/chromeos.c M src/mainboard/google/parrot/mainboard.c M src/mainboard/google/rambi/mainboard.c M src/mainboard/google/slippy/mainboard.c M src/mainboard/hp/dl165_g6_fam10/romstage.c M src/mainboard/intel/baskingridge/chromeos.c M src/mainboard/intel/baskingridge/mainboard.c M src/mainboard/intel/bayleybay_fsp/mainboard.c M src/mainboard/intel/camelbackmountain_fsp/mainboard.c M src/mainboard/intel/d510mo/mainboard.c M src/mainboard/intel/emeraldlake2/chromeos.c M src/mainboard/intel/emeraldlake2/mainboard.c M src/mainboard/intel/wtm2/mainboard.c M src/mainboard/kontron/ktqm77/mainboard.c M src/mainboard/samsung/lumpy/mainboard.c M src/mainboard/siemens/mc_tcu3/mainboard.c M src/mainboard/via/epia-m850/mainboard.c 25 files changed, 0 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/33528/1 diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index 4a817cf..82bc71c 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -17,7 +17,6 @@ #include <stdint.h> #include <device/pci_def.h> -#include <device/pci_ops.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <timestamp.h> diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index 7b2f051..7f3fb0c 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -18,7 +18,6 @@ #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> -#include <device/pci_ops.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> diff --git a/src/mainboard/apple/macbook21/mainboard.c b/src/mainboard/apple/macbook21/mainboard.c index 798fc12..b2aafe3 100644 --- a/src/mainboard/apple/macbook21/mainboard.c +++ b/src/mainboard/apple/macbook21/mainboard.c @@ -17,7 +17,6 @@ #include <device/device.h> #include <device/pci_def.h> -#include <device/pci_ops.h> #include <arch/interrupt.h> #include <northbridge/intel/i945/i945.h> #include <arch/acpigen.h> diff --git a/src/mainboard/asus/kcma-d8/bootblock.c b/src/mainboard/asus/kcma-d8/bootblock.c index 543ffed..b370ae0 100644 --- a/src/mainboard/asus/kcma-d8/bootblock.c +++ b/src/mainboard/asus/kcma-d8/bootblock.c @@ -15,7 +15,6 @@ * GNU General Public License for more details. */ -#include <device/pci_ops.h> #include <pc80/mc146818rtc.h> void bootblock_mainboard_init(void) diff --git a/src/mainboard/asus/kgpe-d16/bootblock.c b/src/mainboard/asus/kgpe-d16/bootblock.c index 543ffed..b370ae0 100644 --- a/src/mainboard/asus/kgpe-d16/bootblock.c +++ b/src/mainboard/asus/kgpe-d16/bootblock.c @@ -15,7 +15,6 @@ * GNU General Public License for more details. */ -#include <device/pci_ops.h> #include <pc80/mc146818rtc.h> void bootblock_mainboard_init(void) diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index 9216ecb..492c978 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -19,7 +19,6 @@ #include <stdint.h> #include <device/pci_def.h> -#include <device/pci_ops.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index 9347919..33e4388 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -17,7 +17,6 @@ #include <stdint.h> #include <device/pci_def.h> -#include <device/pci_ops.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> diff --git a/src/mainboard/google/beltino/mainboard.c b/src/mainboard/google/beltino/mainboard.c index 7bda2f6..347017d 100644 --- a/src/mainboard/google/beltino/mainboard.c +++ b/src/mainboard/google/beltino/mainboard.c @@ -21,7 +21,6 @@ #include <boot/coreboot_tables.h> #include <device/device.h> #include <device/pci_def.h> -#include <device/pci_ops.h> #include <southbridge/intel/lynxpoint/pch.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index 7f72ad2..dacf0cf 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -16,7 +16,6 @@ #include <console/console.h> #include <string.h> #include <bootmode.h> -#include <device/pci_ops.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/mainboard/google/parrot/mainboard.c b/src/mainboard/google/parrot/mainboard.c index 8c3ad63..d37ff23 100644 --- a/src/mainboard/google/parrot/mainboard.c +++ b/src/mainboard/google/parrot/mainboard.c @@ -17,7 +17,6 @@ #include <types.h> #include <device/device.h> #include <device/pci_def.h> -#include <device/pci_ops.h> #include <drivers/intel/gma/int15.h> #include <arch/acpi.h> #include <arch/io.h> diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index d3f6164..30be5f7 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -17,7 +17,6 @@ #include <types.h> #include <device/device.h> #include <device/pci_def.h> -#include <device/pci_ops.h> #include <console/console.h> #if CONFIG(VGA_ROM_RUN) #include <x86emu/x86emu.h> diff --git a/src/mainboard/google/slippy/mainboard.c b/src/mainboard/google/slippy/mainboard.c index b98fc8a..58e708b 100644 --- a/src/mainboard/google/slippy/mainboard.c +++ b/src/mainboard/google/slippy/mainboard.c @@ -18,7 +18,6 @@ #include <smbios.h> #include <device/device.h> #include <device/pci_def.h> -#include <device/pci_ops.h> #include <drivers/intel/gma/int15.h> #include <arch/acpi.h> #include <arch/io.h> diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index c02b0e6..5291247 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -24,7 +24,6 @@ #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> -#include <device/pci_ops.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include "option_table.h" diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index 6561927..2668af1 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -15,7 +15,6 @@ #include <string.h> #include <bootmode.h> -#include <device/pci_ops.h> #include <device/device.h> #include <device/pci.h> #include <southbridge/intel/lynxpoint/pch.h> diff --git a/src/mainboard/intel/baskingridge/mainboard.c b/src/mainboard/intel/baskingridge/mainboard.c index 49e66bf..96b0aee 100644 --- a/src/mainboard/intel/baskingridge/mainboard.c +++ b/src/mainboard/intel/baskingridge/mainboard.c @@ -17,7 +17,6 @@ #include <types.h> #include <device/device.h> #include <device/pci_def.h> -#include <device/pci_ops.h> #include <drivers/intel/gma/int15.h> #include <arch/acpi.h> #include <arch/io.h> diff --git a/src/mainboard/intel/bayleybay_fsp/mainboard.c b/src/mainboard/intel/bayleybay_fsp/mainboard.c index 16c1844..590cc46 100644 --- a/src/mainboard/intel/bayleybay_fsp/mainboard.c +++ b/src/mainboard/intel/bayleybay_fsp/mainboard.c @@ -17,7 +17,6 @@ #include <types.h> #include <device/device.h> #include <device/pci_def.h> -#include <device/pci_ops.h> #if CONFIG(VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif diff --git a/src/mainboard/intel/camelbackmountain_fsp/mainboard.c b/src/mainboard/intel/camelbackmountain_fsp/mainboard.c index ee9f36e..494d9fa 100644 --- a/src/mainboard/intel/camelbackmountain_fsp/mainboard.c +++ b/src/mainboard/intel/camelbackmountain_fsp/mainboard.c @@ -17,7 +17,6 @@ #include <types.h> #include <device/device.h> #include <device/pci_def.h> -#include <device/pci_ops.h> #if CONFIG(VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif diff --git a/src/mainboard/intel/d510mo/mainboard.c b/src/mainboard/intel/d510mo/mainboard.c index d2751bc..cac5064 100644 --- a/src/mainboard/intel/d510mo/mainboard.c +++ b/src/mainboard/intel/d510mo/mainboard.c @@ -15,7 +15,6 @@ #include <device/device.h> #include <device/pci_def.h> -#include <device/pci_ops.h> #include <device/pci.h> #include <drivers/intel/gma/int15.h> diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c index 699141f..226411e 100644 --- a/src/mainboard/intel/emeraldlake2/chromeos.c +++ b/src/mainboard/intel/emeraldlake2/chromeos.c @@ -15,7 +15,6 @@ #include <string.h> #include <bootmode.h> -#include <device/pci_ops.h> #include <device/device.h> #include <device/pci.h> #include <southbridge/intel/bd82x6x/pch.h> diff --git a/src/mainboard/intel/emeraldlake2/mainboard.c b/src/mainboard/intel/emeraldlake2/mainboard.c index d07da83..3032ff4 100644 --- a/src/mainboard/intel/emeraldlake2/mainboard.c +++ b/src/mainboard/intel/emeraldlake2/mainboard.c @@ -17,7 +17,6 @@ #include <types.h> #include <device/device.h> #include <device/pci_def.h> -#include <device/pci_ops.h> #include <drivers/intel/gma/int15.h> #include <arch/acpi.h> #include <arch/interrupt.h> diff --git a/src/mainboard/intel/wtm2/mainboard.c b/src/mainboard/intel/wtm2/mainboard.c index 4bfd039..ba17b1d 100644 --- a/src/mainboard/intel/wtm2/mainboard.c +++ b/src/mainboard/intel/wtm2/mainboard.c @@ -17,7 +17,6 @@ #include <types.h> #include <device/device.h> #include <device/pci_def.h> -#include <device/pci_ops.h> #include <drivers/intel/gma/int15.h> #include <arch/acpi.h> #include <arch/io.h> diff --git a/src/mainboard/kontron/ktqm77/mainboard.c b/src/mainboard/kontron/ktqm77/mainboard.c index afedbfc..675cb05 100644 --- a/src/mainboard/kontron/ktqm77/mainboard.c +++ b/src/mainboard/kontron/ktqm77/mainboard.c @@ -18,7 +18,6 @@ #include <types.h> #include <device/device.h> #include <device/pci_def.h> -#include <device/pci_ops.h> #include <console/console.h> #if CONFIG(VGA_ROM_RUN) #include <x86emu/x86emu.h> diff --git a/src/mainboard/samsung/lumpy/mainboard.c b/src/mainboard/samsung/lumpy/mainboard.c index 8664217..7aad98c 100644 --- a/src/mainboard/samsung/lumpy/mainboard.c +++ b/src/mainboard/samsung/lumpy/mainboard.c @@ -18,7 +18,6 @@ #include <string.h> #include <device/device.h> #include <device/pci_def.h> -#include <device/pci_ops.h> #include <drivers/intel/gma/int15.h> #include <arch/acpi.h> #include <arch/interrupt.h> diff --git a/src/mainboard/siemens/mc_tcu3/mainboard.c b/src/mainboard/siemens/mc_tcu3/mainboard.c index 169b04d..dd0f2ed 100644 --- a/src/mainboard/siemens/mc_tcu3/mainboard.c +++ b/src/mainboard/siemens/mc_tcu3/mainboard.c @@ -18,7 +18,6 @@ #include <string.h> #include <device/device.h> #include <device/pci_def.h> -#include <device/pci_ops.h> #if CONFIG(VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif diff --git a/src/mainboard/via/epia-m850/mainboard.c b/src/mainboard/via/epia-m850/mainboard.c index e7d65a0..03699db 100644 --- a/src/mainboard/via/epia-m850/mainboard.c +++ b/src/mainboard/via/epia-m850/mainboard.c @@ -16,7 +16,6 @@ #include <device/device.h> #include <device/pci_def.h> -#include <device/pci_ops.h> #include <console/console.h> #if CONFIG(VGA_ROM_RUN) -- To view, visit https://review.coreboot.org/c/coreboot/+/33528 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icdbccb3af294dd97ba1835f034669198094a3661 Gerrit-Change-Number: 33528 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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