coreboot-gerrit August 2019

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Change in ...coreboot[master]: mb/google/glados: Fix false coverity alarms
by Nico Huber (Code Review) 19 Sep '19

19 Sep '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32741 Change subject: mb/google/glados: Fix false coverity alarms ...................................................................... mb/google/glados: Fix false coverity alarms Coverity doesn't like the filling of adjacent arrays with a single memcpy(). The structure of the FSP headers doesn't allow us to loop over them either. As simply replicating the memcpy() calls doesn't make the code any more readable, use the new memcpy_elen() and memcpy_dlen() macros. CID=1401338..1401340, 1401342..1401343 Change-Id: Ie1419381f812b0ba0563163139a8cf0d0599e492 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/google/glados/variants/asuka/variant.c M src/mainboard/google/glados/variants/caroline/variant.c M src/mainboard/google/glados/variants/cave/variant.c M src/mainboard/google/glados/variants/chell/variant.c M src/mainboard/google/glados/variants/glados/variant.c M src/mainboard/google/glados/variants/lars/variant.c M src/mainboard/google/glados/variants/sentry/variant.c 7 files changed, 50 insertions(+), 64 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/32741/1 diff --git a/src/mainboard/google/glados/variants/asuka/variant.c b/src/mainboard/google/glados/variants/asuka/variant.c index 4c77897..1800470a 100644 --- a/src/mainboard/google/glados/variants/asuka/variant.c +++ b/src/mainboard/google/glados/variants/asuka/variant.c @@ -15,9 +15,9 @@ */ #include <stdint.h> -#include <string.h> #include <baseboard/variant.h> #include <fsp/soc_binding.h> +#include <lib.h> void variant_memory_init_params( MEMORY_INIT_UPD *const memory_params, const int spd_index) @@ -39,14 +39,12 @@ /* Rcomp target */ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; - memcpy(memory_params->DqByteMapCh0, dq_map, - sizeof(memory_params->DqByteMapCh0) * 2); - memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, - sizeof(memory_params->DqsMapCpu2DramCh0) * 2); - memcpy(memory_params->RcompResistor, RcompResistor, - sizeof(memory_params->RcompResistor)); - memcpy(memory_params->RcompTarget, RcompTarget, - sizeof(memory_params->RcompTarget)); + memcpy_elen(memory_params->DqByteMapCh0, dq_map[0]); + memcpy_elen(memory_params->DqByteMapCh1, dq_map[1]); + memcpy_elen(memory_params->DqsMapCpu2DramCh0, dqs_map[0]); + memcpy_elen(memory_params->DqsMapCpu2DramCh1, dqs_map[1]); + memcpy_elen(memory_params->RcompResistor, RcompResistor); + memcpy_elen(memory_params->RcompTarget, RcompTarget); } int is_dual_channel(const int spd_index) diff --git a/src/mainboard/google/glados/variants/caroline/variant.c b/src/mainboard/google/glados/variants/caroline/variant.c index d61a538..0fa7ee4 100644 --- a/src/mainboard/google/glados/variants/caroline/variant.c +++ b/src/mainboard/google/glados/variants/caroline/variant.c @@ -17,8 +17,8 @@ #include <baseboard/variant.h> #include <fsp/soc_binding.h> #include <gpio.h> +#include <lib.h> #include <stdint.h> -#include <string.h> #include <variant/gpio.h> void variant_memory_init_params( @@ -41,14 +41,12 @@ /* Rcomp target */ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; - memcpy(memory_params->DqByteMapCh0, dq_map, - sizeof(memory_params->DqByteMapCh0) * 2); - memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, - sizeof(memory_params->DqsMapCpu2DramCh0) * 2); - memcpy(memory_params->RcompResistor, RcompResistor, - sizeof(memory_params->RcompResistor)); - memcpy(memory_params->RcompTarget, RcompTarget, - sizeof(memory_params->RcompTarget)); + memcpy_elen(memory_params->DqByteMapCh0, dq_map[0]); + memcpy_elen(memory_params->DqByteMapCh1, dq_map[1]); + memcpy_elen(memory_params->DqsMapCpu2DramCh0, dqs_map[0]); + memcpy_elen(memory_params->DqsMapCpu2DramCh1, dqs_map[1]); + memcpy_elen(memory_params->RcompResistor, RcompResistor); + memcpy_elen(memory_params->RcompTarget, RcompTarget); memory_params->DdrFreqLimit = 1600; } diff --git a/src/mainboard/google/glados/variants/cave/variant.c b/src/mainboard/google/glados/variants/cave/variant.c index fc27fb4..4c0f8fa 100644 --- a/src/mainboard/google/glados/variants/cave/variant.c +++ b/src/mainboard/google/glados/variants/cave/variant.c @@ -17,8 +17,8 @@ #include <baseboard/variant.h> #include <fsp/soc_binding.h> #include <gpio.h> +#include <lib.h> #include <stdint.h> -#include <string.h> #include <variant/gpio.h> void variant_memory_init_params( @@ -41,14 +41,12 @@ /* Rcomp target */ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; - memcpy(memory_params->DqByteMapCh0, dq_map, - sizeof(memory_params->DqByteMapCh0) * 2); - memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, - sizeof(memory_params->DqsMapCpu2DramCh0) * 2); - memcpy(memory_params->RcompResistor, RcompResistor, - sizeof(memory_params->RcompResistor)); - memcpy(memory_params->RcompTarget, RcompTarget, - sizeof(memory_params->RcompTarget)); + memcpy_elen(memory_params->DqByteMapCh0, dq_map[0]); + memcpy_elen(memory_params->DqByteMapCh1, dq_map[1]); + memcpy_elen(memory_params->DqsMapCpu2DramCh0, dqs_map[0]); + memcpy_elen(memory_params->DqsMapCpu2DramCh1, dqs_map[1]); + memcpy_elen(memory_params->RcompResistor, RcompResistor); + memcpy_elen(memory_params->RcompTarget, RcompTarget); } void mainboard_gpio_smi_sleep(void) diff --git a/src/mainboard/google/glados/variants/chell/variant.c b/src/mainboard/google/glados/variants/chell/variant.c index 2d1b363..7b29137 100644 --- a/src/mainboard/google/glados/variants/chell/variant.c +++ b/src/mainboard/google/glados/variants/chell/variant.c @@ -17,8 +17,8 @@ #include <baseboard/variant.h> #include <fsp/soc_binding.h> #include <gpio.h> +#include <lib.h> #include <stdint.h> -#include <string.h> #include <variant/gpio.h> void variant_memory_init_params( @@ -41,14 +41,12 @@ /* Rcomp target */ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; - memcpy(memory_params->DqByteMapCh0, dq_map, - sizeof(memory_params->DqByteMapCh0) * 2); - memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, - sizeof(memory_params->DqsMapCpu2DramCh0) * 2); - memcpy(memory_params->RcompResistor, RcompResistor, - sizeof(memory_params->RcompResistor)); - memcpy(memory_params->RcompTarget, RcompTarget, - sizeof(memory_params->RcompTarget)); + memcpy_elen(memory_params->DqByteMapCh0, dq_map[0]); + memcpy_elen(memory_params->DqByteMapCh1, dq_map[1]); + memcpy_elen(memory_params->DqsMapCpu2DramCh0, dqs_map[0]); + memcpy_elen(memory_params->DqsMapCpu2DramCh1, dqs_map[1]); + memcpy_elen(memory_params->RcompResistor, RcompResistor); + memcpy_elen(memory_params->RcompTarget, RcompTarget); } void mainboard_gpio_smi_sleep(void) diff --git a/src/mainboard/google/glados/variants/glados/variant.c b/src/mainboard/google/glados/variants/glados/variant.c index fc27fb4..4c0f8fa 100644 --- a/src/mainboard/google/glados/variants/glados/variant.c +++ b/src/mainboard/google/glados/variants/glados/variant.c @@ -17,8 +17,8 @@ #include <baseboard/variant.h> #include <fsp/soc_binding.h> #include <gpio.h> +#include <lib.h> #include <stdint.h> -#include <string.h> #include <variant/gpio.h> void variant_memory_init_params( @@ -41,14 +41,12 @@ /* Rcomp target */ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; - memcpy(memory_params->DqByteMapCh0, dq_map, - sizeof(memory_params->DqByteMapCh0) * 2); - memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, - sizeof(memory_params->DqsMapCpu2DramCh0) * 2); - memcpy(memory_params->RcompResistor, RcompResistor, - sizeof(memory_params->RcompResistor)); - memcpy(memory_params->RcompTarget, RcompTarget, - sizeof(memory_params->RcompTarget)); + memcpy_elen(memory_params->DqByteMapCh0, dq_map[0]); + memcpy_elen(memory_params->DqByteMapCh1, dq_map[1]); + memcpy_elen(memory_params->DqsMapCpu2DramCh0, dqs_map[0]); + memcpy_elen(memory_params->DqsMapCpu2DramCh1, dqs_map[1]); + memcpy_elen(memory_params->RcompResistor, RcompResistor); + memcpy_elen(memory_params->RcompTarget, RcompTarget); } void mainboard_gpio_smi_sleep(void) diff --git a/src/mainboard/google/glados/variants/lars/variant.c b/src/mainboard/google/glados/variants/lars/variant.c index cff0096..e3edd29 100644 --- a/src/mainboard/google/glados/variants/lars/variant.c +++ b/src/mainboard/google/glados/variants/lars/variant.c @@ -15,9 +15,9 @@ */ #include <stdint.h> -#include <string.h> #include <baseboard/variant.h> #include <fsp/soc_binding.h> +#include <lib.h> #define K4E6E304EB_MEM_ID 0x5 @@ -29,7 +29,7 @@ #define MEM_SINGLE_CHANC 0xc void variant_memory_init_params( - MEMORY_INIT_UPD *const params, const int spd_index) + MEMORY_INIT_UPD *const memory_params, const int spd_index) { /* DQ byte map */ const u8 dq_map[2][12] = { @@ -58,14 +58,12 @@ if (spd_index == K4E6E304EB_MEM_ID) targeted_rcomp = StrengthendRcompTarget; - memcpy(params->DqByteMapCh0, dq_map, - sizeof(params->DqByteMapCh0) * 2); - memcpy(params->DqsMapCpu2DramCh0, dqs_map, - sizeof(params->DqsMapCpu2DramCh0) * 2); - memcpy(params->RcompResistor, RcompResistor, - sizeof(params->RcompResistor)); - memcpy(params->RcompTarget, targeted_rcomp, - sizeof(params->RcompTarget)); + memcpy_elen(memory_params->DqByteMapCh0, dq_map[0]); + memcpy_elen(memory_params->DqByteMapCh1, dq_map[1]); + memcpy_elen(memory_params->DqsMapCpu2DramCh0, dqs_map[0]); + memcpy_elen(memory_params->DqsMapCpu2DramCh1, dqs_map[1]); + memcpy_elen(memory_params->RcompResistor, RcompResistor); + memcpy_dlen(memory_params->RcompTarget, targeted_rcomp); } int is_dual_channel(const int spd_index) diff --git a/src/mainboard/google/glados/variants/sentry/variant.c b/src/mainboard/google/glados/variants/sentry/variant.c index 4c7fa23..e73aa3c 100644 --- a/src/mainboard/google/glados/variants/sentry/variant.c +++ b/src/mainboard/google/glados/variants/sentry/variant.c @@ -15,9 +15,9 @@ */ #include <stdint.h> -#include <string.h> #include <baseboard/variant.h> #include <fsp/soc_binding.h> +#include <lib.h> #define K4E6E304EE_MEM_ID 0x3 @@ -51,12 +51,10 @@ if (spd_index == K4E6E304EE_MEM_ID) targeted_rcomp = StrengthendRcompTarget; - memcpy(memory_params->DqByteMapCh0, dq_map, - sizeof(memory_params->DqByteMapCh0) * 2); - memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, - sizeof(memory_params->DqsMapCpu2DramCh0) * 2); - memcpy(memory_params->RcompResistor, RcompResistor, - sizeof(memory_params->RcompResistor)); - memcpy(memory_params->RcompTarget, targeted_rcomp, - sizeof(memory_params->RcompTarget)); + memcpy_elen(memory_params->DqByteMapCh0, dq_map[0]); + memcpy_elen(memory_params->DqByteMapCh1, dq_map[1]); + memcpy_elen(memory_params->DqsMapCpu2DramCh0, dqs_map[0]); + memcpy_elen(memory_params->DqsMapCpu2DramCh1, dqs_map[1]); + memcpy_elen(memory_params->RcompResistor, RcompResistor); + memcpy_dlen(memory_params->RcompTarget, targeted_rcomp); } -- To view, visit https://review.coreboot.org/c/coreboot/+/32741 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie1419381f812b0ba0563163139a8cf0d0599e492 Gerrit-Change-Number: 32741 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/intel/{kunimitsu,saddlebrook}: Fix false coverity alarms
by Nico Huber (Code Review) 19 Sep '19

19 Sep '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32742 Change subject: mb/intel/{kunimitsu,saddlebrook}: Fix false coverity alarms ...................................................................... mb/intel/{kunimitsu,saddlebrook}: Fix false coverity alarms Coverity doesn't like the filling of adjacent arrays with a single memcpy(). The structure of the FSP headers doesn't allow us to loop over them either. In case of Kunimitsu we also can't have a better typed solution because of the FSP1.1/FSP2.0 dual port. Just replicating the functions per channel is probably the best we can do. CID=1401341, 1401344 Change-Id: I36a141bc00664ccd29d625ac88e76073086a5074 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/intel/kunimitsu/romstage.c M src/mainboard/intel/kunimitsu/romstage_fsp20.c M src/mainboard/intel/kunimitsu/spd/spd.h M src/mainboard/intel/kunimitsu/spd/spd_util.c M src/mainboard/intel/saddlebrook/romstage.c M src/mainboard/intel/saddlebrook/spd/spd.h M src/mainboard/intel/saddlebrook/spd/spd_util.c 7 files changed, 60 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/32742/1 diff --git a/src/mainboard/intel/kunimitsu/romstage.c b/src/mainboard/intel/kunimitsu/romstage.c index f25f88b..1a474da 100644 --- a/src/mainboard/intel/kunimitsu/romstage.c +++ b/src/mainboard/intel/kunimitsu/romstage.c @@ -30,8 +30,10 @@ MEMORY_INIT_UPD *memory_params) { spd_memory_init_params(memory_params); - mainboard_fill_dq_map_data(&memory_params->DqByteMapCh0); - mainboard_fill_dqs_map_data(&memory_params->DqsMapCpu2DramCh0); + mainboard_fill_dq_map_data0(&memory_params->DqByteMapCh0); + mainboard_fill_dq_map_data1(&memory_params->DqByteMapCh1); + mainboard_fill_dqs_map_data0(&memory_params->DqsMapCpu2DramCh0); + mainboard_fill_dqs_map_data1(&memory_params->DqsMapCpu2DramCh1); mainboard_fill_rcomp_res_data(&memory_params->RcompResistor); mainboard_fill_rcomp_strength_data(&memory_params->RcompTarget); memory_params->MemorySpdDataLen = SPD_LEN; diff --git a/src/mainboard/intel/kunimitsu/romstage_fsp20.c b/src/mainboard/intel/kunimitsu/romstage_fsp20.c index ee1ddd5..10992f0 100644 --- a/src/mainboard/intel/kunimitsu/romstage_fsp20.c +++ b/src/mainboard/intel/kunimitsu/romstage_fsp20.c @@ -26,8 +26,10 @@ FSP_M_CONFIG *mem_cfg; mem_cfg = &mupd->FspmConfig; - mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); - mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_dq_map_data0(&mem_cfg->DqByteMapCh0); + mainboard_fill_dq_map_data1(&mem_cfg->DqByteMapCh1); + mainboard_fill_dqs_map_data0(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_dqs_map_data1(&mem_cfg->DqsMapCpu2DramCh1); mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); diff --git a/src/mainboard/intel/kunimitsu/spd/spd.h b/src/mainboard/intel/kunimitsu/spd/spd.h index 22d371f..e8b42ee 100644 --- a/src/mainboard/intel/kunimitsu/spd/spd.h +++ b/src/mainboard/intel/kunimitsu/spd/spd.h @@ -55,8 +55,10 @@ return (gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios))); } void spd_memory_init_params(MEMORY_INIT_UPD *memory_params); -void mainboard_fill_dq_map_data(void *dq_map_ptr); -void mainboard_fill_dqs_map_data(void *dqs_map_ptr); +void mainboard_fill_dq_map_data0(void *dq_map_ptr); +void mainboard_fill_dq_map_data1(void *dq_map_ptr); +void mainboard_fill_dqs_map_data0(void *dqs_map_ptr); +void mainboard_fill_dqs_map_data1(void *dqs_map_ptr); void mainboard_fill_rcomp_res_data(void *rcomp_ptr); void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); uintptr_t mainboard_get_spd_data(void); diff --git a/src/mainboard/intel/kunimitsu/spd/spd_util.c b/src/mainboard/intel/kunimitsu/spd/spd_util.c index b173628..6dcc92d 100644 --- a/src/mainboard/intel/kunimitsu/spd/spd_util.c +++ b/src/mainboard/intel/kunimitsu/spd/spd_util.c @@ -20,23 +20,33 @@ #include "boardid.h" #include "spd.h" -void mainboard_fill_dq_map_data(void *dq_map_ptr) +void mainboard_fill_dq_map_data0(void *dq_map_ptr) { /* DQ byte map */ - const u8 dq_map[2][12] = { - { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, - 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, - { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, - 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + const u8 dq_map[12] = { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }; memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); } -void mainboard_fill_dqs_map_data(void *dqs_map_ptr) +void mainboard_fill_dq_map_data1(void *dq_map_ptr) +{ + /* DQ byte map */ + const u8 dq_map[12] = { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }; + memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); +} + +void mainboard_fill_dqs_map_data0(void *dqs_map_ptr) { /* DQS CPU<>DRAM map */ - const u8 dqs_map[2][8] = { - { 0, 1, 3, 2, 6, 5, 4, 7 }, - { 2, 3, 0, 1, 6, 7, 4, 5 } }; + const u8 dqs_map[8] = { 0, 1, 3, 2, 6, 5, 4, 7 }; + memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); +} + +void mainboard_fill_dqs_map_data1(void *dqs_map_ptr) +{ + /* DQS CPU<>DRAM map */ + const u8 dqs_map[8] = { 2, 3, 0, 1, 6, 7, 4, 5 }; memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); } diff --git a/src/mainboard/intel/saddlebrook/romstage.c b/src/mainboard/intel/saddlebrook/romstage.c index 48d39db..7b2687f 100644 --- a/src/mainboard/intel/saddlebrook/romstage.c +++ b/src/mainboard/intel/saddlebrook/romstage.c @@ -63,8 +63,10 @@ * should be set in the FSP flash image and should not need to be * changed. */ - mainboard_fill_dq_map_data(&memory_params->DqByteMapCh0); - mainboard_fill_dqs_map_data(&memory_params->DqsMapCpu2DramCh0); + mainboard_fill_dq_map_data0(&memory_params->DqByteMapCh0); + mainboard_fill_dq_map_data1(&memory_params->DqByteMapCh1); + mainboard_fill_dqs_map_data0(&memory_params->DqsMapCpu2DramCh0); + mainboard_fill_dqs_map_data1(&memory_params->DqsMapCpu2DramCh1); mainboard_fill_rcomp_res_data(&memory_params->RcompResistor); mainboard_fill_rcomp_strength_data(&memory_params->RcompTarget); diff --git a/src/mainboard/intel/saddlebrook/spd/spd.h b/src/mainboard/intel/saddlebrook/spd/spd.h index a5f1af3..47587ed 100644 --- a/src/mainboard/intel/saddlebrook/spd/spd.h +++ b/src/mainboard/intel/saddlebrook/spd/spd.h @@ -19,8 +19,10 @@ #define RCOMP_TARGET_PARAMS 0x5 -void mainboard_fill_dq_map_data(void *dq_map_ptr); -void mainboard_fill_dqs_map_data(void *dqs_map_ptr); +void mainboard_fill_dq_map_data0(void *dq_map_ptr); +void mainboard_fill_dq_map_data1(void *dq_map_ptr); +void mainboard_fill_dqs_map_data0(void *dqs_map_ptr); +void mainboard_fill_dqs_map_data1(void *dqs_map_ptr); void mainboard_fill_rcomp_res_data(void *rcomp_ptr); void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); diff --git a/src/mainboard/intel/saddlebrook/spd/spd_util.c b/src/mainboard/intel/saddlebrook/spd/spd_util.c index 5055d9a..7f27c31 100644 --- a/src/mainboard/intel/saddlebrook/spd/spd_util.c +++ b/src/mainboard/intel/saddlebrook/spd/spd_util.c @@ -17,23 +17,33 @@ #include <string.h> #include "spd.h" -void mainboard_fill_dq_map_data(void *dq_map_ptr) +void mainboard_fill_dq_map_data0(void *dq_map_ptr) { /* DQ byte map */ - const u8 dq_map[2][12] = { - { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, - 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, - { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, - 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + const u8 dq_map[12] = { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }; memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); } -void mainboard_fill_dqs_map_data(void *dqs_map_ptr) +void mainboard_fill_dq_map_data1(void *dq_map_ptr) +{ + /* DQ byte map */ + const u8 dq_map[12] = { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 }; + memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); +} + +void mainboard_fill_dqs_map_data0(void *dqs_map_ptr) { /* DQS CPU<>DRAM map */ - const u8 dqs_map[2][8] = { - { 0, 1, 3, 2, 4, 5, 6, 7 }, - { 1, 0, 4, 5, 2, 3, 6, 7 } }; + const u8 dqs_map[8] = { 0, 1, 3, 2, 4, 5, 6, 7 }; + memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); +} + +void mainboard_fill_dqs_map_data1(void *dqs_map_ptr) +{ + /* DQS CPU<>DRAM map */ + const u8 dqs_map[8] = { 1, 0, 4, 5, 2, 3, 6, 7 }; memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); } -- To view, visit https://review.coreboot.org/c/coreboot/+/32742 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36a141bc00664ccd29d625ac88e76073086a5074 Gerrit-Change-Number: 32742 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/lint: make clang-format non-fatal
by Angel Pons (Code Review) 19 Sep '19

19 Sep '19

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35176 ) Change subject: util/lint: make clang-format non-fatal ...................................................................... util/lint: make clang-format non-fatal The current clang-format configuration is completely broken. It forces one to change the code style of patches before pushing them, only to find out that checkpatch now complains about it. This means newcomers get scared away, and developers only get angered and frustrated about it, and end up working around clang-format's requirements anyway. For now, make clang-format's complaints non-fatal, reducing them to text noise. However, since clang-format is currently unusable, reverting it out would be preferred. Change-Id: Iffa8934efa1c27c04e10545f66d8f9976e74c367 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/skylake/chip_fsp20.c M util/lint/check-style M util/lint/lint-stable-022-clang-format 3 files changed, 3 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/35176/1 diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 064f71e..bfd9480 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -127,8 +127,7 @@ * Found the first enabled device in * a given dev number. */ - printk(BIOS_INFO, "PCI func %d was swapped" - " to func 0.\n", i); + printk(BIOS_INFO, "PCI func %d was swapped to func 0.\n", i); func0->path.pci.devfn = dev->path.pci.devfn; dev->path.pci.devfn = devfn0; break; diff --git a/util/lint/check-style b/util/lint/check-style index 2237ed6..a0679d8 100755 --- a/util/lint/check-style +++ b/util/lint/check-style @@ -140,4 +140,4 @@ printf "Aborting commit. Apply changes and commit again or skip checking with" printf " --no-verify (not recommended).\n" -exit 1 +exit 0 diff --git a/util/lint/lint-stable-022-clang-format b/util/lint/lint-stable-022-clang-format index bd662e4..48f51a8 100755 --- a/util/lint/lint-stable-022-clang-format +++ b/util/lint/lint-stable-022-clang-format @@ -33,6 +33,6 @@ if [ "$(git diff --no-prefix HEAD~..HEAD -- $files_to_check | clang-format-diff)" != "" ]; then echo "Coding style mismatch. The following patch fixes it:" git diff --no-prefix HEAD~..HEAD -- $files_to_check | clang-format-diff - exit 1 + exit 0 fi fi -- To view, visit https://review.coreboot.org/c/coreboot/+/35176 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iffa8934efa1c27c04e10545f66d8f9976e74c367 Gerrit-Change-Number: 35176 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 4

Change in ...coreboot[master]: cpu/intel/common: Build FSB detection unconditionally
by Kyösti Mälkki (Code Review) 19 Sep '19

19 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31341 Change subject: cpu/intel/common: Build FSB detection unconditionally ...................................................................... cpu/intel/common: Build FSB detection unconditionally Change-Id: I37a34651d9e7d823ad5689d30739294358a97e31 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/common/Makefile.inc 1 file changed, 7 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/31341/1 diff --git a/src/cpu/intel/common/Makefile.inc b/src/cpu/intel/common/Makefile.inc index b67ca85..ef6c0a4 100644 --- a/src/cpu/intel/common/Makefile.inc +++ b/src/cpu/intel/common/Makefile.inc @@ -1,5 +1,8 @@ ramstage-y += common_init.c -romstage-$(CONFIG_UDELAY_LAPIC) += fsb.c -ramstage-$(CONFIG_UDELAY_LAPIC) += fsb.c -postcar-$(CONFIG_UDELAY_LAPIC) += fsb.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += fsb.c + +bootblock-y += fsb.c +verstage-y += fsb.c +romstage-y += fsb.c +postcar-y += fsb.c +ramstage-y += fsb.c +smm-y += fsb.c -- To view, visit https://review.coreboot.org/c/coreboot/+/31341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37a34651d9e7d823ad5689d30739294358a97e31 Gerrit-Change-Number: 31341 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

5 5

Change in coreboot[master]: cpu,mb,soc: Init missing lb_serial struct fields
by Jacob Garber (Code Review) 19 Sep '19

19 Sep '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34548 ) Change subject: cpu,mb,soc: Init missing lb_serial struct fields ...................................................................... cpu,mb,soc: Init missing lb_serial struct fields Initialize the input_hertz and uart_pci_addr fields of the lb_serial struct to prevent later undefined reads in lb_add_serial(). This was done for exynos5420 in commit ff94e00362 (soc/samsung/exynos5420/uart.c: Init new serial struct variables), and this patch finishes the rest. Change-Id: I733bc8185e2f2d28a9823495b53d6b09dce4deb1 Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Found-by: Coverity CID 1354778 --- M src/cpu/ti/am335x/uart.c M src/mainboard/emulation/qemu-power8/uart.c M src/soc/imgtec/pistachio/uart.c M src/soc/mediatek/common/uart.c M src/soc/nvidia/tegra124/uart.c M src/soc/nvidia/tegra210/uart.c M src/soc/qualcomm/ipq40xx/uart.c M src/soc/qualcomm/qcs405/uart.c M src/soc/samsung/exynos5250/uart.c 9 files changed, 25 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/34548/1 diff --git a/src/cpu/ti/am335x/uart.c b/src/cpu/ti/am335x/uart.c index 4e9d012..657404c 100644 --- a/src/cpu/ti/am335x/uart.c +++ b/src/cpu/ti/am335x/uart.c @@ -190,8 +190,10 @@ serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = get_uart_baudrate(); serial.regwidth = 2; - lb_add_serial(&serial, data); + serial.input_hertz = uart_platform_refclk(); + serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; + lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); } #endif diff --git a/src/mainboard/emulation/qemu-power8/uart.c b/src/mainboard/emulation/qemu-power8/uart.c index 9548b7c..a917421 100644 --- a/src/mainboard/emulation/qemu-power8/uart.c +++ b/src/mainboard/emulation/qemu-power8/uart.c @@ -50,6 +50,9 @@ serial.baseaddr = 0; serial.baud = 115200; serial.regwidth = 1; + serial.input_hertz = uart_platform_refclk(); + serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; + lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); } diff --git a/src/soc/imgtec/pistachio/uart.c b/src/soc/imgtec/pistachio/uart.c index a39f2ec..380292f 100644 --- a/src/soc/imgtec/pistachio/uart.c +++ b/src/soc/imgtec/pistachio/uart.c @@ -151,8 +151,10 @@ serial.baseaddr = CONFIG_CONSOLE_SERIAL_UART_ADDRESS; serial.baud = get_uart_baudrate(); serial.regwidth = 1 << UART_SHIFT; - lb_add_serial(&serial, data); + serial.input_hertz = uart_platform_refclk(); + serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; + lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); } #endif diff --git a/src/soc/mediatek/common/uart.c b/src/soc/mediatek/common/uart.c index 8905c55..c53909d 100644 --- a/src/soc/mediatek/common/uart.c +++ b/src/soc/mediatek/common/uart.c @@ -181,8 +181,10 @@ serial.input_hertz = UART_HZ; serial.baud = get_uart_baudrate(); serial.regwidth = 4; - lb_add_serial(&serial, data); + serial.input_hertz = uart_platform_refclk(); + serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; + lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); } #endif diff --git a/src/soc/nvidia/tegra124/uart.c b/src/soc/nvidia/tegra124/uart.c index c9514ac..697c90d 100644 --- a/src/soc/nvidia/tegra124/uart.c +++ b/src/soc/nvidia/tegra124/uart.c @@ -136,8 +136,10 @@ serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = get_uart_baudrate(); serial.regwidth = 4; - lb_add_serial(&serial, data); + serial.input_hertz = uart_platform_refclk(); + serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; + lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); } #endif diff --git a/src/soc/nvidia/tegra210/uart.c b/src/soc/nvidia/tegra210/uart.c index a91818c..0de85cb 100644 --- a/src/soc/nvidia/tegra210/uart.c +++ b/src/soc/nvidia/tegra210/uart.c @@ -123,8 +123,10 @@ serial.baseaddr = CONFIG_CONSOLE_SERIAL_TEGRA210_UART_ADDRESS; serial.baud = get_uart_baudrate(); serial.regwidth = 4; - lb_add_serial(&serial, data); + serial.input_hertz = uart_platform_refclk(); + serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; + lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); } #endif diff --git a/src/soc/qualcomm/ipq40xx/uart.c b/src/soc/qualcomm/ipq40xx/uart.c index eb3731b..77e0480 100644 --- a/src/soc/qualcomm/ipq40xx/uart.c +++ b/src/soc/qualcomm/ipq40xx/uart.c @@ -293,6 +293,8 @@ serial.baseaddr = (uint32_t)UART1_DM_BASE; serial.baud = get_uart_baudrate(); serial.regwidth = 1; + serial.input_hertz = uart_platform_refclk(); + serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); diff --git a/src/soc/qualcomm/qcs405/uart.c b/src/soc/qualcomm/qcs405/uart.c index 4a43312..8278db2 100644 --- a/src/soc/qualcomm/qcs405/uart.c +++ b/src/soc/qualcomm/qcs405/uart.c @@ -296,6 +296,8 @@ serial.baseaddr = (uint64_t)UART2_DM_BASE; serial.baud = get_uart_baudrate(); serial.regwidth = 1; + serial.input_hertz = uart_platform_refclk(); + serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); diff --git a/src/soc/samsung/exynos5250/uart.c b/src/soc/samsung/exynos5250/uart.c index 1b8e785..9654033 100644 --- a/src/soc/samsung/exynos5250/uart.c +++ b/src/soc/samsung/exynos5250/uart.c @@ -193,8 +193,10 @@ serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = get_uart_baudrate(); serial.regwidth = 4; - lb_add_serial(&serial, data); + serial.input_hertz = uart_platform_refclk(); + serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; + lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); } #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/34548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I733bc8185e2f2d28a9823495b53d6b09dce4deb1 Gerrit-Change-Number: 34548 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

4 14

Change in ...coreboot[master]: security/tpm/tss/tcg-2.0: Add multi digits support to tlcl_extend()
by Frans Hendriks (Code Review) 19 Sep '19

19 Sep '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33252 Change subject: security/tpm/tss/tcg-2.0: Add multi digits support to tlcl_extend() ...................................................................... security/tpm/tss/tcg-2.0: Add multi digits support to tlcl_extend() To support multi digists the tlcl_extend() for TPM2 expects TPML_DIGEST_VALUE pointer as input argument. BUG=N/A TEST=Build binary and verified logging on Facebook FBG-1701 Change-Id: I8d86c41c23e4e93a84e0527d7cddcfd30d5d8394 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/security/tpm/tspi/tspi.c M src/security/tpm/tss/tcg-2.0/tss.c M src/security/tpm/tss/tcg-2.0/tss_structures.h 3 files changed, 65 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/33252/1 diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c index 4698a4d..df1ca3b 100644 --- a/src/security/tpm/tspi/tspi.c +++ b/src/security/tpm/tspi/tspi.c @@ -4,6 +4,7 @@ * Copyright (c) 2013 The Chromium OS Authors. All rights reserved. * Copyright 2017 Facebook Inc. * Copyright 2018 Siemens AG + * Copyright 2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -209,7 +210,28 @@ if (!digest) return TPM_E_IOERROR; - result = tlcl_extend(pcr, digest, NULL); + if (CONFIG(TPM2)) { + TPML_DIGEST_VALUES tpml_digests; + + tpml_digests.count = 1; + switch (digest_algo) { + case VB2_HASH_SHA1: + tpml_digests.digests[0].hashAlg = TPM_ALG_SHA1; + memcpy(tpml_digests.digests[0].digest.sha1, digest, + sizeof(TPMU_HA)); + break; + case VB2_HASH_SHA256: + tpml_digests.digests[0].hashAlg = TPM_ALG_SHA256; + memcpy(tpml_digests.digests[0].digest.sha256, digest, + sizeof(TPMU_HA)); + break; + default: + return TPM_E_IOERROR; + } + result = tlcl_extend(pcr, (uint8_t *)&tpml_digests, NULL); + } else { + result = tlcl_extend(pcr, digest, NULL); + } if (result != TPM_SUCCESS) return result; diff --git a/src/security/tpm/tss/tcg-2.0/tss.c b/src/security/tpm/tss/tcg-2.0/tss.c index e579bff..4574b4f 100644 --- a/src/security/tpm/tss/tcg-2.0/tss.c +++ b/src/security/tpm/tss/tcg-2.0/tss.c @@ -126,24 +126,53 @@ } /* - * The caller will provide the digest in a 32 byte buffer, let's consider it a - * sha256 digest. + * The caller will provide the digest in a 32 byte buffer */ uint32_t tlcl_extend(int pcr_num, const uint8_t *in_digest, uint8_t *out_digest) { struct tpm2_pcr_extend_cmd pcr_ext_cmd; struct tpm2_response *response; + int i; + TPML_DIGEST_VALUES *tpml_digests; pcr_ext_cmd.pcrHandle = HR_PCR + pcr_num; - pcr_ext_cmd.digests.count = 1; - pcr_ext_cmd.digests.digests[0].hashAlg = TPM_ALG_SHA256; - memcpy(pcr_ext_cmd.digests.digests[0].digest.sha256, in_digest, - sizeof(pcr_ext_cmd.digests.digests[0].digest.sha256)); + tpml_digests = (TPML_DIGEST_VALUES *)in_digest; + pcr_ext_cmd.digests.count = tpml_digests->count; + + for (i = 0; i < tpml_digests->count ; i++) { + pcr_ext_cmd.digests.digests[i].hashAlg = + tpml_digests->digests[i].hashAlg; + switch (tpml_digests->digests[i].hashAlg) { + case TPM_ALG_SHA1: + memcpy(pcr_ext_cmd.digests.digests[i].digest.sha1, + tpml_digests->digests[i].digest.sha1, + sizeof(TPMU_HA)); + break; + case TPM_ALG_SHA256: + memcpy(pcr_ext_cmd.digests.digests[i].digest.sha256, + tpml_digests->digests[i].digest.sha256, + sizeof(TPMU_HA)); + } + } response = tpm_process_command(TPM2_PCR_Extend, &pcr_ext_cmd); - printk(BIOS_INFO, "%s: response is %x\n", + /* + * Check if we are invalidating the pcrs, ignore the error if this is + * the case + */ + if ((tpml_digests->count == 1) && + (tpml_digests->digests[0].hashAlg == TPM_ALG_ERROR) && + (tpml_digests->digests[0].digest.invalidate_pcrs == 1) && + response && (response->hdr.tpm_code & ~TPM_RC_N_MASK) == + (TPM_RC_P | TPM_RC_HASH)) { + printk(BIOS_SPEW, "%s: TPM_RC_HASH returned this is" + " expected\n", __func__); + return TPM_SUCCESS; + } + + printk(BIOS_INFO, "%s: response is 0x%x\n", __func__, response ? response->hdr.tpm_code : -1); if (!response || response->hdr.tpm_code) return TPM_E_IOERROR; diff --git a/src/security/tpm/tss/tcg-2.0/tss_structures.h b/src/security/tpm/tss/tcg-2.0/tss_structures.h index 991cbcf..b11a9f4 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_structures.h +++ b/src/security/tpm/tss/tcg-2.0/tss_structures.h @@ -79,6 +79,12 @@ space is defined by the lower 16 bits. */ #define TPM_CC_VENDOR_BIT_MASK 0x20000000 +/* Table 15 - TPM_RC Constants (Actions) */ +#define RC_FMT1 (TPM_RC)(0x080) +#define TPM_RC_HASH (TPM_RC)(RC_FMT1 + 0x003) +#define TPM_RC_P (TPM_RC)(0x040) +#define TPM_RC_N_MASK (TPM_RC)(0xF00) + /* Startup values. */ #define TPM_SU_CLEAR 0 #define TPM_SU_STATE 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/33252 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d86c41c23e4e93a84e0527d7cddcfd30d5d8394 Gerrit-Change-Number: 33252 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

6 23

Change in coreboot[master]: cpu/x86/lapic: Refactor timer_fsb()
by Kyösti Mälkki (Code Review) 19 Sep '19

19 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34091 ) Change subject: cpu/x86/lapic: Refactor timer_fsb() ...................................................................... cpu/x86/lapic: Refactor timer_fsb() Common apic_timer code in cpu/x86 should not depend on intel header files. Change-Id: Ib099921d4b8e561daea47219385762bb00fc4548 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/common/fsb.c M src/cpu/x86/lapic/apic_timer.c M src/include/delay.h 3 files changed, 40 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/34091/1 diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c index d66e87a..151ad9e 100644 --- a/src/cpu/intel/common/fsb.c +++ b/src/cpu/intel/common/fsb.c @@ -11,12 +11,14 @@ * GNU General Public License for more details. */ +#include <arch/early_variables.h> #include <cpu/cpu.h> #include <cpu/x86/msr.h> #include <cpu/intel/speedstep.h> #include <cpu/intel/fsb.h> #include <console/console.h> #include <commonlib/helpers.h> +#include <delay.h> static int get_fsb(void) { @@ -95,3 +97,23 @@ printk(BIOS_ERR, "FSB not supported or not found\n"); return -1; } + + + +static u32 g_timer_fsb CAR_GLOBAL; + +int set_timer_fsb(void) +{ + int ia32_fsb = get_ia32_fsb(); + + if (ia32_fsb > 0) { + car_set_var(g_timer_fsb, ia32_fsb); + return 0; + } + return -1; +} + +u32 get_timer_fsb(void) +{ + return car_get_var(g_timer_fsb); +} diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index 6521a8a..2e0583b 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -20,44 +20,8 @@ #include <thread.h> #include <arch/cpu.h> #include <arch/early_variables.h> -#include <cpu/intel/fsb.h> #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> -#include <cpu/intel/speedstep.h> - -/* NOTE: This code uses global variables, so it can not be used during - * memory init. - */ - -#if CONFIG_UDELAY_LAPIC_FIXED_FSB != 0 -static inline u32 get_timer_fsb(void) -{ - return CONFIG_UDELAY_LAPIC_FIXED_FSB; -} - -static int set_timer_fsb(void) -{ - return 0; -} -#else -static u32 g_timer_fsb CAR_GLOBAL; - -static int set_timer_fsb(void) -{ - int ia32_fsb = get_ia32_fsb(); - - if (ia32_fsb > 0) { - car_set_var(g_timer_fsb, ia32_fsb); - return 0; - } - return -1; -} - -static inline u32 get_timer_fsb(void) -{ - return car_get_var(g_timer_fsb); -} -#endif void init_timer(void) { diff --git a/src/include/delay.h b/src/include/delay.h index 8f894d2..acdd374 100644 --- a/src/include/delay.h +++ b/src/include/delay.h @@ -1,6 +1,24 @@ #ifndef DELAY_H #define DELAY_H +#include <stdint.h> + +#if CONFIG_UDELAY_LAPIC_FIXED_FSB != 0 +static inline u32 get_timer_fsb(void) +{ + return CONFIG_UDELAY_LAPIC_FIXED_FSB; +} + +static int set_timer_fsb(void) +{ + return 0; +} +#else +int set_timer_fsb(void); +u32 get_timer_fsb(void); +#endif + + void init_timer(void); void udelay(unsigned int usecs); -- To view, visit https://review.coreboot.org/c/coreboot/+/34091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib099921d4b8e561daea47219385762bb00fc4548 Gerrit-Change-Number: 34091 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: x86emu: Drop UDELAY_LAPIC dependency
by Kyösti Mälkki (Code Review) 18 Sep '19

18 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34201 ) Change subject: x86emu: Drop UDELAY_LAPIC dependency ...................................................................... x86emu: Drop UDELAY_LAPIC dependency It won't build though, since current_time_from() has been removed. Change-Id: I2f7788f626c0504e6354a08b7986e4d18be140a5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/34201/1 diff --git a/src/Kconfig b/src/Kconfig index b64fdca..ec0f35b 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -976,7 +976,7 @@ config X86EMU_DEBUG_TIMINGS bool "Output timing information" default n - depends on X86EMU_DEBUG && UDELAY_LAPIC && HAVE_MONOTONIC_TIMER + depends on X86EMU_DEBUG && HAVE_MONOTONIC_TIMER help Print timing information needed by i915tool. -- To view, visit https://review.coreboot.org/c/coreboot/+/34201 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f7788f626c0504e6354a08b7986e4d18be140a5 Gerrit-Change-Number: 34201 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mb/google/drallion: Update gpio config for drallion
by Varun Joshi (Code Review) 18 Sep '19

18 Sep '19

Hello Varun Joshi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/35175 to review the following change. Change subject: mb/google/drallion: Update gpio config for drallion ...................................................................... mb/google/drallion: Update gpio config for drallion Signed-off-by: Varun Joshi <varun.joshi(a)intel.com> Change-Id: I78f85a266eb42ea186ff896db5cde0a347339a71 --- M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/drallion/variants/drallion/gpio.c 2 files changed, 90 insertions(+), 89 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/35175/1 diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 54184f0..bedc68e 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -355,7 +355,7 @@ end end # I2C #4 device pci 19.1 off end # I2C #5 - device pci 19.2 off end # UART #2 + device pci 19.2 off end # UART #2 device pci 1a.0 off end # eMMC device pci 1c.0 off end # PCI Express Port 1 (USB) device pci 1c.1 off end # PCI Express Port 2 (USB) @@ -374,7 +374,7 @@ device pci 1d.4 on smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" end # PCI Express Port 13 (x4) - device pci 1e.0 on end # UART #0 + device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 device pci 1e.2 off end # GSPI #0 device pci 1e.3 off end # GSPI #1 diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c index ebe5ee2..087c66b 100644 --- a/src/mainboard/google/drallion/variants/drallion/gpio.c +++ b/src/mainboard/google/drallion/variants/drallion/gpio.c @@ -24,38 +24,39 @@ /* ESPI_IO2 */ /* ESPI_IO3 */ /* ESPI_CS# */ -/* SERIRQ */ -/* PIRQA# */ PAD_NC(GPP_A7, NONE), +/* SERIRQ */ PAD_NC(GPP_A6, NONE), +/* TPM_PIRQ#_A7 */ PAD_CFG_GPI_APIC(GPP_A7, NONE, PLTRST, + EDGE_SINGLE, INVERT), /* CLKRUN# */ PAD_NC(GPP_A8, NONE), /* ESPI_CLK */ /* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), /* PME# */ PAD_NC(GPP_A11, NONE), /* ISH_LID_CL#_TAB */ -/* ISH_GP6 */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF2), +/* ISH_GP6 */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF2), /* ISH_LID_CL#_TAB */ /* SUSWARN# */ PAD_NC(GPP_A13, NONE), /* ESPI_RESET# */ /* SUSACK# */ PAD_NC(GPP_A15, NONE), -/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), -/* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE), +/* SD_1P8_SEL */ PAD_CFG_GPI(GPP_A16, NONE, PLTRST), /* 2.7MM_CAM_DET# */ +/* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF2), /* ISH_P_SENSOR_INT# */ /* ISH_ACC1_INT# */ /* ISH_GP0 */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* ISH_ACC2_INT# */ /* ISH_GP1 */ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), -/* ISH_GP2 */ PAD_NC(GPP_A20, NONE), -/* ISH_GP3 */ PAD_NC(GPP_A21, NONE), +/* ISH_GP2 */ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), /* ISH_TABLE_MODE# */ +/* ISH_GP3 */ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), /* ISH_ALS_INT# */ /* ISH_NB_MODE */ /* ISH_GP4 */ PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1), /* ISH_LID_CL#_NB */ /* ISH_GP5 */ PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), -/* CORE_VID0 */ -/* CORE_VID1 */ -/* VRALERT# */ PAD_NC(GPP_B2, NONE), +/* CORE_VID0 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), +/* CORE_VID1 */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), +/* VRALERT# */ PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), /* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, EDGE_SINGLE, INVERT), /* TOUCHPAD_INTR# */ /* CPU_GP3 */ PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* TOUCH_SCREEN_DET# */ /* LAN_CLKREQ_CPU_N */ -/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), +/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* CARD_CLKREQ_CPU_N */ /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN_CLKREQ_CPU_N */ @@ -64,71 +65,71 @@ /* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* SSD_CKLREQ_CPU_N */ /* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), -/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), /* TBT_CLKREQ_CPU_N (nostuff) */ -/* EXT_PWR_GATE# */ PAD_CFG_GPO(GPP_B11, 0, DEEP), /* 3.3V_CAM_EN# */ +/* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), +/* EXT_PWR_GATE# */ PAD_CFG_GPO(GPP_B11, 0, PLTRST), /* 3.3V_CAM_EN# */ /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), -/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE), /* PRIM_CORE_OPT_DIS (nostuff) */ -/* GSPI0_CLK */ PAD_CFG_GPI(GPP_B16, NONE, DEEP), /* ONE_DIMM# */ +/* GSPI0_CS# */ PAD_CFG_GPO(GPP_B15, 0, PLTRST), /* PRIM_CORE_OPT_DIS */ +/* GSPI0_CLK */ PAD_CFG_GPI(GPP_B16, NONE, PLTRST,), /* ONE_DIMM# */ /* GSPI0_MISO */ PAD_NC(GPP_B17, NONE), /* RTC_DET# */ /* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), /* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* HDD_FALL_INT (nostuff) */ -/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), /* TPM_PIRQ# (nostuff) */ -/* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */ +/* GSPI1_CLK */ PAD_CFG_GPI(GPP_B20, NONE, PLTRST), +/* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 1, PLTRST), /* PCH_3.3V_TS_EN */ /* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), /* SML1ALERT# */ PAD_NC(GPP_B23, DN_20K), -/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* MEM_SMBCLK */ -/* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* MEM_SMBDATA */ +/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* MEM_SMBCLK */ +/* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* MEM_SMBDATA */ /* SMBALERT# */ PAD_NC(GPP_C2, DN_20K), /* SML0CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0_SMBCLK */ /* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0_SMBDATA */ -/* SML0ALERT# */ PAD_NC(GPP_C5, DN_20K), -/* SM1CLK */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* SML1_SMBCLK */ -/* SM1DATA */ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* SML1_SMBDATA */ -/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* SERVOTX_UART */ -/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* SERVORX_UART */ -/* UART0_RTS# */ PAD_CFG_GPI(GPP_C10, NONE, DEEP), /* TYPEC_CON_SEL1 */ -/* UART0_CTS# */ PAD_CFG_GPI(GPP_C11, NONE, DEEP), /* TYPEC_CON_SEL2 */ -/* UART1_RXD */ PAD_CFG_GPI_SCI_LOW(GPP_C12, NONE, DEEP, - EDGE_SINGLE), /* SIO_EXT_WAKE# */ +/* SML0ALERT# */ PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1), + + +/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* SERVOTX_UART */ +/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* SERVOTX_UART */ +/* UART0_RTS# */ PAD_CFG_GPI(GPP_C10, NONE, PLTRST), /* WWAN_FULL_PWR_EN */ +/* UART0_CTS# */ PAD_CFG_GPI(GPP_C11, NONE, PLTRST), /* SBIOS_TX */ +/* UART1_RXD */ PAD_CFG_GPI(GPP_C12, NONE, PLTRST), /* SC_CAGE_DET# */ + /* UART1_TXD */ PAD_NC(GPP_C13, NONE), -/* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* LCD_CBL_DET# */ -/* UART1_CTS# */ PAD_NC(GPP_C15, NONE), +/* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, PLTRST), /* LCD_CBL_DET# */ +/* UART1_CTS# */ PAD_CFG_GPO(GPP_C15, 0, PLTRST), /* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TS_I2C_SDA */ /* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TS_I2C_SCL */ /* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* I2C1_SDA_TP */ /* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* I2C1_SCK_TP */ -/* UART2_RXD */ PAD_NC(GPP_C20, NONE), -/* UART2_TXD */ PAD_NC(GPP_C21, NONE), -/* UART2_RTS# */ PAD_NC(GPP_C22, NONE), +/* UART2_RXD */ PAD_NC(GPP_C20, NONE), +/* UART2_TXD */ PAD_NC(GPP_C21, NONE), +/* UART2_RTS# */ PAD_CFG_GPI(GPP_C22, NONE, PLTRST), /* SMART_SPK_DET1# */ /* UART2_CTS# */ PAD_CFG_GPI_APIC(GPP_C23, NONE, PLTRST, LEVEL, NONE), /* TS_INT# */ /* SPI1_CS# */ PAD_CFG_GPI_APIC(GPP_D0, NONE, PLTRST, EDGE_SINGLE, INVERT), /* MEDIACARD_IRQ# */ -/* SPI1_CLK */ PAD_NC(GPP_D1, NONE), -/* SPI1_MISO */ PAD_CFG_GPI(GPP_D2, NONE, DEEP), /* ISH_LAN# */ -/* SPI1_MOSI */ PAD_NC(GPP_D3, NONE), -/* FASHTRIG */ PAD_NC(GPP_D4, NONE), /* TBT_FORCE_PWR (nostuff) */ +/* SPI1_CLK */ PAD_CFG_GPI(GPP_D1, NONE, DEEP), /* VPRO_DET# */ +/* SPI1_MISO */ PAD_NC(GPP_D2, NONE), +/* SPI1_MOSI */ PAD_CFG_GPI(GPP_D3, NONE, PLTRST), /* RTC_DET# */ +/* FASHTRIG */ PAD_CFG_GPO(GPP_D4, 0, PLTRST), /* ISH_I2C0_ACC_SDA */ /* ISH_I2C0_SDA */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* ISH_I2C0_ACC_SCL */ /* ISH_I2C0_SCL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), -/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), -/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), -/* ISH_SPI_CS# */ PAD_CFG_GPI(GPP_D9, NONE, DEEP), /* IR_CAM_DET# */ +/* ISH_I2C1_SDA */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), +/* ISH_I2C1_SCL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), +/* ISH_SPI_CS# */ PAD_CFG_GPI(GPP_D9, NONE, PLTRST), /* IR_CAM_DET# */ /* ISH_SPI_CLK */ PAD_NC(GPP_D10, NONE), -/* ISH_SPI_MISO */ PAD_CFG_GPI(GPP_D11, NONE, DEEP), /* TBT_DET# */ +/* ISH_SPI_MISO */ PAD_CFG_GPI(GPP_D11, NONE, PLTRST), /* TBT_RTD3_WAKE# */ /* ISH_SPI_MOSI */ PAD_NC(GPP_D12, NONE), /* ISH_CPU_UART0_RX */ /* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, UP_20K, DEEP, NF1), /* ISH_CPU_UART0_TX */ /* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), -/* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 1, DEEP), /* WWAN_FULL_PWR_EN */ -/* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE), -/* DMIC_CLK1 */ PAD_CFG_GPI(GPP_D17, NONE, DEEP), /* KB_DET# */ +/* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 1, PLTRST), /* RTD3_CIO_PWR_EN */ +/* ISH_UART0_CTS# */ PAD_CFG_GPI(GPP_D16, NONE, PLTRST), +/* DMIC_CLK1 */ PAD_CFG_GPI(GPP_D17, NONE, PLTRST), /* KB_DET# */ /* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST, EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */ /* DMIC_CLK0 */ PAD_NC(GPP_D19, NONE), @@ -138,77 +139,77 @@ /* I2S_MCLK */ PAD_CFG_GPI_SCI_LOW(GPP_D23, NONE, DEEP, EDGE_SINGLE), /* WWAN_GPIO_WAKE# */ -/* SATAXPCIE0 */ PAD_NC(GPP_E0, NONE), +/* SATAXPCIE0 */ PAD_CFG_NF(GPP_E0, NONE, DEEP, NF2), /* HDD_DET# */ /* M3042_PCIE#_SATA */ -/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), +/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF2), /* M2880_PCIE_SATA# */ -/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), -/* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */ +/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF2), +/* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, PLTRST), /* MEM_INTERLEAVED */ /* SATA_DEVSLP0 */ PAD_NC(GPP_E4, NONE), /* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* M3042_DEVSLP */ /* SATA_DEVSLP2 */ PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), /* M2280_DEVSLP */ -/* CPU_GP1 */ PAD_CFG_GPO(GPP_E7, 1, DEEP), /* TOUCH_SCREEN_PD# */ -/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */ +/* CPU_GP1 */ PAD_CFG_GPO(GPP_E7, 1, PLTRST), /* TOUCH_SCREEN_PD# */ +/* SATALED# */ PAD_CFG_GPO(GPP_E8, 1, PLTRST), /* SECURE_BIO */ /* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_OC0# */ /* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB_OC1# */ -/* USB2_OC2# */ PAD_NC(GPP_E11, NONE), -/* USB2_OC3# */ PAD_NC(GPP_E12, NONE), +/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), +/* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DP_HPD_CPU */ /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DP2_HPD_CPU */ -/* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* PCH_WP */ -/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), /* FFS_INT2 (nostuff) */ +/* DDPD_HPD2 */ PAD_CFG_GPO(GPP_E15, 1, PLTRST), /* HDMI_PD# */ +/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), -/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* HDMI_SCL_CPU */ -/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* HDMI_SDA_CPU */ -/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), -/* DDPC_CTRLDATA */ PAD_NC(GPP_E21, NONE), +/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* CPU_DP1_CTRL_CLK */ +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* CPU_DP1_CTRL_CLK */ +/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* CPU_DP2_CTRL_CLK */ +/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* CPU_DP2_CTRL_CLK */ /* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), /* DDPD_CTRLDATA */ PAD_NC(GPP_E23, NONE), /* CNV_PA_BLANKING */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* CNV_COEX3 */ -/* GPP_F1 */ PAD_NC(GPP_F1, NONE), -/* GPP_F2 */ PAD_NC(GPP_F2, NONE), +/* GPP_F1 */ PAD_CFG_GPI(GPP_F1, NONE, DEEP), /* DDR_CHA_EN_1P8 */ +/* GPP_F2 */ PAD_CFG_GPI(GPP_F2, NONE, DEEP), /* DDR_CHB_EN_1P8 */ /* GPP_F3 */ PAD_NC(GPP_F3, NONE), -/* CNV_BRI_DT */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), -/* CNV_BRI_RSP */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), -/* CNV_RGI_DT */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), -/* CNV_RGI_RSP */ PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), +/* CNV_BRI_DT */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* CNV_BRI_PTX_DRX_1P8 */ +/* CNV_BRI_RSP */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), /* CNV_BRI_BRX_DTX_1P8 */ +/* CNV_RGI_DT */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), /* CNV_RGI_PTX_DRX_1P8 */ +/* CNV_RGI_RSP */ PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), /* CNV_RGI_PRX_DTX_1P8 */ /* CNV_MFUART2_RXD */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* CNV_COEX2 */ /* CNV_MFUART2_TXD */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* CNV_COEX1 */ /* GPP_F10 */ PAD_NC(GPP_F10, NONE), /* EMMC_CMD */ PAD_NC(GPP_F11, NONE), -/* EMMC_DATA0 */ PAD_NC(GPP_F12, NONE), -/* EMMC_DATA1 */ PAD_NC(GPP_F13, NONE), -/* EMMC_DATA2 */ PAD_NC(GPP_F14, NONE), -/* EMMC_DATA3 */ PAD_NC(GPP_F15, NONE), -/* EMMC_DATA4 */ PAD_NC(GPP_F16, NONE), +/* EMMC_DATA0 */ PAD_CFG_GPI(GPP_F12, NONE, DEEP), /* MEM_CONFIGO_1P8 */ +/* EMMC_DATA1 */ PAD_CFG_GPI(GPP_F13, NONE, DEEP), /* MEM_CONFIGO_1P8 */ +/* EMMC_DATA2 */ PAD_CFG_GPI(GPP_F14, NONE, DEEP), /* MEM_CONFIGO_1P8 */ +/* EMMC_DATA3 */ PAD_CFG_GPI(GPP_F15, NONE, DEEP), /* MEM_CONFIGO_1P8 */ +/* EMMC_DATA4 */ PAD_CFG_GPI(GPP_F16, NONE, DEEP), /* MEM_CONFIGO_1P8 */ /* EMMC_DATA5 */ PAD_NC(GPP_F17, NONE), /* EMMC_DATA6 */ PAD_NC(GPP_F18, NONE), /* EMMC_DATA7 */ PAD_NC(GPP_F19, NONE), /* EMMC_RCLK */ PAD_NC(GPP_F20, NONE), /* EMMC_CLK */ PAD_NC(GPP_F21, NONE), /* EMMC_RESET# */ PAD_NC(GPP_F22, NONE), -/* A4WP_PRESENT */ PAD_NC(GPP_F23, NONE), +/* A4WP_PRESENT */ PAD_CFG_NF(GPP_F23, NONE, PLTRST, NF1), -/* SD_CMD */ PAD_CFG_GPI(GPP_G0, NONE, DEEP), /* CAM_MIC_CBL_DET# */ +/* SD_CMD */ PAD_CFG_GPI(GPP_G0, NONE, PLTRST), /* CAM_MIC_CBL_DET# */ /* SD_DATA0 */ PAD_NC(GPP_G1, NONE), /* ANT_CONFIG (nostuff) */ -/* SD_DATA1 */ PAD_NC(GPP_G2, NONE), /* TBT_CIO_PLUG_EVT# (nostuff) */ +/* SD_DATA1 */ PAD_CFG_GPI(GPP_G2, NONE, PLTRST), /* TBT_CIO_PLUG_EVT# (nostuff) */ /* SD_DATA2 */ PAD_NC(GPP_G3, NONE), -/* SD_DATA3 */ PAD_CFG_GPI(GPP_G4, NONE, DEEP), /* CTLESS_DET# */ -/* SD_CD# */ PAD_CFG_GPO(GPP_G5, 1, DEEP), /* HOST_SD_WP# */ -/* SD_CLK */ PAD_CFG_GPO(GPP_G6, 1, DEEP), /* AUD_PWR_EN */ -/* SD_WP */ PAD_CFG_GPI(GPP_G7, NONE, DEEP), /* SPK_DET# */ +/* SD_DATA3 */ PAD_CFG_GPI(GPP_G4, NONE, PLTRST), /* CTLESS_DET# */ +/* SD_CD# */ PAD_CFG_GPO(GPP_G5, 1, PLTRST), /* HOST_SD_WP# */ +/* SD_CLK */ PAD_CFG_GPO(GPP_G6, 1, PLTRST), /* AUD_PWR_EN */ +/* SD_WP */ PAD_CFG_GPI(GPP_G7, NONE, PLTRST), /* SPK_DET# */ /* I2S2_SCLK */ PAD_NC(GPP_H0, NONE), /* I2S2_SFRM */ PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), /* CNV_RF_RESET# */ /* I2S2_TXD */ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), /* CLKREQ_CNV# */ -/* I2S2_RXD */ PAD_NC(GPP_H3, NONE), +/* I2S2_RXD */ PAD_CFG_GPI(GPP_H3, NONE, DEEP), /* CNVI_EN# */ /* I2C2_SDA */ PAD_NC(GPP_H4, NONE), -/* I2C2_SCL */ PAD_NC(GPP_H5, NONE), +/* I2C2_SCL */ PAD_CFG_GPI(GPP_H5, NONE, PLTRST), /* 360_SENSOR_DET# */ /* I2C3_SDA */ PAD_NC(GPP_H6, NONE), /* I2C3_SCL */ PAD_NC(GPP_H7, NONE), -/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */ -/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */ +/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA__PCH_H1 */ +/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_PCH_H1 */ /* I2C5_SDA */ PAD_NC(GPP_H10, NONE), /* ISH_I2C2_SDA */ /* I2C5_SCL */ PAD_NC(GPP_H11, NONE), /* ISH_I2C2_SCL */ /* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE), @@ -219,7 +220,7 @@ /* TIMESYNC0 */ PAD_NC(GPP_H19, NONE), /* IMGCLKOUT1 */ PAD_NC(GPP_H20, NONE), /* GPP_H21 */ PAD_NC(GPP_H21, NONE), -/* GPP_H22 */ PAD_NC(GPP_H22, NONE), /* RTD3_CIO_PWR_EN (nostuff) */ +/* GPP_H22 */ PAD_NC(GPP_H22, NONE), /* GPP_H23 */ PAD_NC(GPP_H23, NONE), /* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* BATLOW# */ @@ -229,11 +230,11 @@ /* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SIO_SLP_S3# */ /* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* SIO_SLP_S4# */ /* SLP_A# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), /* SIO_SLP_A# */ -/* GPD7 */ PAD_NC(GPD7, NONE), /* TBT_RTD3_WAKE# (nostuff) */ +/* GPD7 */ PAD_NC(GPD7, NONE), /* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SUSCLK */ /* SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1), /* SIO_SLP_WLAN# */ /* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), /* SIO_SLP_S5# */ -/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), /* PM_LANPHY_EN */ +/* LANPHYC */ PAD_NC(GPD11, NONE), /* PM_LANPHY_EN */ }; /* Early pad configuration in bootblock */ @@ -241,10 +242,10 @@ /* M2_SKT2_CFG1 */ PAD_CFG_GPO(GPP_H13, 1, DEEP), /* M.2 SSD D3 cold */ /* SSD RESET pin will stay low first */ /* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 0, DEEP), /* D3 cold RST */ -/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */ -/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */ -/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */ -/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */ +/* UART2_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* SERVOTX_UART */ +/* UART2_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* SERVORX_UART */ +/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_PCH_H1 */ +/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_PCH_H1 */ /* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST, EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */ /* RESET# need to stay low before FULL_CARD_POWER_OFF assert */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35175 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78f85a266eb42ea186ff896db5cde0a347339a71 Gerrit-Change-Number: 35175 Gerrit-PatchSet: 1 Gerrit-Owner: Varun Joshi <varun.joshi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Varun Joshi <varun.joshi(a)intel.com> Gerrit-MessageType: newchange

7 38

Change in ...coreboot[master]: cpu/intel/common: Use common tsc_freq_mhz()
by Kyösti Mälkki (Code Review) 18 Sep '19

18 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31342 Change subject: cpu/intel/common: Use common tsc_freq_mhz() ...................................................................... cpu/intel/common: Use common tsc_freq_mhz() Change-Id: I0e7159039751a88d86b6c343be5f085e6e15570a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/common/fsb.c M src/cpu/intel/haswell/Makefile.inc D src/cpu/intel/haswell/tsc_freq.c M src/cpu/intel/model_2065x/Makefile.inc D src/cpu/intel/model_2065x/tsc_freq.c M src/cpu/intel/model_206ax/Makefile.inc D src/cpu/intel/model_206ax/tsc_freq.c 7 files changed, 12 insertions(+), 90 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/31342/1 diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c index d06739c..f53baa0 100644 --- a/src/cpu/intel/common/fsb.c +++ b/src/cpu/intel/common/fsb.c @@ -13,6 +13,7 @@ #include <cpu/cpu.h> #include <cpu/x86/msr.h> +#include <cpu/x86/tsc.h> #include <cpu/intel/speedstep.h> #include <cpu/intel/fsb.h> #include <console/console.h> @@ -105,3 +106,14 @@ printk(BIOS_ERR, "FSB not supported or not found\n"); return -1; } + +unsigned long tsc_freq_mhz(void) +{ + int ret, fsb, ratio; + + ret = get_fsb_tsc(&fsb, &ratio); + if (ret < 0) + die("TSC frequency not known\n"); + + return 100 * DIV_ROUND_CLOSEST(ratio * fsb, 100); +} diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index c317c09..87da59b 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -1,7 +1,5 @@ ramstage-y += haswell_init.c -ramstage-y += tsc_freq.c romstage-y += romstage.c -romstage-y += tsc_freq.c romstage-y += ../car/romstage.c ramstage-y += acpi.c @@ -12,7 +10,6 @@ postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c ifneq ($(CONFIG_TSC_MONOTONIC_TIMER),y) ramstage-y += monotonic_timer.c diff --git a/src/cpu/intel/haswell/tsc_freq.c b/src/cpu/intel/haswell/tsc_freq.c deleted file mode 100644 index b05cae5..0000000 --- a/src/cpu/intel/haswell/tsc_freq.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/tsc.h> -#include "cpu/intel/haswell/haswell.h" - -unsigned long tsc_freq_mhz(void) -{ - msr_t platform_info; - - platform_info = rdmsr(MSR_PLATFORM_INFO); - return HASWELL_BCLK * ((platform_info.lo >> 8) & 0xff); -} diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc index ec8643a..b8e474d 100644 --- a/src/cpu/intel/model_2065x/Makefile.inc +++ b/src/cpu/intel/model_2065x/Makefile.inc @@ -10,9 +10,6 @@ subdirs-y += ../smm/gen1 subdirs-y += ../common -ramstage-y += tsc_freq.c -romstage-y += tsc_freq.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c ramstage-y += acpi.c diff --git a/src/cpu/intel/model_2065x/tsc_freq.c b/src/cpu/intel/model_2065x/tsc_freq.c deleted file mode 100644 index 041785b..0000000 --- a/src/cpu/intel/model_2065x/tsc_freq.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/tsc.h> -#include "model_2065x.h" - -unsigned long tsc_freq_mhz(void) -{ - msr_t platform_info; - - platform_info = rdmsr(MSR_PLATFORM_INFO); - return NEHALEM_BCLK * ((platform_info.lo >> 8) & 0xff); -} diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index d193e60..6339ba0 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -17,9 +17,6 @@ romstage-y += common.c smm-$(CONFIG_HAVE_SMI_HANDLER) += common.c -ramstage-y += tsc_freq.c -romstage-y += tsc_freq.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c diff --git a/src/cpu/intel/model_206ax/tsc_freq.c b/src/cpu/intel/model_206ax/tsc_freq.c deleted file mode 100644 index 545ca5f..0000000 --- a/src/cpu/intel/model_206ax/tsc_freq.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/tsc.h> -#include "model_206ax.h" - -unsigned long tsc_freq_mhz(void) -{ - msr_t platform_info; - - platform_info = rdmsr(MSR_PLATFORM_INFO); - return SANDYBRIDGE_BCLK * ((platform_info.lo >> 8) & 0xff); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/31342 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e7159039751a88d86b6c343be5f085e6e15570a Gerrit-Change-Number: 31342 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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