Hello Varun Joshi,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/35175
to review the following change.
Change subject: mb/google/drallion: Update gpio config for drallion ......................................................................
mb/google/drallion: Update gpio config for drallion
Signed-off-by: Varun Joshi varun.joshi@intel.com Change-Id: I78f85a266eb42ea186ff896db5cde0a347339a71 --- M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/drallion/variants/drallion/gpio.c 2 files changed, 90 insertions(+), 89 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/35175/1
diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 54184f0..bedc68e 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -355,7 +355,7 @@ end end # I2C #4 device pci 19.1 off end # I2C #5 - device pci 19.2 off end # UART #2 + device pci 19.2 off end # UART #2 device pci 1a.0 off end # eMMC device pci 1c.0 off end # PCI Express Port 1 (USB) device pci 1c.1 off end # PCI Express Port 2 (USB) @@ -374,7 +374,7 @@ device pci 1d.4 on smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" end # PCI Express Port 13 (x4) - device pci 1e.0 on end # UART #0 + device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 device pci 1e.2 off end # GSPI #0 device pci 1e.3 off end # GSPI #1 diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c index ebe5ee2..087c66b 100644 --- a/src/mainboard/google/drallion/variants/drallion/gpio.c +++ b/src/mainboard/google/drallion/variants/drallion/gpio.c @@ -24,38 +24,39 @@ /* ESPI_IO2 */ /* ESPI_IO3 */ /* ESPI_CS# */ -/* SERIRQ */ -/* PIRQA# */ PAD_NC(GPP_A7, NONE), +/* SERIRQ */ PAD_NC(GPP_A6, NONE), +/* TPM_PIRQ#_A7 */ PAD_CFG_GPI_APIC(GPP_A7, NONE, PLTRST, + EDGE_SINGLE, INVERT), /* CLKRUN# */ PAD_NC(GPP_A8, NONE), /* ESPI_CLK */ /* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), /* PME# */ PAD_NC(GPP_A11, NONE), /* ISH_LID_CL#_TAB */ -/* ISH_GP6 */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF2), +/* ISH_GP6 */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF2), /* ISH_LID_CL#_TAB */ /* SUSWARN# */ PAD_NC(GPP_A13, NONE), /* ESPI_RESET# */ /* SUSACK# */ PAD_NC(GPP_A15, NONE), -/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), -/* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE), +/* SD_1P8_SEL */ PAD_CFG_GPI(GPP_A16, NONE, PLTRST), /* 2.7MM_CAM_DET# */ +/* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF2), /* ISH_P_SENSOR_INT# */ /* ISH_ACC1_INT# */ /* ISH_GP0 */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* ISH_ACC2_INT# */ /* ISH_GP1 */ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), -/* ISH_GP2 */ PAD_NC(GPP_A20, NONE), -/* ISH_GP3 */ PAD_NC(GPP_A21, NONE), +/* ISH_GP2 */ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), /* ISH_TABLE_MODE# */ +/* ISH_GP3 */ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), /* ISH_ALS_INT# */ /* ISH_NB_MODE */ /* ISH_GP4 */ PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1), /* ISH_LID_CL#_NB */ /* ISH_GP5 */ PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1),
-/* CORE_VID0 */ -/* CORE_VID1 */ -/* VRALERT# */ PAD_NC(GPP_B2, NONE), +/* CORE_VID0 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), +/* CORE_VID1 */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), +/* VRALERT# */ PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), /* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, EDGE_SINGLE, INVERT), /* TOUCHPAD_INTR# */ /* CPU_GP3 */ PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* TOUCH_SCREEN_DET# */ /* LAN_CLKREQ_CPU_N */ -/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), +/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* CARD_CLKREQ_CPU_N */ /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN_CLKREQ_CPU_N */ @@ -64,71 +65,71 @@ /* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* SSD_CKLREQ_CPU_N */ /* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), -/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), /* TBT_CLKREQ_CPU_N (nostuff) */ -/* EXT_PWR_GATE# */ PAD_CFG_GPO(GPP_B11, 0, DEEP), /* 3.3V_CAM_EN# */ +/* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), +/* EXT_PWR_GATE# */ PAD_CFG_GPO(GPP_B11, 0, PLTRST), /* 3.3V_CAM_EN# */ /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), -/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE), /* PRIM_CORE_OPT_DIS (nostuff) */ -/* GSPI0_CLK */ PAD_CFG_GPI(GPP_B16, NONE, DEEP), /* ONE_DIMM# */ +/* GSPI0_CS# */ PAD_CFG_GPO(GPP_B15, 0, PLTRST), /* PRIM_CORE_OPT_DIS */ +/* GSPI0_CLK */ PAD_CFG_GPI(GPP_B16, NONE, PLTRST,), /* ONE_DIMM# */ /* GSPI0_MISO */ PAD_NC(GPP_B17, NONE), /* RTC_DET# */ /* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), /* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* HDD_FALL_INT (nostuff) */ -/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), /* TPM_PIRQ# (nostuff) */ -/* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */ +/* GSPI1_CLK */ PAD_CFG_GPI(GPP_B20, NONE, PLTRST), +/* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 1, PLTRST), /* PCH_3.3V_TS_EN */ /* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), /* SML1ALERT# */ PAD_NC(GPP_B23, DN_20K),
-/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* MEM_SMBCLK */ -/* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* MEM_SMBDATA */ +/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* MEM_SMBCLK */ +/* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* MEM_SMBDATA */ /* SMBALERT# */ PAD_NC(GPP_C2, DN_20K), /* SML0CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0_SMBCLK */ /* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0_SMBDATA */ -/* SML0ALERT# */ PAD_NC(GPP_C5, DN_20K), -/* SM1CLK */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* SML1_SMBCLK */ -/* SM1DATA */ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* SML1_SMBDATA */ -/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* SERVOTX_UART */ -/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* SERVORX_UART */ -/* UART0_RTS# */ PAD_CFG_GPI(GPP_C10, NONE, DEEP), /* TYPEC_CON_SEL1 */ -/* UART0_CTS# */ PAD_CFG_GPI(GPP_C11, NONE, DEEP), /* TYPEC_CON_SEL2 */ -/* UART1_RXD */ PAD_CFG_GPI_SCI_LOW(GPP_C12, NONE, DEEP, - EDGE_SINGLE), /* SIO_EXT_WAKE# */ +/* SML0ALERT# */ PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1), + + +/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* SERVOTX_UART */ +/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* SERVOTX_UART */ +/* UART0_RTS# */ PAD_CFG_GPI(GPP_C10, NONE, PLTRST), /* WWAN_FULL_PWR_EN */ +/* UART0_CTS# */ PAD_CFG_GPI(GPP_C11, NONE, PLTRST), /* SBIOS_TX */ +/* UART1_RXD */ PAD_CFG_GPI(GPP_C12, NONE, PLTRST), /* SC_CAGE_DET# */ + /* UART1_TXD */ PAD_NC(GPP_C13, NONE), -/* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* LCD_CBL_DET# */ -/* UART1_CTS# */ PAD_NC(GPP_C15, NONE), +/* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, PLTRST), /* LCD_CBL_DET# */ +/* UART1_CTS# */ PAD_CFG_GPO(GPP_C15, 0, PLTRST), /* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TS_I2C_SDA */ /* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TS_I2C_SCL */ /* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* I2C1_SDA_TP */ /* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* I2C1_SCK_TP */ -/* UART2_RXD */ PAD_NC(GPP_C20, NONE), -/* UART2_TXD */ PAD_NC(GPP_C21, NONE), -/* UART2_RTS# */ PAD_NC(GPP_C22, NONE), +/* UART2_RXD */ PAD_NC(GPP_C20, NONE), +/* UART2_TXD */ PAD_NC(GPP_C21, NONE), +/* UART2_RTS# */ PAD_CFG_GPI(GPP_C22, NONE, PLTRST), /* SMART_SPK_DET1# */ /* UART2_CTS# */ PAD_CFG_GPI_APIC(GPP_C23, NONE, PLTRST, LEVEL, NONE), /* TS_INT# */
/* SPI1_CS# */ PAD_CFG_GPI_APIC(GPP_D0, NONE, PLTRST, EDGE_SINGLE, INVERT), /* MEDIACARD_IRQ# */ -/* SPI1_CLK */ PAD_NC(GPP_D1, NONE), -/* SPI1_MISO */ PAD_CFG_GPI(GPP_D2, NONE, DEEP), /* ISH_LAN# */ -/* SPI1_MOSI */ PAD_NC(GPP_D3, NONE), -/* FASHTRIG */ PAD_NC(GPP_D4, NONE), /* TBT_FORCE_PWR (nostuff) */ +/* SPI1_CLK */ PAD_CFG_GPI(GPP_D1, NONE, DEEP), /* VPRO_DET# */ +/* SPI1_MISO */ PAD_NC(GPP_D2, NONE), +/* SPI1_MOSI */ PAD_CFG_GPI(GPP_D3, NONE, PLTRST), /* RTC_DET# */ +/* FASHTRIG */ PAD_CFG_GPO(GPP_D4, 0, PLTRST), /* ISH_I2C0_ACC_SDA */ /* ISH_I2C0_SDA */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* ISH_I2C0_ACC_SCL */ /* ISH_I2C0_SCL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), -/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), -/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), -/* ISH_SPI_CS# */ PAD_CFG_GPI(GPP_D9, NONE, DEEP), /* IR_CAM_DET# */ +/* ISH_I2C1_SDA */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), +/* ISH_I2C1_SCL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), +/* ISH_SPI_CS# */ PAD_CFG_GPI(GPP_D9, NONE, PLTRST), /* IR_CAM_DET# */ /* ISH_SPI_CLK */ PAD_NC(GPP_D10, NONE), -/* ISH_SPI_MISO */ PAD_CFG_GPI(GPP_D11, NONE, DEEP), /* TBT_DET# */ +/* ISH_SPI_MISO */ PAD_CFG_GPI(GPP_D11, NONE, PLTRST), /* TBT_RTD3_WAKE# */ /* ISH_SPI_MOSI */ PAD_NC(GPP_D12, NONE), /* ISH_CPU_UART0_RX */ /* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, UP_20K, DEEP, NF1), /* ISH_CPU_UART0_TX */ /* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), -/* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 1, DEEP), /* WWAN_FULL_PWR_EN */ -/* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE), -/* DMIC_CLK1 */ PAD_CFG_GPI(GPP_D17, NONE, DEEP), /* KB_DET# */ +/* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 1, PLTRST), /* RTD3_CIO_PWR_EN */ +/* ISH_UART0_CTS# */ PAD_CFG_GPI(GPP_D16, NONE, PLTRST), +/* DMIC_CLK1 */ PAD_CFG_GPI(GPP_D17, NONE, PLTRST), /* KB_DET# */ /* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST, EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */ /* DMIC_CLK0 */ PAD_NC(GPP_D19, NONE), @@ -138,77 +139,77 @@ /* I2S_MCLK */ PAD_CFG_GPI_SCI_LOW(GPP_D23, NONE, DEEP, EDGE_SINGLE), /* WWAN_GPIO_WAKE# */
-/* SATAXPCIE0 */ PAD_NC(GPP_E0, NONE), +/* SATAXPCIE0 */ PAD_CFG_NF(GPP_E0, NONE, DEEP, NF2), /* HDD_DET# */ /* M3042_PCIE#_SATA */ -/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), +/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF2), /* M2880_PCIE_SATA# */ -/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), -/* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */ +/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF2), +/* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, PLTRST), /* MEM_INTERLEAVED */ /* SATA_DEVSLP0 */ PAD_NC(GPP_E4, NONE), /* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* M3042_DEVSLP */ /* SATA_DEVSLP2 */ PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), /* M2280_DEVSLP */ -/* CPU_GP1 */ PAD_CFG_GPO(GPP_E7, 1, DEEP), /* TOUCH_SCREEN_PD# */ -/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */ +/* CPU_GP1 */ PAD_CFG_GPO(GPP_E7, 1, PLTRST), /* TOUCH_SCREEN_PD# */ +/* SATALED# */ PAD_CFG_GPO(GPP_E8, 1, PLTRST), /* SECURE_BIO */ /* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_OC0# */ /* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB_OC1# */ -/* USB2_OC2# */ PAD_NC(GPP_E11, NONE), -/* USB2_OC3# */ PAD_NC(GPP_E12, NONE), +/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), +/* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DP_HPD_CPU */ /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DP2_HPD_CPU */ -/* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* PCH_WP */ -/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), /* FFS_INT2 (nostuff) */ +/* DDPD_HPD2 */ PAD_CFG_GPO(GPP_E15, 1, PLTRST), /* HDMI_PD# */ +/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), -/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* HDMI_SCL_CPU */ -/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* HDMI_SDA_CPU */ -/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), -/* DDPC_CTRLDATA */ PAD_NC(GPP_E21, NONE), +/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* CPU_DP1_CTRL_CLK */ +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* CPU_DP1_CTRL_CLK */ +/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* CPU_DP2_CTRL_CLK */ +/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* CPU_DP2_CTRL_CLK */ /* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), /* DDPD_CTRLDATA */ PAD_NC(GPP_E23, NONE),
/* CNV_PA_BLANKING */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* CNV_COEX3 */ -/* GPP_F1 */ PAD_NC(GPP_F1, NONE), -/* GPP_F2 */ PAD_NC(GPP_F2, NONE), +/* GPP_F1 */ PAD_CFG_GPI(GPP_F1, NONE, DEEP), /* DDR_CHA_EN_1P8 */ +/* GPP_F2 */ PAD_CFG_GPI(GPP_F2, NONE, DEEP), /* DDR_CHB_EN_1P8 */ /* GPP_F3 */ PAD_NC(GPP_F3, NONE), -/* CNV_BRI_DT */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), -/* CNV_BRI_RSP */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), -/* CNV_RGI_DT */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), -/* CNV_RGI_RSP */ PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), +/* CNV_BRI_DT */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* CNV_BRI_PTX_DRX_1P8 */ +/* CNV_BRI_RSP */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), /* CNV_BRI_BRX_DTX_1P8 */ +/* CNV_RGI_DT */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), /* CNV_RGI_PTX_DRX_1P8 */ +/* CNV_RGI_RSP */ PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), /* CNV_RGI_PRX_DTX_1P8 */ /* CNV_MFUART2_RXD */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* CNV_COEX2 */ /* CNV_MFUART2_TXD */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* CNV_COEX1 */ /* GPP_F10 */ PAD_NC(GPP_F10, NONE), /* EMMC_CMD */ PAD_NC(GPP_F11, NONE), -/* EMMC_DATA0 */ PAD_NC(GPP_F12, NONE), -/* EMMC_DATA1 */ PAD_NC(GPP_F13, NONE), -/* EMMC_DATA2 */ PAD_NC(GPP_F14, NONE), -/* EMMC_DATA3 */ PAD_NC(GPP_F15, NONE), -/* EMMC_DATA4 */ PAD_NC(GPP_F16, NONE), +/* EMMC_DATA0 */ PAD_CFG_GPI(GPP_F12, NONE, DEEP), /* MEM_CONFIGO_1P8 */ +/* EMMC_DATA1 */ PAD_CFG_GPI(GPP_F13, NONE, DEEP), /* MEM_CONFIGO_1P8 */ +/* EMMC_DATA2 */ PAD_CFG_GPI(GPP_F14, NONE, DEEP), /* MEM_CONFIGO_1P8 */ +/* EMMC_DATA3 */ PAD_CFG_GPI(GPP_F15, NONE, DEEP), /* MEM_CONFIGO_1P8 */ +/* EMMC_DATA4 */ PAD_CFG_GPI(GPP_F16, NONE, DEEP), /* MEM_CONFIGO_1P8 */ /* EMMC_DATA5 */ PAD_NC(GPP_F17, NONE), /* EMMC_DATA6 */ PAD_NC(GPP_F18, NONE), /* EMMC_DATA7 */ PAD_NC(GPP_F19, NONE), /* EMMC_RCLK */ PAD_NC(GPP_F20, NONE), /* EMMC_CLK */ PAD_NC(GPP_F21, NONE), /* EMMC_RESET# */ PAD_NC(GPP_F22, NONE), -/* A4WP_PRESENT */ PAD_NC(GPP_F23, NONE), +/* A4WP_PRESENT */ PAD_CFG_NF(GPP_F23, NONE, PLTRST, NF1),
-/* SD_CMD */ PAD_CFG_GPI(GPP_G0, NONE, DEEP), /* CAM_MIC_CBL_DET# */ +/* SD_CMD */ PAD_CFG_GPI(GPP_G0, NONE, PLTRST), /* CAM_MIC_CBL_DET# */ /* SD_DATA0 */ PAD_NC(GPP_G1, NONE), /* ANT_CONFIG (nostuff) */ -/* SD_DATA1 */ PAD_NC(GPP_G2, NONE), /* TBT_CIO_PLUG_EVT# (nostuff) */ +/* SD_DATA1 */ PAD_CFG_GPI(GPP_G2, NONE, PLTRST), /* TBT_CIO_PLUG_EVT# (nostuff) */ /* SD_DATA2 */ PAD_NC(GPP_G3, NONE), -/* SD_DATA3 */ PAD_CFG_GPI(GPP_G4, NONE, DEEP), /* CTLESS_DET# */ -/* SD_CD# */ PAD_CFG_GPO(GPP_G5, 1, DEEP), /* HOST_SD_WP# */ -/* SD_CLK */ PAD_CFG_GPO(GPP_G6, 1, DEEP), /* AUD_PWR_EN */ -/* SD_WP */ PAD_CFG_GPI(GPP_G7, NONE, DEEP), /* SPK_DET# */ +/* SD_DATA3 */ PAD_CFG_GPI(GPP_G4, NONE, PLTRST), /* CTLESS_DET# */ +/* SD_CD# */ PAD_CFG_GPO(GPP_G5, 1, PLTRST), /* HOST_SD_WP# */ +/* SD_CLK */ PAD_CFG_GPO(GPP_G6, 1, PLTRST), /* AUD_PWR_EN */ +/* SD_WP */ PAD_CFG_GPI(GPP_G7, NONE, PLTRST), /* SPK_DET# */
/* I2S2_SCLK */ PAD_NC(GPP_H0, NONE), /* I2S2_SFRM */ PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), /* CNV_RF_RESET# */ /* I2S2_TXD */ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), /* CLKREQ_CNV# */ -/* I2S2_RXD */ PAD_NC(GPP_H3, NONE), +/* I2S2_RXD */ PAD_CFG_GPI(GPP_H3, NONE, DEEP), /* CNVI_EN# */ /* I2C2_SDA */ PAD_NC(GPP_H4, NONE), -/* I2C2_SCL */ PAD_NC(GPP_H5, NONE), +/* I2C2_SCL */ PAD_CFG_GPI(GPP_H5, NONE, PLTRST), /* 360_SENSOR_DET# */ /* I2C3_SDA */ PAD_NC(GPP_H6, NONE), /* I2C3_SCL */ PAD_NC(GPP_H7, NONE), -/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */ -/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */ +/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA__PCH_H1 */ +/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_PCH_H1 */ /* I2C5_SDA */ PAD_NC(GPP_H10, NONE), /* ISH_I2C2_SDA */ /* I2C5_SCL */ PAD_NC(GPP_H11, NONE), /* ISH_I2C2_SCL */ /* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE), @@ -219,7 +220,7 @@ /* TIMESYNC0 */ PAD_NC(GPP_H19, NONE), /* IMGCLKOUT1 */ PAD_NC(GPP_H20, NONE), /* GPP_H21 */ PAD_NC(GPP_H21, NONE), -/* GPP_H22 */ PAD_NC(GPP_H22, NONE), /* RTD3_CIO_PWR_EN (nostuff) */ +/* GPP_H22 */ PAD_NC(GPP_H22, NONE), /* GPP_H23 */ PAD_NC(GPP_H23, NONE),
/* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* BATLOW# */ @@ -229,11 +230,11 @@ /* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SIO_SLP_S3# */ /* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* SIO_SLP_S4# */ /* SLP_A# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), /* SIO_SLP_A# */ -/* GPD7 */ PAD_NC(GPD7, NONE), /* TBT_RTD3_WAKE# (nostuff) */ +/* GPD7 */ PAD_NC(GPD7, NONE), /* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SUSCLK */ /* SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1), /* SIO_SLP_WLAN# */ /* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), /* SIO_SLP_S5# */ -/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), /* PM_LANPHY_EN */ +/* LANPHYC */ PAD_NC(GPD11, NONE), /* PM_LANPHY_EN */ };
/* Early pad configuration in bootblock */ @@ -241,10 +242,10 @@ /* M2_SKT2_CFG1 */ PAD_CFG_GPO(GPP_H13, 1, DEEP), /* M.2 SSD D3 cold */ /* SSD RESET pin will stay low first */ /* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 0, DEEP), /* D3 cold RST */ -/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */ -/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */ -/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */ -/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */ +/* UART2_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* SERVOTX_UART */ +/* UART2_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* SERVORX_UART */ +/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_PCH_H1 */ +/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_PCH_H1 */ /* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST, EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */ /* RESET# need to stay low before FULL_CARD_POWER_OFF assert */
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35175 )
Change subject: mb/google/drallion: Update gpio config for drallion ......................................................................
Patch Set 1:
(39 comments)
https://review.coreboot.org/c/coreboot/+/35175/1/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/gpio.c:
https://review.coreboot.org/c/coreboot/+/35175/1/src/mainboard/google/dralli... PS1, Line 27: /* SERIRQ */ PAD_NC(GPP_A6, NONE), trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/1/src/mainboard/google/dralli... PS1, Line 27: /* SERIRQ */ PAD_NC(GPP_A6, NONE), please, no space before tabs
https://review.coreboot.org/c/coreboot/+/35175/1/src/mainboard/google/dralli... PS1, Line 28: /* TPM_PIRQ#_A7 */ PAD_CFG_GPI_APIC(GPP_A7, NONE, PLTRST, trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/1/src/mainboard/google/dralli... PS1, Line 40: /* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF2), /* ISH_P_SENSOR_INT# */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/1/src/mainboard/google/dralli... PS1, Line 52: /* CORE_VID0 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/1/src/mainboard/google/dralli... PS1, Line 52: /* CORE_VID0 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), please, no space before tabs
https://review.coreboot.org/c/coreboot/+/35175/1/src/mainboard/google/dralli... PS1, Line 53: /* CORE_VID1 */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), please, no space before tabs
https://review.coreboot.org/c/coreboot/+/35175/1/src/mainboard/google/dralli... PS1, Line 59: /* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/1/src/mainboard/google/dralli... PS1, Line 68: /* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/1/src/mainboard/google/dralli... PS1, Line 69: /* EXT_PWR_GATE# */ PAD_CFG_GPO(GPP_B11, 0, PLTRST), /* 3.3V_CAM_EN# */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/1/src/mainboard/google/dralli... PS1, Line 73: /* GSPI0_CS# */ PAD_CFG_GPO(GPP_B15, 0, PLTRST), /* PRIM_CORE_OPT_DIS */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/1/src/mainboard/google/dralli... PS1, Line 74: /* GSPI0_CLK */ PAD_CFG_GPI(GPP_B16, NONE, PLTRST,), /* ONE_DIMM# */ space required after that ',' (ctx:VxB)
https://review.coreboot.org/c/coreboot/+/35175/1/src/mainboard/google/dralli... PS1, Line 78: /* GSPI1_CLK */ PAD_CFG_GPI(GPP_B20, NONE, PLTRST), trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/1/src/mainboard/google/dralli... PS1, Line 79: /* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 1, PLTRST), /* PCH_3.3V_TS_EN */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/1/src/mainboard/google/dralli... PS1, Line 83: /* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* MEM_SMBCLK */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/1/src/mainboard/google/dralli... PS1, Line 84: /* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* MEM_SMBDATA */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/1/src/mainboard/google/dralli... PS1, Line 89: trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/1/src/mainboard/google/dralli... PS1, Line 89: please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35175/1/src/mainboard/google/dralli... PS1, Line 90: trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/1/src/mainboard/google/dralli... PS1, Line 90: please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35175/1/src/mainboard/google/dralli... PS1, Line 91: /* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* SERVOTX_UART */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/1/src/mainboard/google/dralli... PS1, Line 92: /* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* SERVOTX_UART */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/1/src/mainboard/google/dralli... PS1, Line 99: /* UART1_CTS# */ PAD_CFG_GPO(GPP_C15, 0, PLTRST), trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/1/src/mainboard/google/dralli... PS1, Line 104: /* UART2_RXD */ PAD_NC(GPP_C20, NONE), trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/1/src/mainboard/google/dralli... PS1, Line 105: /* UART2_TXD */ PAD_NC(GPP_C21, NONE), trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/1/src/mainboard/google/dralli... PS1, Line 113: /* SPI1_MISO */ PAD_NC(GPP_D2, NONE), trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/1/src/mainboard/google/dralli... PS1, Line 115: /* FASHTRIG */ PAD_CFG_GPO(GPP_D4, 0, PLTRST), trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/1/src/mainboard/google/dralli... PS1, Line 130: /* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 1, PLTRST), /* RTD3_CIO_PWR_EN */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/1/src/mainboard/google/dralli... PS1, Line 151: /* CPU_GP1 */ PAD_CFG_GPO(GPP_E7, 1, PLTRST), /* TOUCH_SCREEN_PD# */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/1/src/mainboard/google/dralli... PS1, Line 152: /* SATALED# */ PAD_CFG_GPO(GPP_E8, 1, PLTRST), /* SECURE_BIO */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/1/src/mainboard/google/dralli... PS1, Line 160: /* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/1/src/mainboard/google/dralli... PS1, Line 162: /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* CPU_DP1_CTRL_CLK */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/1/src/mainboard/google/dralli... PS1, Line 163: /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* CPU_DP1_CTRL_CLK */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/1/src/mainboard/google/dralli... PS1, Line 164: /* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* CPU_DP2_CTRL_CLK */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/1/src/mainboard/google/dralli... PS1, Line 165: /* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* CPU_DP2_CTRL_CLK */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/1/src/mainboard/google/dralli... PS1, Line 192: /* A4WP_PRESENT */ PAD_CFG_NF(GPP_F23, NONE, PLTRST, NF1), trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/1/src/mainboard/google/dralli... PS1, Line 199: /* SD_CD# */ PAD_CFG_GPO(GPP_G5, 1, PLTRST), /* HOST_SD_WP# */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/1/src/mainboard/google/dralli... PS1, Line 200: /* SD_CLK */ PAD_CFG_GPO(GPP_G6, 1, PLTRST), /* AUD_PWR_EN */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/1/src/mainboard/google/dralli... PS1, Line 223: /* GPP_H22 */ PAD_NC(GPP_H22, NONE), trailing whitespace
Hello Varun Joshi, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35175
to look at the new patch set (#2).
Change subject: mb/google/drallion: Update gpio config for drallion ......................................................................
mb/google/drallion: Update gpio config for drallion
Signed-off-by: Varun Joshi varun.joshi@intel.com Change-Id: I78f85a266eb42ea186ff896db5cde0a347339a71 --- M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/drallion/variants/drallion/gpio.c 2 files changed, 90 insertions(+), 89 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/35175/2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35175 )
Change subject: mb/google/drallion: Update gpio config for drallion ......................................................................
Patch Set 2:
(39 comments)
https://review.coreboot.org/c/coreboot/+/35175/2/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/gpio.c:
https://review.coreboot.org/c/coreboot/+/35175/2/src/mainboard/google/dralli... PS2, Line 27: /* SERIRQ */ PAD_NC(GPP_A6, NONE), trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/2/src/mainboard/google/dralli... PS2, Line 27: /* SERIRQ */ PAD_NC(GPP_A6, NONE), please, no space before tabs
https://review.coreboot.org/c/coreboot/+/35175/2/src/mainboard/google/dralli... PS2, Line 28: /* TPM_PIRQ#_A7 */ PAD_CFG_GPI_APIC(GPP_A7, NONE, PLTRST, trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/2/src/mainboard/google/dralli... PS2, Line 40: /* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF2), /* ISH_P_SENSOR_INT# */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/2/src/mainboard/google/dralli... PS2, Line 52: /* CORE_VID0 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/2/src/mainboard/google/dralli... PS2, Line 52: /* CORE_VID0 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), please, no space before tabs
https://review.coreboot.org/c/coreboot/+/35175/2/src/mainboard/google/dralli... PS2, Line 53: /* CORE_VID1 */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), please, no space before tabs
https://review.coreboot.org/c/coreboot/+/35175/2/src/mainboard/google/dralli... PS2, Line 59: /* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/2/src/mainboard/google/dralli... PS2, Line 68: /* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/2/src/mainboard/google/dralli... PS2, Line 69: /* EXT_PWR_GATE# */ PAD_CFG_GPO(GPP_B11, 0, PLTRST), /* 3.3V_CAM_EN# */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/2/src/mainboard/google/dralli... PS2, Line 73: /* GSPI0_CS# */ PAD_CFG_GPO(GPP_B15, 0, PLTRST), /* PRIM_CORE_OPT_DIS */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/2/src/mainboard/google/dralli... PS2, Line 74: /* GSPI0_CLK */ PAD_CFG_GPI(GPP_B16, NONE, PLTRST,), /* ONE_DIMM# */ space required after that ',' (ctx:VxB)
https://review.coreboot.org/c/coreboot/+/35175/2/src/mainboard/google/dralli... PS2, Line 78: /* GSPI1_CLK */ PAD_CFG_GPI(GPP_B20, NONE, PLTRST), trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/2/src/mainboard/google/dralli... PS2, Line 79: /* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 1, PLTRST), /* PCH_3.3V_TS_EN */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/2/src/mainboard/google/dralli... PS2, Line 83: /* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* MEM_SMBCLK */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/2/src/mainboard/google/dralli... PS2, Line 84: /* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* MEM_SMBDATA */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/2/src/mainboard/google/dralli... PS2, Line 89: trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/2/src/mainboard/google/dralli... PS2, Line 89: please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35175/2/src/mainboard/google/dralli... PS2, Line 90: trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/2/src/mainboard/google/dralli... PS2, Line 90: please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35175/2/src/mainboard/google/dralli... PS2, Line 91: /* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* SERVOTX_UART */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/2/src/mainboard/google/dralli... PS2, Line 92: /* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* SERVOTX_UART */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/2/src/mainboard/google/dralli... PS2, Line 99: /* UART1_CTS# */ PAD_CFG_GPO(GPP_C15, 0, PLTRST), trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/2/src/mainboard/google/dralli... PS2, Line 104: /* UART2_RXD */ PAD_NC(GPP_C20, NONE), trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/2/src/mainboard/google/dralli... PS2, Line 105: /* UART2_TXD */ PAD_NC(GPP_C21, NONE), trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/2/src/mainboard/google/dralli... PS2, Line 113: /* SPI1_MISO */ PAD_NC(GPP_D2, NONE), trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/2/src/mainboard/google/dralli... PS2, Line 115: /* FASHTRIG */ PAD_CFG_GPO(GPP_D4, 0, PLTRST), trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/2/src/mainboard/google/dralli... PS2, Line 130: /* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 1, PLTRST), /* RTD3_CIO_PWR_EN */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/2/src/mainboard/google/dralli... PS2, Line 151: /* CPU_GP1 */ PAD_CFG_GPO(GPP_E7, 1, PLTRST), /* TOUCH_SCREEN_PD# */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/2/src/mainboard/google/dralli... PS2, Line 152: /* SATALED# */ PAD_CFG_GPO(GPP_E8, 1, PLTRST), /* SECURE_BIO */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/2/src/mainboard/google/dralli... PS2, Line 160: /* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/2/src/mainboard/google/dralli... PS2, Line 162: /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* CPU_DP1_CTRL_CLK */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/2/src/mainboard/google/dralli... PS2, Line 163: /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* CPU_DP1_CTRL_CLK */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/2/src/mainboard/google/dralli... PS2, Line 164: /* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* CPU_DP2_CTRL_CLK */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/2/src/mainboard/google/dralli... PS2, Line 165: /* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* CPU_DP2_CTRL_CLK */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/2/src/mainboard/google/dralli... PS2, Line 192: /* A4WP_PRESENT */ PAD_CFG_NF(GPP_F23, NONE, PLTRST, NF1), trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/2/src/mainboard/google/dralli... PS2, Line 199: /* SD_CD# */ PAD_CFG_GPO(GPP_G5, 1, PLTRST), /* HOST_SD_WP# */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/2/src/mainboard/google/dralli... PS2, Line 200: /* SD_CLK */ PAD_CFG_GPO(GPP_G6, 1, PLTRST), /* AUD_PWR_EN */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/2/src/mainboard/google/dralli... PS2, Line 223: /* GPP_H22 */ PAD_NC(GPP_H22, NONE), trailing whitespace
Hello Varun Joshi, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35175
to look at the new patch set (#3).
Change subject: mb/google/drallion: Update gpio config for drallion ......................................................................
mb/google/drallion: Update gpio config for drallion
Signed-off-by: Varun Joshi varun.joshi@intel.com Change-Id: I78f85a266eb42ea186ff896db5cde0a347339a71 --- M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/drallion/variants/drallion/gpio.c 2 files changed, 90 insertions(+), 89 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/35175/3
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35175 )
Change subject: mb/google/drallion: Update gpio config for drallion ......................................................................
Patch Set 3:
(38 comments)
https://review.coreboot.org/c/coreboot/+/35175/3/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/gpio.c:
https://review.coreboot.org/c/coreboot/+/35175/3/src/mainboard/google/dralli... PS3, Line 27: /* SERIRQ */ PAD_NC(GPP_A6, NONE), trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/3/src/mainboard/google/dralli... PS3, Line 27: /* SERIRQ */ PAD_NC(GPP_A6, NONE), please, no space before tabs
https://review.coreboot.org/c/coreboot/+/35175/3/src/mainboard/google/dralli... PS3, Line 28: /* TPM_PIRQ#_A7 */ PAD_CFG_GPI_APIC(GPP_A7, NONE, PLTRST, trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/3/src/mainboard/google/dralli... PS3, Line 40: /* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF2), /* ISH_P_SENSOR_INT# */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/3/src/mainboard/google/dralli... PS3, Line 52: /* CORE_VID0 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/3/src/mainboard/google/dralli... PS3, Line 52: /* CORE_VID0 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), please, no space before tabs
https://review.coreboot.org/c/coreboot/+/35175/3/src/mainboard/google/dralli... PS3, Line 53: /* CORE_VID1 */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), please, no space before tabs
https://review.coreboot.org/c/coreboot/+/35175/3/src/mainboard/google/dralli... PS3, Line 59: /* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/3/src/mainboard/google/dralli... PS3, Line 68: /* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/3/src/mainboard/google/dralli... PS3, Line 69: /* EXT_PWR_GATE# */ PAD_CFG_GPO(GPP_B11, 0, PLTRST), /* 3.3V_CAM_EN# */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/3/src/mainboard/google/dralli... PS3, Line 73: /* GSPI0_CS# */ PAD_CFG_GPO(GPP_B15, 0, PLTRST), /* PRIM_CORE_OPT_DIS */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/3/src/mainboard/google/dralli... PS3, Line 78: /* GSPI1_CLK */ PAD_CFG_GPI(GPP_B20, NONE, PLTRST), trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/3/src/mainboard/google/dralli... PS3, Line 79: /* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 1, PLTRST), /* PCH_3.3V_TS_EN */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/3/src/mainboard/google/dralli... PS3, Line 83: /* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* MEM_SMBCLK */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/3/src/mainboard/google/dralli... PS3, Line 84: /* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* MEM_SMBDATA */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/3/src/mainboard/google/dralli... PS3, Line 89: trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/3/src/mainboard/google/dralli... PS3, Line 89: please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35175/3/src/mainboard/google/dralli... PS3, Line 90: trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/3/src/mainboard/google/dralli... PS3, Line 90: please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35175/3/src/mainboard/google/dralli... PS3, Line 91: /* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* SERVOTX_UART */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/3/src/mainboard/google/dralli... PS3, Line 92: /* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* SERVOTX_UART */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/3/src/mainboard/google/dralli... PS3, Line 99: /* UART1_CTS# */ PAD_CFG_GPO(GPP_C15, 0, PLTRST), trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/3/src/mainboard/google/dralli... PS3, Line 104: /* UART2_RXD */ PAD_NC(GPP_C20, NONE), trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/3/src/mainboard/google/dralli... PS3, Line 105: /* UART2_TXD */ PAD_NC(GPP_C21, NONE), trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/3/src/mainboard/google/dralli... PS3, Line 113: /* SPI1_MISO */ PAD_NC(GPP_D2, NONE), trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/3/src/mainboard/google/dralli... PS3, Line 115: /* FASHTRIG */ PAD_CFG_GPO(GPP_D4, 0, PLTRST), trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/3/src/mainboard/google/dralli... PS3, Line 130: /* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 1, PLTRST), /* RTD3_CIO_PWR_EN */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/3/src/mainboard/google/dralli... PS3, Line 151: /* CPU_GP1 */ PAD_CFG_GPO(GPP_E7, 1, PLTRST), /* TOUCH_SCREEN_PD# */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/3/src/mainboard/google/dralli... PS3, Line 152: /* SATALED# */ PAD_CFG_GPO(GPP_E8, 1, PLTRST), /* SECURE_BIO */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/3/src/mainboard/google/dralli... PS3, Line 160: /* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/3/src/mainboard/google/dralli... PS3, Line 162: /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* CPU_DP1_CTRL_CLK */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/3/src/mainboard/google/dralli... PS3, Line 163: /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* CPU_DP1_CTRL_CLK */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/3/src/mainboard/google/dralli... PS3, Line 164: /* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* CPU_DP2_CTRL_CLK */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/3/src/mainboard/google/dralli... PS3, Line 165: /* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* CPU_DP2_CTRL_CLK */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/3/src/mainboard/google/dralli... PS3, Line 192: /* A4WP_PRESENT */ PAD_CFG_NF(GPP_F23, NONE, PLTRST, NF1), trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/3/src/mainboard/google/dralli... PS3, Line 199: /* SD_CD# */ PAD_CFG_GPO(GPP_G5, 1, PLTRST), /* HOST_SD_WP# */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/3/src/mainboard/google/dralli... PS3, Line 200: /* SD_CLK */ PAD_CFG_GPO(GPP_G6, 1, PLTRST), /* AUD_PWR_EN */ trailing whitespace
https://review.coreboot.org/c/coreboot/+/35175/3/src/mainboard/google/dralli... PS3, Line 223: /* GPP_H22 */ PAD_NC(GPP_H22, NONE), trailing whitespace
Varun Joshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35175 )
Change subject: mb/google/drallion: Update gpio config for drallion ......................................................................
Patch Set 4:
This change is ready for review.
Varun Joshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35175 )
Change subject: mb/google/drallion: Update gpio config for drallion ......................................................................
Patch Set 4:
GPIO changes for drallion
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35175 )
Change subject: mb/google/drallion: Update gpio config for drallion ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35175/4/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/35175/4/src/mainboard/google/dralli... PS4, Line 358: device pci 19.2 off end # UART #2 I think we should align this.
https://review.coreboot.org/c/coreboot/+/35175/4/src/mainboard/google/dralli... PS4, Line 377: device pci 1e.0 on end # UART #0 same above.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35175 )
Change subject: mb/google/drallion: Update gpio config for drallion ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35175/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35175/4//COMMIT_MSG@8 PS4, Line 8: Please add B:139370304 here.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35175 )
Change subject: mb/google/drallion: Update gpio config for drallion ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35175/4/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/gpio.c:
https://review.coreboot.org/c/coreboot/+/35175/4/src/mainboard/google/dralli... PS4, Line 90: /* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* SERVOTX_UART */ We did this in early table, should we init again?
Hello Varun Joshi, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35175
to look at the new patch set (#5).
Change subject: mb/google/drallion: Update gpio config for drallion ......................................................................
mb/google/drallion: Update gpio config for drallion
Signed-off-by: Varun Joshi varun.joshi@intel.com Change-Id: I78f85a266eb42ea186ff896db5cde0a347339a71 --- M src/mainboard/google/drallion/variants/drallion/gpio.c 1 file changed, 75 insertions(+), 78 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/35175/5
Hello Varun Joshi, Bora Guvendik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35175
to look at the new patch set (#6).
Change subject: mb/google/drallion: Update gpio config for drallion ......................................................................
mb/google/drallion: Update gpio config for drallion
Signed-off-by: Varun Joshi varun.joshi@intel.com Change-Id: I78f85a266eb42ea186ff896db5cde0a347339a71 BUG=b:139370304 --- M src/mainboard/google/drallion/variants/drallion/gpio.c 1 file changed, 76 insertions(+), 79 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/35175/6
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35175 )
Change subject: mb/google/drallion: Update gpio config for drallion ......................................................................
Patch Set 6:
(5 comments)
https://review.coreboot.org/c/coreboot/+/35175/6/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/gpio.c:
https://review.coreboot.org/c/coreboot/+/35175/6/src/mainboard/google/dralli... PS6, Line 36: /* SUSWARN# */ PAD_NC(GPP_A13, NONE), We may this for SD card reader D3 cold. Could you chech with Tim?
https://review.coreboot.org/c/coreboot/+/35175/6/src/mainboard/google/dralli... PS6, Line 38: /* SUSACK# */ PAD_NC(GPP_A15, NONE), We may this for SD card reader D3 cold. Could you chech with Tim?
https://review.coreboot.org/c/coreboot/+/35175/6/src/mainboard/google/dralli... PS6, Line 91: /* UART0_RTS# */ PAD_CFG_GPI(GPP_C10, NONE, PLTRST), This should be GPO, WWAN_FULL_PWR_EN default high.
https://review.coreboot.org/c/coreboot/+/35175/6/src/mainboard/google/dralli... PS6, Line 103: /* UART2_RTS# */ PAD_CFG_GPI(GPP_C22, NONE, PLTRST), /* SPK detect */
https://review.coreboot.org/c/coreboot/+/35175/6/src/mainboard/google/dralli... PS6, Line 157: /* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), HDMI_PD#, GPO default high
Hello Varun Joshi, Bora Guvendik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35175
to look at the new patch set (#7).
Change subject: mb/google/drallion: Update gpio config for drallion ......................................................................
mb/google/drallion: Update gpio config for drallion
Signed-off-by: Varun Joshi varun.joshi@intel.com Change-Id: I78f85a266eb42ea186ff896db5cde0a347339a71 BUG=b:139370304 --- M src/mainboard/google/drallion/variants/drallion/gpio.c 1 file changed, 78 insertions(+), 82 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/35175/7
Hello Varun Joshi, Bora Guvendik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35175
to look at the new patch set (#8).
Change subject: mb/google/drallion: Update gpio config for drallion ......................................................................
mb/google/drallion: Update gpio config for drallion
Signed-off-by: Varun Joshi varun.joshi@intel.com Change-Id: I78f85a266eb42ea186ff896db5cde0a347339a71 BUG=b:139370304 --- M src/mainboard/google/drallion/variants/drallion/gpio.c 1 file changed, 78 insertions(+), 82 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/35175/8
Hello Varun Joshi, Bora Guvendik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35175
to look at the new patch set (#9).
Change subject: mb/google/drallion: Update gpio config for drallion ......................................................................
mb/google/drallion: Update gpio config for drallion
Signed-off-by: Varun Joshi varun.joshi@intel.com Change-Id: I78f85a266eb42ea186ff896db5cde0a347339a71 BUG=b:139370304 --- M src/mainboard/google/drallion/variants/drallion/gpio.c 1 file changed, 78 insertions(+), 82 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/35175/9
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35175 )
Change subject: mb/google/drallion: Update gpio config for drallion ......................................................................
Patch Set 9:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35175/9/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/gpio.c:
https://review.coreboot.org/c/coreboot/+/35175/9/src/mainboard/google/dralli... PS9, Line 166: /* GPP_F1 */ PAD_CFG_GPI(GPP_F1, NONE, DEEP), /* DDR_CHA_EN_1P8 */ We should put this into early_gpio_table. F1/F2 based on Duncan's comment.https://review.coreboot.org/c/coreboot/+/35241
https://review.coreboot.org/c/coreboot/+/35175/9/src/mainboard/google/dralli... PS9, Line 177: /* EMMC_DATA0 */ PAD_CFG_GPI(GPP_F12, NONE, DEEP), /* MEM_CONFIGO_1P8 */ We should put this into early_gpio_table. See here:https://review.coreboot.org/c/coreboot/+/35141/7/src/mainboard/google/dralli...
Hello Varun Joshi, Bora Guvendik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35175
to look at the new patch set (#10).
Change subject: mb/google/drallion: Update gpio config for drallion ......................................................................
mb/google/drallion: Update gpio config for drallion
Signed-off-by: Varun Joshi varun.joshi@intel.com Change-Id: I78f85a266eb42ea186ff896db5cde0a347339a71 BUG=b:139370304 --- M src/mainboard/google/drallion/variants/drallion/gpio.c 1 file changed, 78 insertions(+), 82 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/35175/10
Hello Varun Joshi, Bora Guvendik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35175
to look at the new patch set (#11).
Change subject: mb/google/drallion: Update gpio config for drallion ......................................................................
mb/google/drallion: Update gpio config for drallion
Signed-off-by: Varun Joshi varun.joshi@intel.com Change-Id: I78f85a266eb42ea186ff896db5cde0a347339a71 BUG=b:139370304 --- M src/mainboard/google/drallion/variants/drallion/gpio.c 1 file changed, 78 insertions(+), 82 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/35175/11
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35175 )
Change subject: mb/google/drallion: Update gpio config for drallion ......................................................................
Patch Set 11:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35175/6/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/gpio.c:
https://review.coreboot.org/c/coreboot/+/35175/6/src/mainboard/google/dralli... PS6, Line 36: /* SUSWARN# */ PAD_NC(GPP_A13, NONE),
We may this for SD card reader D3 cold. […]
This is no longer needed.
https://review.coreboot.org/c/coreboot/+/35175/6/src/mainboard/google/dralli... PS6, Line 38: /* SUSACK# */ PAD_NC(GPP_A15, NONE),
We may this for SD card reader D3 cold. […]
This is no longer needed.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35175 )
Change subject: mb/google/drallion: Update gpio config for drallion ......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35175/11/src/mainboard/google/drall... File src/mainboard/google/drallion/variants/drallion/gpio.c:
https://review.coreboot.org/c/coreboot/+/35175/11/src/mainboard/google/drall... PS11, Line 156: /* DDPE_HPD3 */ PAD_CFG_GPO(GPP_E16, 0, PLTRST), /* HDMI_PD# */ HW suggest default high.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35175 )
Change subject: mb/google/drallion: Update gpio config for drallion ......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35175/11//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35175/11//COMMIT_MSG@8 PS11, Line 8: From what source (datasheet, …)?
Hello Varun Joshi, Bora Guvendik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35175
to look at the new patch set (#12).
Change subject: mb/google/drallion: Update gpio config for drallion Source: Pin Schematics Signed-off-by: Varun Joshi varun.joshi@intel.com Change-Id: I78f85a266eb42ea186ff896db5cde0a347339a71 BUG=b:139370304 ......................................................................
mb/google/drallion: Update gpio config for drallion Source: Pin Schematics Signed-off-by: Varun Joshi varun.joshi@intel.com Change-Id: I78f85a266eb42ea186ff896db5cde0a347339a71 BUG=b:139370304 --- M src/mainboard/google/drallion/variants/drallion/gpio.c 1 file changed, 78 insertions(+), 82 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/35175/12
Hello Varun Joshi, Bora Guvendik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35175
to look at the new patch set (#13).
Change subject: mb/google/drallion: Update gpio config for drallion ......................................................................
mb/google/drallion: Update gpio config for drallion
Signed-off-by: Varun Joshi varun.joshi@intel.com Change-Id: I78f85a266eb42ea186ff896db5cde0a347339a71 BUG=b:139370304 Source: Pin Schematics --- M src/mainboard/google/drallion/variants/drallion/gpio.c 1 file changed, 78 insertions(+), 82 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/35175/13
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35175 )
Change subject: mb/google/drallion: Update gpio config for drallion ......................................................................
Patch Set 13:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35175/13/src/mainboard/google/drall... File src/mainboard/google/drallion/variants/drallion/gpio.c:
https://review.coreboot.org/c/coreboot/+/35175/13/src/mainboard/google/drall... PS13, Line 196: /* I2C2_SCL */ PAD_CFG_GPI(GPP_H5, NONE, PLTRST), /* 360_SENSOR_DET# */ We may should put this in early table as well.
Mathew King has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35175 )
Change subject: mb/google/drallion: Update gpio config for drallion ......................................................................
Patch Set 13:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35175/13//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35175/13//COMMIT_MSG@11 PS13, Line 11: BUG=b:139370304 BUG should go before the signed-of-by
https://review.coreboot.org/c/coreboot/+/35175/13//COMMIT_MSG@12 PS13, Line 12: Source: Pin Schematics This should be after the first line
Hello Varun Joshi, Bora Guvendik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35175
to look at the new patch set (#14).
Change subject: mb/google/drallion: Update gpio config for drallion Source: Pin Schematics BUG=b:139370304 Signed-off-by: Varun Joshi varun.joshi@intel.com Change-Id: I78f85a266eb42ea186ff896db5cde0a347339a71 ......................................................................
mb/google/drallion: Update gpio config for drallion Source: Pin Schematics BUG=b:139370304 Signed-off-by: Varun Joshi varun.joshi@intel.com Change-Id: I78f85a266eb42ea186ff896db5cde0a347339a71 --- M src/mainboard/google/drallion/variants/drallion/gpio.c 1 file changed, 78 insertions(+), 82 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/35175/14
Selma Bensaid has uploaded a new patch set (#15) to the change originally created by Varun Joshi. ( https://review.coreboot.org/c/coreboot/+/35175 )
Change subject: mb/google/drallion: Update gpio config for drallion ......................................................................
mb/google/drallion: Update gpio config for drallion
Source: Pin Schematics
BUG=b:139370304 Signed-off-by: Varun Joshi varun.joshi@intel.com Change-Id: I78f85a266eb42ea186ff896db5cde0a347339a71 --- M src/mainboard/google/drallion/variants/drallion/gpio.c 1 file changed, 78 insertions(+), 82 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/35175/15
Varun Joshi has uploaded a new patch set (#16) to the change originally created by Varun Joshi. ( https://review.coreboot.org/c/coreboot/+/35175 )
Change subject: mb/google/drallion: Update gpio config for drallion ......................................................................
mb/google/drallion: Update gpio config for drallion
Source: Pin Schematics
BUG=b:139370304 Signed-off-by: Varun Joshi varun.joshi@intel.com Change-Id: I78f85a266eb42ea186ff896db5cde0a347339a71 --- M src/mainboard/google/drallion/variants/drallion/gpio.c 1 file changed, 78 insertions(+), 82 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/35175/16
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35175 )
Change subject: mb/google/drallion: Update gpio config for drallion ......................................................................
Patch Set 16: Code-Review+1
I have no concern about the gpio now. Others we can modify in the factory PO if needed.
Mathew King has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35175 )
Change subject: mb/google/drallion: Update gpio config for drallion ......................................................................
Patch Set 17: Code-Review+2
Mathew King has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35175 )
Change subject: mb/google/drallion: Update gpio config for drallion ......................................................................
Patch Set 17:
(14 comments)
In the future please resolve comments as they are fixed. There is one left that was not done can you address it?
https://review.coreboot.org/c/coreboot/+/35175/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35175/4//COMMIT_MSG@8 PS4, Line 8:
Please add B:139370304 here.
Done
https://review.coreboot.org/c/coreboot/+/35175/11//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35175/11//COMMIT_MSG@8 PS11, Line 8:
From what source (datasheet, …)?
Done
https://review.coreboot.org/c/coreboot/+/35175/13//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35175/13//COMMIT_MSG@11 PS13, Line 11: BUG=b:139370304
BUG should go before the signed-of-by
Done
https://review.coreboot.org/c/coreboot/+/35175/13//COMMIT_MSG@12 PS13, Line 12: Source: Pin Schematics
This should be after the first line
Done
https://review.coreboot.org/c/coreboot/+/35175/4/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/35175/4/src/mainboard/google/dralli... PS4, Line 358: device pci 19.2 off end # UART #2
I think we should align this.
Done
https://review.coreboot.org/c/coreboot/+/35175/4/src/mainboard/google/dralli... PS4, Line 377: device pci 1e.0 on end # UART #0
same above.
Done
https://review.coreboot.org/c/coreboot/+/35175/4/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/gpio.c:
https://review.coreboot.org/c/coreboot/+/35175/4/src/mainboard/google/dralli... PS4, Line 90: /* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* SERVOTX_UART */
We did this in early table, should we init again?
Please fix or resolve with a comment
https://review.coreboot.org/c/coreboot/+/35175/6/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/gpio.c:
https://review.coreboot.org/c/coreboot/+/35175/6/src/mainboard/google/dralli... PS6, Line 91: /* UART0_RTS# */ PAD_CFG_GPI(GPP_C10, NONE, PLTRST),
This should be GPO, WWAN_FULL_PWR_EN default high.
Done
https://review.coreboot.org/c/coreboot/+/35175/6/src/mainboard/google/dralli... PS6, Line 103: /* UART2_RTS# */ PAD_CFG_GPI(GPP_C22, NONE, PLTRST),
/* SPK detect */
Done
https://review.coreboot.org/c/coreboot/+/35175/6/src/mainboard/google/dralli... PS6, Line 157: /* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE),
HDMI_PD#, GPO default high
Done
https://review.coreboot.org/c/coreboot/+/35175/9/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/gpio.c:
https://review.coreboot.org/c/coreboot/+/35175/9/src/mainboard/google/dralli... PS9, Line 166: /* GPP_F1 */ PAD_CFG_GPI(GPP_F1, NONE, DEEP), /* DDR_CHA_EN_1P8 */
We should put this into early_gpio_table. F1/F2 based on Duncan's comment.https://review.coreboot. […]
Done
https://review.coreboot.org/c/coreboot/+/35175/9/src/mainboard/google/dralli... PS9, Line 177: /* EMMC_DATA0 */ PAD_CFG_GPI(GPP_F12, NONE, DEEP), /* MEM_CONFIGO_1P8 */
We should put this into early_gpio_table. See here:https://review.coreboot. […]
Done
https://review.coreboot.org/c/coreboot/+/35175/11/src/mainboard/google/drall... File src/mainboard/google/drallion/variants/drallion/gpio.c:
https://review.coreboot.org/c/coreboot/+/35175/11/src/mainboard/google/drall... PS11, Line 156: /* DDPE_HPD3 */ PAD_CFG_GPO(GPP_E16, 0, PLTRST), /* HDMI_PD# */
HW suggest default high.
Done
https://review.coreboot.org/c/coreboot/+/35175/13/src/mainboard/google/drall... File src/mainboard/google/drallion/variants/drallion/gpio.c:
https://review.coreboot.org/c/coreboot/+/35175/13/src/mainboard/google/drall... PS13, Line 196: /* I2C2_SCL */ PAD_CFG_GPI(GPP_H5, NONE, PLTRST), /* 360_SENSOR_DET# */
We may should put this in early table as well.
Done
Varun Joshi has uploaded a new patch set (#18) to the change originally created by Varun Joshi. ( https://review.coreboot.org/c/coreboot/+/35175 )
Change subject: mb/google/drallion: Update gpio config for drallion ......................................................................
mb/google/drallion: Update gpio config for drallion
Source: Pin Schematics
BUG=b:139370304 Signed-off-by: Varun Joshi varun.joshi@intel.com Change-Id: I78f85a266eb42ea186ff896db5cde0a347339a71 --- M src/mainboard/google/drallion/variants/drallion/gpio.c 1 file changed, 76 insertions(+), 82 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/35175/18
Varun Joshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35175 )
Change subject: mb/google/drallion: Update gpio config for drallion ......................................................................
Patch Set 18:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35175/4/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/gpio.c:
https://review.coreboot.org/c/coreboot/+/35175/4/src/mainboard/google/dralli... PS4, Line 90: /* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* SERVOTX_UART */
Please fix or resolve with a comment
Done
Varun Joshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35175 )
Change subject: mb/google/drallion: Update gpio config for drallion ......................................................................
Patch Set 18:
Patch Set 17:
(14 comments)
In the future please resolve comments as they are fixed. There is one left that was not done can you address it?
Will take care of this. Other comment is resolved now.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35175 )
Change subject: mb/google/drallion: Update gpio config for drallion ......................................................................
Patch Set 19: Code-Review+1
Mathew King has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35175 )
Change subject: mb/google/drallion: Update gpio config for drallion ......................................................................
Patch Set 19: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35175 )
Change subject: mb/google/drallion: Update gpio config for drallion ......................................................................
mb/google/drallion: Update gpio config for drallion
Source: Pin Schematics
BUG=b:139370304 Signed-off-by: Varun Joshi varun.joshi@intel.com Change-Id: I78f85a266eb42ea186ff896db5cde0a347339a71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35175 Reviewed-by: EricR Lai ericr_lai@compal.corp-partner.google.com Reviewed-by: Mathew King mathewk@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/drallion/variants/drallion/gpio.c 1 file changed, 76 insertions(+), 82 deletions(-)
Approvals: build bot (Jenkins): Verified EricR Lai: Looks good to me, but someone else must approve Mathew King: Looks good to me, approved
diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c index ebe5ee2..064f96c 100644 --- a/src/mainboard/google/drallion/variants/drallion/gpio.c +++ b/src/mainboard/google/drallion/variants/drallion/gpio.c @@ -24,33 +24,33 @@ /* ESPI_IO2 */ /* ESPI_IO3 */ /* ESPI_CS# */ -/* SERIRQ */ -/* PIRQA# */ PAD_NC(GPP_A7, NONE), +/* SERIRQ */ PAD_NC(GPP_A6, NONE), +/* TPM_PIRQ#_A7 */ PAD_NC(GPP_A7, NONE), /* CLKRUN# */ PAD_NC(GPP_A8, NONE), /* ESPI_CLK */ /* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), /* PME# */ PAD_NC(GPP_A11, NONE), /* ISH_LID_CL#_TAB */ /* ISH_GP6 */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF2), -/* SUSWARN# */ PAD_NC(GPP_A13, NONE), +/* SUSWARN# */ PAD_CFG_GPO(GPP_A13, 0, DEEP), /* ESPI_RESET# */ -/* SUSACK# */ PAD_NC(GPP_A15, NONE), -/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), -/* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE), +/* SUSACK# */ PAD_CFG_GPO(GPP_A15, 0, DEEP), +/* SD_1P8_SEL */ PAD_CFG_GPI(GPP_A16, NONE, PLTRST), /* 2.7MM_CAM_DET# */ +/* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF2), /* ISH_ACC1_INT# */ /* ISH_GP0 */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* ISH_ACC2_INT# */ /* ISH_GP1 */ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), -/* ISH_GP2 */ PAD_NC(GPP_A20, NONE), -/* ISH_GP3 */ PAD_NC(GPP_A21, NONE), +/* ISH_GP2 */ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), +/* ISH_GP3 */ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), /* ISH_NB_MODE */ /* ISH_GP4 */ PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1), /* ISH_LID_CL#_NB */ /* ISH_GP5 */ PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1),
-/* CORE_VID0 */ -/* CORE_VID1 */ -/* VRALERT# */ PAD_NC(GPP_B2, NONE), +/* CORE_VID0 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), +/* CORE_VID1 */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), +/* VRALERT# */ PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), /* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, EDGE_SINGLE, INVERT), /* TOUCHPAD_INTR# */ /* CPU_GP3 */ PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* TOUCH_SCREEN_DET# */ @@ -64,37 +64,32 @@ /* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* SSD_CKLREQ_CPU_N */ /* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), -/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), /* TBT_CLKREQ_CPU_N (nostuff) */ -/* EXT_PWR_GATE# */ PAD_CFG_GPO(GPP_B11, 0, DEEP), /* 3.3V_CAM_EN# */ +/* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), +/* EXT_PWR_GATE# */ PAD_CFG_GPO(GPP_B11, 0, PLTRST), /* 3.3V_CAM_EN# */ /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), -/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE), /* PRIM_CORE_OPT_DIS (nostuff) */ -/* GSPI0_CLK */ PAD_CFG_GPI(GPP_B16, NONE, DEEP), /* ONE_DIMM# */ +/* GSPI0_CS# */ PAD_CFG_GPO(GPP_B15, 0, PLTRST), /* PRIM_CORE_OPT_DIS */ +/* GSPI0_CLK */ PAD_CFG_GPI(GPP_B16, NONE, PLTRST), /* ONE_DIMM# */ /* GSPI0_MISO */ PAD_NC(GPP_B17, NONE), /* RTC_DET# */ /* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), /* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* HDD_FALL_INT (nostuff) */ -/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), /* TPM_PIRQ# (nostuff) */ -/* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */ +/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), +/* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 1, PLTRST), /* PCH_3.3V_TS_EN */ /* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), /* SML1ALERT# */ PAD_NC(GPP_B23, DN_20K),
/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* MEM_SMBCLK */ /* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* MEM_SMBDATA */ /* SMBALERT# */ PAD_NC(GPP_C2, DN_20K), -/* SML0CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0_SMBCLK */ -/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0_SMBDATA */ -/* SML0ALERT# */ PAD_NC(GPP_C5, DN_20K), -/* SM1CLK */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* SML1_SMBCLK */ -/* SM1DATA */ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* SML1_SMBDATA */ -/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* SERVOTX_UART */ -/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* SERVORX_UART */ -/* UART0_RTS# */ PAD_CFG_GPI(GPP_C10, NONE, DEEP), /* TYPEC_CON_SEL1 */ -/* UART0_CTS# */ PAD_CFG_GPI(GPP_C11, NONE, DEEP), /* TYPEC_CON_SEL2 */ -/* UART1_RXD */ PAD_CFG_GPI_SCI_LOW(GPP_C12, NONE, DEEP, - EDGE_SINGLE), /* SIO_EXT_WAKE# */ +/* SML0CLK */ PAD_NC(GPP_C3, NONE), +/* SML0DATA */ PAD_NC(GPP_C4, NONE), +/* SML0ALERT# */ PAD_CFG_GPI(GPP_C5, NONE, DEEP), +/* UART0_RTS# */ PAD_CFG_GPO(GPP_C10, 1, PLTRST), /* WWAN_FULL_PWR_EN */ +/* UART0_CTS# */ PAD_NC(GPP_C11, NONE), +/* UART1_RXD */ PAD_NC(GPP_C12, NONE), /* UART1_TXD */ PAD_NC(GPP_C13, NONE), -/* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* LCD_CBL_DET# */ +/* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, PLTRST), /* LCD_CBL_DET# */ /* UART1_CTS# */ PAD_NC(GPP_C15, NONE), /* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TS_I2C_SDA */ /* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TS_I2C_SCL */ @@ -102,72 +97,70 @@ /* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* I2C1_SCK_TP */ /* UART2_RXD */ PAD_NC(GPP_C20, NONE), /* UART2_TXD */ PAD_NC(GPP_C21, NONE), -/* UART2_RTS# */ PAD_NC(GPP_C22, NONE), +/* UART2_RTS# */ PAD_CFG_GPI(GPP_C22, NONE, PLTRST), /* SPK_DETECT */ /* UART2_CTS# */ PAD_CFG_GPI_APIC(GPP_C23, NONE, PLTRST, LEVEL, NONE), /* TS_INT# */
/* SPI1_CS# */ PAD_CFG_GPI_APIC(GPP_D0, NONE, PLTRST, EDGE_SINGLE, INVERT), /* MEDIACARD_IRQ# */ -/* SPI1_CLK */ PAD_NC(GPP_D1, NONE), -/* SPI1_MISO */ PAD_CFG_GPI(GPP_D2, NONE, DEEP), /* ISH_LAN# */ -/* SPI1_MOSI */ PAD_NC(GPP_D3, NONE), -/* FASHTRIG */ PAD_NC(GPP_D4, NONE), /* TBT_FORCE_PWR (nostuff) */ +/* SPI1_CLK */ PAD_CFG_GPI(GPP_D1, NONE, DEEP), /* VPRO_DET# */ +/* SPI1_MISO */ PAD_NC(GPP_D2, NONE), +/* SPI1_MOSI */ PAD_CFG_GPI(GPP_D3, NONE, PLTRST), /* RTC_DET# */ +/* FASHTRIG */ PAD_NC(GPP_D4, NONE), /* ISH_I2C0_ACC_SDA */ /* ISH_I2C0_SDA */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* ISH_I2C0_ACC_SCL */ /* ISH_I2C0_SCL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), -/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), -/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), -/* ISH_SPI_CS# */ PAD_CFG_GPI(GPP_D9, NONE, DEEP), /* IR_CAM_DET# */ +/* ISH_I2C1_SDA */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), +/* ISH_I2C1_SCL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), +/* ISH_SPI_CS# */ PAD_CFG_GPI(GPP_D9, NONE, PLTRST), /* IR_CAM_DET# */ /* ISH_SPI_CLK */ PAD_NC(GPP_D10, NONE), -/* ISH_SPI_MISO */ PAD_CFG_GPI(GPP_D11, NONE, DEEP), /* TBT_DET# */ +/* ISH_SPI_MISO */ PAD_NC(GPP_D11, NONE), /* ISH_SPI_MOSI */ PAD_NC(GPP_D12, NONE), /* ISH_CPU_UART0_RX */ /* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, UP_20K, DEEP, NF1), /* ISH_CPU_UART0_TX */ /* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), -/* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 1, DEEP), /* WWAN_FULL_PWR_EN */ -/* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE), -/* DMIC_CLK1 */ PAD_CFG_GPI(GPP_D17, NONE, DEEP), /* KB_DET# */ +/* ISH_UART0_RTS# */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_CTS# */ PAD_CFG_GPI(GPP_D16, NONE, PLTRST), +/* DMIC_CLK1 */ PAD_CFG_GPI(GPP_D17, NONE, PLTRST), /* KB_DET# */ /* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST, EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */ /* DMIC_CLK0 */ PAD_NC(GPP_D19, NONE), /* DMIC_DATA0 */ PAD_NC(GPP_D20, NONE), -/* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 1, DEEP), /* WWAN_BB_RST# */ +/* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 0, DEEP), /* WWAN_BB_RST# */ /* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 0, DEEP), /* WWAN_GPIO_PERST# */ /* I2S_MCLK */ PAD_CFG_GPI_SCI_LOW(GPP_D23, NONE, DEEP, EDGE_SINGLE), /* WWAN_GPIO_WAKE# */
-/* SATAXPCIE0 */ PAD_NC(GPP_E0, NONE), +/* SATAXPCIE0 */ PAD_CFG_NF(GPP_E0, NONE, DEEP, NF2), /* HDD_DET# */ /* M3042_PCIE#_SATA */ -/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), +/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF2), /* M2880_PCIE_SATA# */ -/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), -/* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */ +/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF2), +/* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, PLTRST), /* MEM_INTERLEAVED */ /* SATA_DEVSLP0 */ PAD_NC(GPP_E4, NONE), /* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* M3042_DEVSLP */ /* SATA_DEVSLP2 */ PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), /* M2280_DEVSLP */ -/* CPU_GP1 */ PAD_CFG_GPO(GPP_E7, 1, DEEP), /* TOUCH_SCREEN_PD# */ -/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */ +/* CPU_GP1 */ PAD_CFG_GPO(GPP_E7, 0, PLTRST), /* TOUCH_SCREEN_PD# */ +/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_OC0# */ /* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB_OC1# */ -/* USB2_OC2# */ PAD_NC(GPP_E11, NONE), -/* USB2_OC3# */ PAD_NC(GPP_E12, NONE), +/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), +/* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DP_HPD_CPU */ /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DP2_HPD_CPU */ -/* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* PCH_WP */ -/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), /* FFS_INT2 (nostuff) */ +/* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */ +/* DDPE_HPD3 */ PAD_CFG_GPO(GPP_E16, 1, PLTRST), /* HDMI_PD# */ /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), -/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* HDMI_SCL_CPU */ -/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* HDMI_SDA_CPU */ -/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), -/* DDPC_CTRLDATA */ PAD_NC(GPP_E21, NONE), +/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), +/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), +/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), /* DDPD_CTRLDATA */ PAD_NC(GPP_E23, NONE),
/* CNV_PA_BLANKING */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* CNV_COEX3 */ -/* GPP_F1 */ PAD_NC(GPP_F1, NONE), -/* GPP_F2 */ PAD_NC(GPP_F2, NONE), /* GPP_F3 */ PAD_NC(GPP_F3, NONE), /* CNV_BRI_DT */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* CNV_BRI_RSP */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), @@ -177,38 +170,31 @@ /* CNV_MFUART2_TXD */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* CNV_COEX1 */ /* GPP_F10 */ PAD_NC(GPP_F10, NONE), /* EMMC_CMD */ PAD_NC(GPP_F11, NONE), -/* EMMC_DATA0 */ PAD_NC(GPP_F12, NONE), -/* EMMC_DATA1 */ PAD_NC(GPP_F13, NONE), -/* EMMC_DATA2 */ PAD_NC(GPP_F14, NONE), -/* EMMC_DATA3 */ PAD_NC(GPP_F15, NONE), -/* EMMC_DATA4 */ PAD_NC(GPP_F16, NONE), /* EMMC_DATA5 */ PAD_NC(GPP_F17, NONE), /* EMMC_DATA6 */ PAD_NC(GPP_F18, NONE), /* EMMC_DATA7 */ PAD_NC(GPP_F19, NONE), /* EMMC_RCLK */ PAD_NC(GPP_F20, NONE), /* EMMC_CLK */ PAD_NC(GPP_F21, NONE), /* EMMC_RESET# */ PAD_NC(GPP_F22, NONE), -/* A4WP_PRESENT */ PAD_NC(GPP_F23, NONE), - -/* SD_CMD */ PAD_CFG_GPI(GPP_G0, NONE, DEEP), /* CAM_MIC_CBL_DET# */ +/* A4WP_PRESENT */ PAD_CFG_NF(GPP_F23, NONE, PLTRST, NF1), +/* SD_CMD */ PAD_CFG_GPI(GPP_G0, NONE, PLTRST), /* CAM_MIC */ /* SD_DATA0 */ PAD_NC(GPP_G1, NONE), /* ANT_CONFIG (nostuff) */ -/* SD_DATA1 */ PAD_NC(GPP_G2, NONE), /* TBT_CIO_PLUG_EVT# (nostuff) */ +/* SD_DATA1 */ PAD_NC(GPP_G2, NONE), /* SD_DATA2 */ PAD_NC(GPP_G3, NONE), -/* SD_DATA3 */ PAD_CFG_GPI(GPP_G4, NONE, DEEP), /* CTLESS_DET# */ -/* SD_CD# */ PAD_CFG_GPO(GPP_G5, 1, DEEP), /* HOST_SD_WP# */ -/* SD_CLK */ PAD_CFG_GPO(GPP_G6, 1, DEEP), /* AUD_PWR_EN */ -/* SD_WP */ PAD_CFG_GPI(GPP_G7, NONE, DEEP), /* SPK_DET# */ +/* SD_DATA3 */ PAD_CFG_GPI(GPP_G4, NONE, PLTRST), /* CTLESS_DET# */ +/* SD_CD# */ PAD_CFG_GPO(GPP_G5, 1, PLTRST), /* HOST_SD_WP# */ +/* SD_CLK */ PAD_CFG_GPO(GPP_G6, 1, PLTRST), /* AUD_PWR_EN */ +/* SD_WP */ PAD_CFG_GPI(GPP_G7, NONE, PLTRST), /* SPK_DET# */
/* I2S2_SCLK */ PAD_NC(GPP_H0, NONE), /* I2S2_SFRM */ PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), /* CNV_RF_RESET# */ /* I2S2_TXD */ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), /* CLKREQ_CNV# */ -/* I2S2_RXD */ PAD_NC(GPP_H3, NONE), +/* I2S2_RXD */ PAD_CFG_GPI(GPP_H3, NONE, DEEP), /* CNVI_EN# */ /* I2C2_SDA */ PAD_NC(GPP_H4, NONE), -/* I2C2_SCL */ PAD_NC(GPP_H5, NONE), /* I2C3_SDA */ PAD_NC(GPP_H6, NONE), /* I2C3_SCL */ PAD_NC(GPP_H7, NONE), -/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */ -/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */ +/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), +/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C5_SDA */ PAD_NC(GPP_H10, NONE), /* ISH_I2C2_SDA */ /* I2C5_SCL */ PAD_NC(GPP_H11, NONE), /* ISH_I2C2_SCL */ /* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE), @@ -219,7 +205,7 @@ /* TIMESYNC0 */ PAD_NC(GPP_H19, NONE), /* IMGCLKOUT1 */ PAD_NC(GPP_H20, NONE), /* GPP_H21 */ PAD_NC(GPP_H21, NONE), -/* GPP_H22 */ PAD_NC(GPP_H22, NONE), /* RTD3_CIO_PWR_EN (nostuff) */ +/* GPP_H22 */ PAD_NC(GPP_H22, NONE), /* GPP_H23 */ PAD_NC(GPP_H23, NONE),
/* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* BATLOW# */ @@ -229,11 +215,11 @@ /* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SIO_SLP_S3# */ /* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* SIO_SLP_S4# */ /* SLP_A# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), /* SIO_SLP_A# */ -/* GPD7 */ PAD_NC(GPD7, NONE), /* TBT_RTD3_WAKE# (nostuff) */ +/* GPD7 */ PAD_NC(GPD7, NONE), /* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SUSCLK */ /* SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1), /* SIO_SLP_WLAN# */ /* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), /* SIO_SLP_S5# */ -/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), /* PM_LANPHY_EN */ +/* LANPHYC */ PAD_NC(GPD11, NONE), /* PM_LANPHY_EN */ };
/* Early pad configuration in bootblock */ @@ -241,10 +227,10 @@ /* M2_SKT2_CFG1 */ PAD_CFG_GPO(GPP_H13, 1, DEEP), /* M.2 SSD D3 cold */ /* SSD RESET pin will stay low first */ /* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 0, DEEP), /* D3 cold RST */ -/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */ -/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */ -/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */ -/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */ +/* UART2_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* SERVOTX_UART */ +/* UART2_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* SERVORX_UART */ +/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* SDA_PCH_H1 */ +/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* SCL_PCH_H1 */ /* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST, EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */ /* RESET# need to stay low before FULL_CARD_POWER_OFF assert */ @@ -253,6 +239,14 @@ /* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */ /* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* PCH_WP */ /* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 1, DEEP), /* D3 cold RST */ +/* GPP_F1 */ PAD_CFG_GPI(GPP_F1, NONE, DEEP), /* DDR_CHA_EN_1P8 */ +/* GPP_F2 */ PAD_CFG_GPI(GPP_F2, NONE, DEEP), /* DDR_CHB_EN_1P8 */ +/* EMMC_DATA0 */ PAD_CFG_GPI(GPP_F12, NONE, DEEP), /* MEM_CONFIGO_1P8 */ +/* EMMC_DATA1 */ PAD_CFG_GPI(GPP_F13, NONE, DEEP), /* MEM_CONFIGO_1P8 */ +/* EMMC_DATA2 */ PAD_CFG_GPI(GPP_F14, NONE, DEEP), /* MEM_CONFIGO_1P8 */ +/* EMMC_DATA3 */ PAD_CFG_GPI(GPP_F15, NONE, DEEP), /* MEM_CONFIGO_1P8 */ +/* EMMC_DATA4 */ PAD_CFG_GPI(GPP_F16, NONE, DEEP), /* MEM_CONFIGO_1P8 */ +/* I2C2_SCL */ PAD_CFG_GPI(GPP_H5, NONE, PLTRST), /* 360_SENSOR_DET# */ };
const struct pad_config *variant_gpio_table(size_t *num)
-
build bot (Jenkins) (Code Review) -
EricR Lai (Code Review)
-
Mathew King (Code Review)
-
Patrick Georgi (Code Review)
-
Paul Menzel (Code Review)
-
Selma Bensaid (Code Review)
-
Varun Joshi (Code Review)