2 comments:
File src/mainboard/google/drallion/variants/drallion/gpio.c:
Patch Set #9, Line 166: /* GPP_F1 */ PAD_CFG_GPI(GPP_F1, NONE, DEEP), /* DDR_CHA_EN_1P8 */
We should put this into early_gpio_table. F1/F2 based on Duncan's comment.https://review.coreboot.org/c/coreboot/+/35241
Patch Set #9, Line 177: /* EMMC_DATA0 */ PAD_CFG_GPI(GPP_F12, NONE, DEEP), /* MEM_CONFIGO_1P8 */
We should put this into early_gpio_table. See here:https://review.coreboot.org/c/coreboot/+/35141/7/src/mainboard/google/drallion/variants/drallion/gpio.c
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