38 comments:
File src/mainboard/google/drallion/variants/drallion/gpio.c:
Patch Set #3, Line 27: /* SERIRQ */ PAD_NC(GPP_A6, NONE),
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Patch Set #3, Line 27: /* SERIRQ */ PAD_NC(GPP_A6, NONE),
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Patch Set #3, Line 28: /* TPM_PIRQ#_A7 */ PAD_CFG_GPI_APIC(GPP_A7, NONE, PLTRST,
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Patch Set #3, Line 40: /* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF2), /* ISH_P_SENSOR_INT# */
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Patch Set #3, Line 52: /* CORE_VID0 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
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Patch Set #3, Line 52: /* CORE_VID0 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
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Patch Set #3, Line 53: /* CORE_VID1 */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
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Patch Set #3, Line 59: /* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
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Patch Set #3, Line 68: /* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
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Patch Set #3, Line 69: /* EXT_PWR_GATE# */ PAD_CFG_GPO(GPP_B11, 0, PLTRST), /* 3.3V_CAM_EN# */
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Patch Set #3, Line 73: /* GSPI0_CS# */ PAD_CFG_GPO(GPP_B15, 0, PLTRST), /* PRIM_CORE_OPT_DIS */
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Patch Set #3, Line 78: /* GSPI1_CLK */ PAD_CFG_GPI(GPP_B20, NONE, PLTRST),
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Patch Set #3, Line 79: /* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 1, PLTRST), /* PCH_3.3V_TS_EN */
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Patch Set #3, Line 83: /* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* MEM_SMBCLK */
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Patch Set #3, Line 84: /* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* MEM_SMBDATA */
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Patch Set #3, Line 91: /* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* SERVOTX_UART */
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Patch Set #3, Line 92: /* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* SERVOTX_UART */
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Patch Set #3, Line 99: /* UART1_CTS# */ PAD_CFG_GPO(GPP_C15, 0, PLTRST),
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Patch Set #3, Line 104: /* UART2_RXD */ PAD_NC(GPP_C20, NONE),
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Patch Set #3, Line 105: /* UART2_TXD */ PAD_NC(GPP_C21, NONE),
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Patch Set #3, Line 113: /* SPI1_MISO */ PAD_NC(GPP_D2, NONE),
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Patch Set #3, Line 115: /* FASHTRIG */ PAD_CFG_GPO(GPP_D4, 0, PLTRST),
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Patch Set #3, Line 130: /* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 1, PLTRST), /* RTD3_CIO_PWR_EN */
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Patch Set #3, Line 151: /* CPU_GP1 */ PAD_CFG_GPO(GPP_E7, 1, PLTRST), /* TOUCH_SCREEN_PD# */
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Patch Set #3, Line 152: /* SATALED# */ PAD_CFG_GPO(GPP_E8, 1, PLTRST), /* SECURE_BIO */
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Patch Set #3, Line 160: /* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE),
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Patch Set #3, Line 162: /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* CPU_DP1_CTRL_CLK */
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Patch Set #3, Line 163: /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* CPU_DP1_CTRL_CLK */
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Patch Set #3, Line 164: /* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* CPU_DP2_CTRL_CLK */
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Patch Set #3, Line 165: /* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* CPU_DP2_CTRL_CLK */
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Patch Set #3, Line 192: /* A4WP_PRESENT */ PAD_CFG_NF(GPP_F23, NONE, PLTRST, NF1),
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Patch Set #3, Line 199: /* SD_CD# */ PAD_CFG_GPO(GPP_G5, 1, PLTRST), /* HOST_SD_WP# */
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Patch Set #3, Line 200: /* SD_CLK */ PAD_CFG_GPO(GPP_G6, 1, PLTRST), /* AUD_PWR_EN */
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Patch Set #3, Line 223: /* GPP_H22 */ PAD_NC(GPP_H22, NONE),
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