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Change in coreboot[master]: inteltool: Add Sky Lake Xeon E DMI3 Host bridge Id
by Maxim Polyakov (Code Review) 05 Sep '19

05 Sep '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35125 ) Change subject: inteltool: Add Sky Lake Xeon E DMI3 Host bridge Id ...................................................................... inteltool: Add Sky Lake Xeon E DMI3 Host bridge Id Change-Id: I4b429536fc2db16d770120487e4c383da437593a Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M util/inteltool/inteltool.c M util/inteltool/inteltool.h M util/inteltool/memory.c M util/inteltool/pcie.c 4 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/35125/1 diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 6aff416..7eec062 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -128,6 +128,8 @@ "6th generation (Skylake-S family) Core Processor (Desktop)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2, "6th generation (Skylake-S family) Core Processor (Desktop)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_E, + "6th generation (Skylake family) Core Processor Xeon E (Server)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL, "Bay Trail" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U, "7th generation (Kaby Lake family) Core Processor (Mobile)" }, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 4e4bfc0..ec6ca4f 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -286,6 +286,7 @@ #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M 0x1910 /* Skylake (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST 0x1918 /* Skylake (Workstation) */ #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D 0x191f /* Skylake (Desktop) */ +#define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_E 0x2020 /* Sky Lake E (Server) */ #define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U 0x5904 /* Kabylake (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y 0x590C /* Kabylake (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q 0x5914 /* Kabylake (Mobile) */ diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c index 222ac8a..e80f1ba 100644 --- a/util/inteltool/memory.c +++ b/util/inteltool/memory.c @@ -221,6 +221,7 @@ case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_E: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y: diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index 33644ab..b7c72cb 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -267,6 +267,7 @@ case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_E: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q: @@ -393,6 +394,7 @@ case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_E: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q: @@ -503,6 +505,7 @@ case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_E: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q: -- To view, visit https://review.coreboot.org/c/coreboot/+/35125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b429536fc2db16d770120487e4c383da437593a Gerrit-Change-Number: 35125 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: inteltool: add Lewisburg C62x GPIOs support
by Maxim Polyakov (Code Review) 05 Sep '19

05 Sep '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34942 ) Change subject: inteltool: add Lewisburg C62x GPIOs support ...................................................................... inteltool: add Lewisburg C62x GPIOs support These changes are in accordance with the documentation: [*] page 361, Intel(R) C620 Series Chipset Platform Controller Hub (PCH) Datasheet, Document Number: 336067-007US, May 2019 https://www3.intel.com/content/dam/www/public/us/en/documents/ datasheets/c620-series-chipset-datasheet.pdf Tesed on SUPERMICRO MBD-X11DPL-I-O and Intel S2600WF Wolf Pass Change-Id: I43f8f3701de6ab7f89a78c2f5b939b5edd6d5b9d Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M util/inteltool/gpio.c M util/inteltool/gpio_groups.c M util/inteltool/pcr.c 3 files changed, 493 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/34942/1 diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index 741aed4..c433e81 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -1047,6 +1047,13 @@ case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM: + case PCI_DEVICE_ID_INTEL_LEWISBURG_C621: + case PCI_DEVICE_ID_INTEL_LEWISBURG_C622: + case PCI_DEVICE_ID_INTEL_LEWISBURG_C624: + case PCI_DEVICE_ID_INTEL_LEWISBURG_C625: + case PCI_DEVICE_ID_INTEL_LEWISBURG_C626: + case PCI_DEVICE_ID_INTEL_LEWISBURG_C627: + case PCI_DEVICE_ID_INTEL_LEWISBURG_C628: case PCI_DEVICE_ID_INTEL_H310: case PCI_DEVICE_ID_INTEL_H370: case PCI_DEVICE_ID_INTEL_Z390: diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index 0387418..908162c 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -959,6 +959,474 @@ &sunrise_community_gpd, &sunrise_lp_community_fg, }; +static const char *const lewisburg_group_a_names[] = { + "GPP_A0", "RCIN#", "n/a", "ESPI_ALERT1#", + "GPP_A1", "LAD0", "n/a", "ESPI_IO0", + "GPP_A2", "LAD1", "n/a", "ESPI_IO1", + "GPP_A3", "LAD2", "n/a", "ESPI_IO2", + "GPP_A4", "LAD3", "n/a", "ESPI_IO3", + "GPP_A5", "LFRAME#", "n/a", "ESPI_CS0#", + "GPP_A6", "SERIRQ", "n/a", "ESPI_CS1#", + "GPP_A7", "PIRQA#", "n/a", "ESPI_ALERT0#", + "GPP_A8", "CLKRUN#", "n/a", "n/a", + "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK", + "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a", + "GPP_A11", "PME#", "n/a", "n/a", + "GPP_A12", "BM_BUSY#", "n/a", "SX_EXIT_HOLDOFF#", + "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a", + "GPP_A14", "n/a", "n/a", "ESPI_RESET#", + "GPP_A15", "SUS_ACK#", "n/a", "n/a", + "GPP_A16", "CLKOUT_LPC2", "n/a", "n/a", + "GPP_A17", "n/a", "n/a", "n/a", + "GPP_A18", "n/a", "n/a", "n/a", + "GPP_A19", "n/a", "n/a", "n/a", + "GPP_A20", "n/a", "n/a", "n/a", + "GPP_A21", "n/a", "n/a", "n/a", + "GPP_A22", "n/a", "n/a", "n/a", + "GPP_A23", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group lewisburg_group_a = { + .display = "------- GPIO Group GPP_A -------", + .pad_count = ARRAY_SIZE(lewisburg_group_a_names) / 4, + .func_count = 4, + .pad_names = lewisburg_group_a_names, +}; + +static const char *const lewisburg_group_b_names[] = { + "GPP_B0", "CORE_VID0", "n/a", "n/a", + "GPP_B1", "CORE_VID1", "n/a", "n/a", + "GPP_B2", "n/a", "n/a", "n/a", + "GPP_B3", "CPU_GP2", "n/a", "n/a", + "GPP_B4", "CPU_GP3", "n/a", "n/a", + "GPP_B5", "SRCCLKREQ0#", "n/a", "n/a", + "GPP_B6", "SRCCLKREQ1#", "n/a", "n/a", + "GPP_B7", "SRCCLKREQ2#", "n/a", "n/a", + "GPP_B8", "SRCCLKREQ3#", "n/a", "n/a", + "GPP_B9", "SRCCLKREQ4#", "n/a", "n/a", + "GPP_B10", "SRCCLKREQ5#", "n/a", "n/a", + "GPP_B11", "n/a", "n/a", "n/a", + "GPP_B12", "GLB_RST_WARN_N#", "n/a", "n/a", + "GPP_B13", "PLTRST#", "n/a", "n/a", + "GPP_B14", "SPKR", "n/a", "n/a", + "GPP_B15", "n/a", "n/a", "n/a", + "GPP_B16", "n/a", "n/a", "n/a", + "GPP_B17", "n/a", "n/a", "n/a", + "GPP_B18", "n/a", "n/a", "n/a", + "GPP_B19", "n/a", "n/a", "n/a", + "GPP_B20", "n/a", "n/a", "n/a", + "GPP_B21", "n/a", "n/a", "n/a", + "GPP_B22", "n/a", "n/a", "n/a", + "GPP_B23", "SML1ALERT#", "PCHHOT#", "MEIE_SML1ALRT#", +}; + +static const struct gpio_group lewisburg_group_b = { + .display = "------- GPIO Group GPP_B -------", + .pad_count = ARRAY_SIZE(lewisburg_group_b_names) / 4, + .func_count = 4, + .pad_names = lewisburg_group_b_names, +}; + +static const char *const lewisburg_group_c_names[] = { + "GPP_C0", "SMBCLK", "n/a", "n/a", + "GPP_C1", "SMBDATA", "n/a", "n/a", + "GPP_C2", "SMBALERT#", "n/a", "n/a", + "GPP_C3", "SML0CLK", "SML0CLK_IE#", "n/a", + "GPP_C4", "SML0DATA", "SML0DATA_IE", "n/a", + "GPP_C5", "SML0ALERT#", "SML0ALERT_IE#", "n/a", + "GPP_C6", "SML1CLK", "SML1CLK_IE", "n/a", + "GPP_C7", "SML1DATA", "SML1DATA_IE", "n/a", + "GPP_C8", "n/a", "n/a", "n/a", + "GPP_C9", "n/a", "n/a", "n/a", + "GPP_C10", "n/a", "n/a", "n/a", + "GPP_C11", "n/a", "n/a", "n/a", + "GPP_C12", "n/a", "n/a", "n/a", + "GPP_C13", "n/a", "n/a", "n/a", + "GPP_C14", "n/a", "n/a", "n/a", + "GPP_C15", "n/a", "n/a", "n/a", + "GPP_C16", "n/a", "n/a", "n/a", + "GPP_C17", "n/a", "n/a", "n/a", + "GPP_C18", "n/a", "n/a", "n/a", + "GPP_C19", "n/a", "n/a", "n/a", + "GPP_C20", "n/a", "n/a", "n/a", + "GPP_C21", "n/a", "n/a", "n/a", + "GPP_C22", "n/a", "n/a", "n/a", + "GPP_C23", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group lewisburg_group_c = { + .display = "------- GPIO Group GPP_C -------", + .pad_count = ARRAY_SIZE(lewisburg_group_c_names) / 4, + .func_count = 4, + .pad_names = lewisburg_group_c_names, +}; + +static const char *const lewisburg_group_d_names[] = { + "GPP_D0", "n/a", "n/a", "SERIAL_BLINK", + "GPP_D1", "n/a", "n/a", "SERIAL_BLINK", + "GPP_D2", "n/a", "n/a", "SERIAL_BLINK", + "GPP_D3", "n/a", "n/a", "SERIAL_BLINK", + "GPP_D4", "n/a", "n/a", "SERIAL_BLINK", + "GPP_D5", "n/a", "n/a", "n/a", + "GPP_D6", "n/a", "n/a", "n/a", + "GPP_D7", "n/a", "n/a", "n/a", + "GPP_D8", "n/a", "n/a", "n/a", + "GPP_D9", "n/a", "n/a", "SSATA_DEVSLP3", + "GPP_D10", "n/a", "n/a", "SSATA_DEVSLP4", + "GPP_D11", "n/a", "n/a", "SSATA_DEVSLP5", + "GPP_D12", "n/a", "n/a", "SSATA_SDATAOUT1", + "GPP_D13", "n/a", "SML0BCLK", "SML0BCLK_IE", + "GPP_D14", "n/a", "SML0BDATA", "SML0BDATA_IE", + "GPP_D15", "n/a", "n/a", "SSATA_SDATAOUT0", + "GPP_D16", "n/a", "SML0BALERT#", "SML0BALERT_IE#", + "GPP_D17", "n/a", "n/a", "n/a", + "GPP_D18", "n/a", "n/a", "n/a", + "GPP_D19", "n/a", "n/a", "n/a", + "GPP_D20", "n/a", "n/a", "n/a", + "GPP_D21", "n/a", "n/a", "IE_UART_RX", + "GPP_D22", "n/a", "n/a", "IE_UART_TX", + "GPP_D23", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group lewisburg_group_d = { + .display = "------- GPIO Group GPP_D -------", + .pad_count = ARRAY_SIZE(lewisburg_group_d_names) / 4, + .func_count = 4, + .pad_names = lewisburg_group_d_names, +}; + +/* The functions in this group are the same as in the pad group E for + the Sunrise chipset */ +static const struct gpio_group lewisburg_group_e = { + .display = "------- GPIO Group GPP_E -------", + .pad_count = ARRAY_SIZE(sunrise_group_e_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_e_names, +}; + +static const char *const lewisburg_group_f_names[] = { + "GPP_F0", "SATAXPCIE3", "n/a", "SATAGP3", + "GPP_F1", "SATAXPCIE4", "n/a", "SATAGP4", + "GPP_F2", "SATAXPCIE5", "n/a", "SATAGP5", + "GPP_F3", "SATAXPCIE6", "n/a", "SATAGP6", + "GPP_F4", "SATAXPCIE7", "n/a", "SATAGP7", + "GPP_F5", "SATA_DEVSLP3", "n/a", "n/a", + "GPP_F6", "SATA_DEVSLP4", "n/a", "n/a", + "GPP_F7", "SATA_DEVSLP5", "n/a", "n/a", + "GPP_F8", "SATA_DEVSLP6", "n/a", "n/a", + "GPP_F9", "SATA_DEVSLP7", "n/a", "n/a", + "GPP_F10", "SATA_SCLOCK", "n/a", "n/a", + "GPP_F11", "SATA_SLOAD", "n/a", "n/a", + "GPP_F12", "SATA_SDATAOUT1", "n/a", "n/a", + "GPP_F13", "SATA_SDATAOUT2", "n/a", "n/a", + "GPP_F14", "n/a", "n/a", "SSATA_LED#", + "GPP_F15", "USB_OC4#", "n/a", "n/a", + "GPP_F16", "USB_OC5#", "n/a", "n/a", + "GPP_F17", "USB_OC6#", "n/a", "n/a", + "GPP_F18", "USB_OC7#", "n/a", "n/a", + "GPP_F19", "LAN_SMBCLK", "n/a", "n/a", + "GPP_F20", "LAN_SMBDATA", "n/a", "n/a", + "GPP_F21", "LAN_SMBALRT#", "n/a", "n/a", + "GPP_F22", "n/a", "n/a", "SSATA_SCLOCK", + "GPP_F23", "n/a", "n/a", "SSATA_SLOAD", +}; + +static const struct gpio_group lewisburg_group_f = { + .display = "------- GPIO Group GPP_F -------", + .pad_count = ARRAY_SIZE(lewisburg_group_f_names) / 4, + .func_count = 4, + .pad_names = lewisburg_group_f_names, +}; + +static const char *const lewisburg_group_g_names[] = { + "GPP_G0", "FAN_TACH_0", "FAN_TACH_0_IE", "n/a", + "GPP_G1", "FAN_TACH_1", "FAN_TACH_1_IE", "n/a", + "GPP_G2", "FAN_TACH_2", "FAN_TACH_2_IE", "n/a", + "GPP_G3", "FAN_TACH_3", "FAN_TACH_3_IE", "n/a", + "GPP_G4", "FAN_TACH_4", "FAN_TACH_4_IE", "n/a", + "GPP_G5", "FAN_TACH_5", "FAN_TACH_5_IE", "n/a", + "GPP_G6", "FAN_TACH_6", "FAN_TACH_6_IE", "n/a", + "GPP_G7", "FAN_TACH_7", "FAN_TACH_7_IE", "n/a", + "GPP_G8", "FAN_PWM_0", "FAN_PWM_0_IE", "n/a", + "GPP_G9", "FAN_PWM_1", "FAN_PWM_1_IE", "n/a", + "GPP_G10", "FAN_PWM_2", "FAN_PWM_2_IE", "n/a", + "GPP_G11", "FAN_PWM_3", "FAN_PWM_3_IE", "n/a", + "GPP_G12", "n/a", "n/a", "n/a", + "GPP_G13", "n/a", "n/a", "n/a", + "GPP_G14", "n/a", "n/a", "n/a", + "GPP_G15", "n/a", "n/a", "n/a", + "GPP_G16", "n/a", "n/a", "n/a", + "GPP_G17", "ADR_COMPLETE", "n/a", "n/a", + "GPP_G18", "NMI#", "n/a", "n/a", + "GPP_G19", "SMI#", "n/a", "n/a", + "GPP_G20", "n/a", "SSATA_DEVSLP0", "n/a", + "GPP_G21", "n/a", "SSATA_DEVSLP1", "n/a", + "GPP_G22", "n/a", "SSATA_DEVSLP2", "n/a", + "GPP_G23", "n/a", "SSATAXPCIE0", "SSATAGP0", +}; + +static const struct gpio_group lewisburg_group_g = { + .display = "------- GPIO Group GPP_G -------", + .pad_count = ARRAY_SIZE(lewisburg_group_g_names) / 4, + .func_count = 4, + .pad_names = lewisburg_group_g_names, +}; + +static const char *const lewisburg_group_h_names[] = { + "GPP_H0", "SRCCLKREQ6#", "n/a", "n/a", + "GPP_H1", "SRCCLKREQ7#", "n/a", "n/a", + "GPP_H2", "SRCCLKREQ8#", "n/a", "n/a", + "GPP_H3", "SRCCLKREQ9#", "n/a", "n/a", + "GPP_H4", "SRCCLKREQ10#", "n/a", "n/a", + "GPP_H5", "SRCCLKREQ11#", "n/a", "n/a", + "GPP_H6", "SRCCLKREQ12#", "n/a", "n/a", + "GPP_H7", "SRCCLKREQ13#", "n/a", "n/a", + "GPP_H8", "SRCCLKREQ14#", "n/a", "n/a", + "GPP_H9", "SRCCLKREQ15#", "n/a", "n/a", + "GPP_H10", "SML2CLK", "SML2CLK_IE", "n/a", + "GPP_H11", "SML2DATA", "SML2DATA_IE", "n/a", + "GPP_H12", "SML2ALERT#", "SML2ALERT#_IE#", "n/a", + "GPP_H13", "SML3CLK", "SML3CLK_IE", "n/a", + "GPP_H14", "SML3DATA", "SML3DATA_IE", "n/a", + "GPP_H15", "SML3ALERT#", "SML3ALERT#_IE#", "n/a", + "GPP_H16", "SML4CLK", "SML4CLK_IE", "n/a", + "GPP_H17", "SML4DATA", "SML4DATA_IE", "n/a", + "GPP_H18", "SML4ALERT#", "SML4ALERT#_IE#", "n/a", + "GPP_H19", "n/a", "SSATAXPCIE1", "SSATAGP1", + "GPP_H20", "n/a", "SSATAXPCIE2", "SSATAGP2", + "GPP_H21", "n/a", "SSATAXPCIE3", "SSATAGP3", + "GPP_H22", "n/a", "SSATAXPCIE4", "SSATAGP4", + "GPP_H23", "n/a", "SSATAXPCIE5", "SSATAGP5", +}; + +static const struct gpio_group lewisburg_group_h = { + .display = "------- GPIO Group GPP_H -------", + .pad_count = ARRAY_SIZE(lewisburg_group_h_names) / 4, + .func_count = 4, + .pad_names = lewisburg_group_h_names, +}; + +static const char *const lewisburg_group_i_names[] = { + "GPP_I0", "n/a", "LAN_TDO", "n/a", + "GPP_I1", "n/a", "LAN_TCK", "n/a", + "GPP_I2", "n/a", "LAN_TMS", "n/a", + "GPP_I3", "n/a", "LAN_TDI", "n/a", + "GPP_I4", "n/a", "RESET_IN#", "n/a", + "GPP_I5", "n/a", "RESET_OUT#", "n/a", + "GPP_I6", "n/a", "RESET_DONE", "n/a", + "GPP_I7", "n/a", "LAN_TRST_IN", "n/a", + "GPP_I8", "n/a", "PCI_DIS", "n/a", + "GPP_I9", "n/a", "LAN_DIS", "n/a", + "GPP_I10", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group lewisburg_group_i = { + .display = "------- GPIO Group GPP_I -------", + .pad_count = ARRAY_SIZE(lewisburg_group_i_names) / 4, + .func_count = 4, + .pad_names = lewisburg_group_i_names, +}; + +static const char *const lewisburg_group_j_names[] = { + "GPP_J0", "LAN_LED_P0_0", "n/a", "n/a", + "GPP_J1", "LAN_LED_P0_1", "n/a", "n/a", + "GPP_J2", "LAN_LED_P1_0", "n/a", "n/a", + "GPP_J3", "LAN_LED_P1_1", "n/a", "n/a", + "GPP_J4", "LAN_LED_P2_0", "n/a", "n/a", + "GPP_J5", "LAN_LED_P2_1", "n/a", "n/a", + "GPP_J6", "LAN_LED_P3_0", "n/a", "n/a", + "GPP_J7", "LAN_LED_P3_1", "n/a", "n/a", + "GPP_J8", "LAN_I2C_SCL_MDC_P0", "n/a", "n/a", + "GPP_J9", "LAN_I2C_SDA_MDIO_P0", "n/a", "n/a", + "GPP_J10", "LAN_I2C_SCL_MDC_P1", "n/a", "n/a", + "GPP_J11", "LAN_I2C_SDA_MDIO_P1", "n/a", "n/a", + "GPP_J12", "LAN_I2C_SCL_MDC_P2", "n/a", "n/a", + "GPP_J13", "LAN_I2C_SDA_MDIO_P2", "n/a", "n/a", + "GPP_J14", "LAN_I2C_SCL_MDC_P3", "n/a", "n/a", + "GPP_J15", "LAN_I2C_SDA_MDIO_P3", "n/a", "n/a", + "GPP_J16", "LAN_SDP_P0_0", "n/a", "n/a", + "GPP_J17", "LAN_SDP_P0_1", "n/a", "n/a", + "GPP_J18", "LAN_SDP_P1_0", "n/a", "n/a", + "GPP_J19", "LAN_SDP_P1_1", "n/a", "n/a", + "GPP_J20", "LAN_SDP_P2_0", "n/a", "n/a", + "GPP_J21", "LAN_SDP_P2_1", "n/a", "n/a", + "GPP_J22", "LAN_SDP_P3_0", "n/a", "n/a", + "GPP_J23", "LAN_SDP_P3_1", "n/a", "n/a", +}; + +static const struct gpio_group lewisburg_group_j = { + .display = "------- GPIO Group GPP_J -------", + .pad_count = ARRAY_SIZE(lewisburg_group_j_names) / 4, + .func_count = 4, + .pad_names = lewisburg_group_j_names, +}; + +static const char *const lewisburg_group_k_names[] = { + "GPP_K0", "LAN_NCSI_CLK_IN", "n/a", "n/a", + "GPP_K1", "LAN_NCSI_TXD0", "n/a", "n/a", + "GPP_K2", "LAN_NCSI_TXD1", "n/a", "n/a", + "GPP_K3", "LAN_NCSI_TX_EN", "n/a", "n/a", + "GPP_K4", "LAN_NCSI_CRS_DV", "n/a", "n/a", + "GPP_K5", "LAN_NCSI_RXD0", "n/a", "n/a", + "GPP_K6", "LAN_NCSI_RXD1", "n/a", "n/a", + "GPP_K7", "RESERVED", "n/a", "n/a", + "GPP_K8", "LAN_NCSI_ARB_IN", "n/a", "n/a", + "GPP_K9", "LAN_NCSI_ARB_OUT", "n/a", "n/a", + "GPP_K10", "PE_RST#", "n/a", "n/a", + "GPP_K11", "n/a", "n/a", "n/a", + "GPP_K12", "n/a", "n/a", "n/a", + "GPP_K13", "n/a", "n/a", "n/a", + "GPP_K14", "n/a", "n/a", "n/a", + "GPP_K15", "n/a", "n/a", "n/a", + "GPP_K16", "n/a", "n/a", "n/a", + "GPP_K17", "n/a", "n/a", "n/a", + "GPP_K18", "n/a", "n/a", "n/a", + "GPP_K19", "n/a", "n/a", "n/a", + "GPP_K20", "n/a", "n/a", "n/a", + "GPP_K21", "n/a", "n/a", "n/a", + "GPP_K22", "n/a", "n/a", "n/a", + "GPP_K23", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group lewisburg_group_k = { + .display = "------- GPIO Group GPP_K -------", + .pad_count = ARRAY_SIZE(lewisburg_group_k_names) / 4, + .func_count = 4, + .pad_names = lewisburg_group_k_names, +}; + +static const char *const lewisburg_group_l_names[] = { + "GPP_L2", "TESTCH0_D0", "n/a", "n/a", + "GPP_L3", "TESTCH0_D1", "n/a", "n/a", + "GPP_L4", "TESTCH0_D2", "n/a", "n/a", + "GPP_L5", "TESTCH0_D3", "n/a", "n/a", + "GPP_L6", "TESTCH0_D4", "n/a", "n/a", + "GPP_L7", "TESTCH0_D5", "n/a", "n/a", + "GPP_L8", "TESTCH0_D6", "n/a", "n/a", + "GPP_L9", "TESTCH0_D7", "n/a", "n/a", + "GPP_L10", "TESTCH0_CLK", "n/a", "n/a", + "GPP_L11", "TESTCH1_D0", "n/a", "n/a", + "GPP_L12", "TESTCH1_D1", "n/a", "n/a", + "GPP_L13", "TESTCH1_D2", "n/a", "n/a", + "GPP_L14", "TESTCH1_D3", "n/a", "n/a", + "GPP_L15", "TESTCH1_D4", "n/a", "n/a", + "GPP_L16", "TESTCH1_D5", "n/a", "n/a", + "GPP_L17", "TESTCH1_D6", "n/a", "n/a", + "GPP_L18", "TESTCH1_D7", "n/a", "n/a", + "GPP_L19", "TESTCH1_CLK", "n/a", "n/a", +}; + +static const struct gpio_group lewisburg_group_l = { + .display = "------- GPIO Group GPP_L -------", + .pad_count = ARRAY_SIZE(lewisburg_group_l_names) / 4, + .func_count = 4, + .pad_names = lewisburg_group_l_names, +}; + +static const char *const lewisburg_group_gpd_names[] = { + "GPD0", "POWER_DEBUG_N", "n/a", "n/a", + "GPD1", "ACPRESENT", "n/a", "n/a", + "GPD2", "GBE_WAKE#", "n/a", "n/a", + "GPD3", "PWRBTN#", "n/a", "n/a", + "GPD4", "SLP_S3#", "n/a", "n/a", + "GPD5", "SLP_S4#", "n/a", "n/a", + "GPD6", "SLP_A#", "n/a", "n/a", + "GPD7", "RESERVED", "n/a", "n/a", + "GPD8", "SUSCLK", "n/a", "n/a", + "GPD9", "RESERVED", "n/a", "n/a", + "GPD10", "SLP_S5#", "n/a", "n/a", + "GPD11", "GBEPHY", "n/a", "n/a", +}; + +static const struct gpio_group lewisburg_group_gpd = { + .display = "-------- GPIO Group GPD --------", + .pad_count = ARRAY_SIZE(lewisburg_group_gpd_names) / 4, + .func_count = 4, + .pad_names = lewisburg_group_gpd_names, +}; + +static const struct gpio_group *const lewisburg_community0_abf_groups[] = { + &lewisburg_group_a, + &lewisburg_group_b, + &lewisburg_group_f, +}; + +static const struct gpio_community lewisburg_community0_abf = { + .name = "------- GPIO Community 0 -------", + .pcr_port_id = 0xaf, + .group_count = ARRAY_SIZE(lewisburg_community0_abf_groups), + .groups = lewisburg_community0_abf_groups, +}; + +static const struct gpio_group *const lewisburg_community1_cde_groups[] = { + &lewisburg_group_c, + &lewisburg_group_d, + &lewisburg_group_e, +}; + +static const struct gpio_community lewisburg_community1_cde = { + .name = "------- GPIO Community 1 -------", + .pcr_port_id = 0xae, + .group_count = ARRAY_SIZE(lewisburg_community1_cde_groups), + .groups = lewisburg_community1_cde_groups, +}; + +static const struct gpio_group *const lewisburg_community2_gpd_groups[] = { + &lewisburg_group_gpd, +}; + +static const struct gpio_community lewisburg_community2_gpd = { + .name = "------- GPIO Community 2 -------", + .pcr_port_id = 0xad, + .group_count = ARRAY_SIZE(lewisburg_community2_gpd_groups), + .groups = lewisburg_community2_gpd_groups, +}; + +static const struct gpio_group *const lewisburg_community3_i_groups[] = { + &lewisburg_group_i, +}; + +static const struct gpio_community lewisburg_community3_i = { + .name = "------- GPIO Community 3 -------", + .pcr_port_id = 0xac, + .group_count = ARRAY_SIZE(lewisburg_community3_i_groups), + .groups = lewisburg_community3_i_groups, +}; + +static const struct gpio_group *const lewisburg_community4_jk_groups[] = { + &lewisburg_group_j, + &lewisburg_group_k, +}; + +static const struct gpio_community lewisburg_community4_jk = { + .name = "------- GPIO Community 4 -------", + .pcr_port_id = 0xab, + .group_count = ARRAY_SIZE(lewisburg_community4_jk_groups), + .groups = lewisburg_community4_jk_groups, +}; + +static const struct gpio_group *const lewisburg_community5_ghl_groups[] = { + &lewisburg_group_g, + &lewisburg_group_h, + &lewisburg_group_l, +}; + +static const struct gpio_community lewisburg_community5_ghl = { + .name = "------- GPIO Community 5 -------", + .pcr_port_id = 0x11, + .group_count = ARRAY_SIZE(lewisburg_community5_ghl_groups), + .groups = lewisburg_community5_ghl_groups, +}; + +static const struct gpio_community *const lewisburg_communities[] = { + &lewisburg_community0_abf, + &lewisburg_community1_cde, + &lewisburg_community2_gpd, + &lewisburg_community3_i, + &lewisburg_community4_jk, + &lewisburg_community5_ghl, +}; + static const char *const denverton_group_north_all_names[] = { "NORTH_ALL_GBE0_SDP0", "NORTH_ALL_GBE1_SDP0", @@ -1801,6 +2269,17 @@ communities = sunrise_lp_communities; pcr_init(sb); break; + case PCI_DEVICE_ID_INTEL_LEWISBURG_C621: + case PCI_DEVICE_ID_INTEL_LEWISBURG_C622: + case PCI_DEVICE_ID_INTEL_LEWISBURG_C624: + case PCI_DEVICE_ID_INTEL_LEWISBURG_C625: + case PCI_DEVICE_ID_INTEL_LEWISBURG_C626: + case PCI_DEVICE_ID_INTEL_LEWISBURG_C627: + case PCI_DEVICE_ID_INTEL_LEWISBURG_C628: + community_count = ARRAY_SIZE(lewisburg_communities); + communities = lewisburg_communities; + pcr_init(sb); + break; case PCI_DEVICE_ID_INTEL_DNV_LPC: community_count = ARRAY_SIZE(denverton_communities); communities = denverton_communities; diff --git a/util/inteltool/pcr.c b/util/inteltool/pcr.c index c969620..d6d86e8 100644 --- a/util/inteltool/pcr.c +++ b/util/inteltool/pcr.c @@ -103,6 +103,13 @@ case PCI_DEVICE_ID_INTEL_HM175: case PCI_DEVICE_ID_INTEL_QM175: case PCI_DEVICE_ID_INTEL_CM238: + case PCI_DEVICE_ID_INTEL_LEWISBURG_C621: + case PCI_DEVICE_ID_INTEL_LEWISBURG_C622: + case PCI_DEVICE_ID_INTEL_LEWISBURG_C624: + case PCI_DEVICE_ID_INTEL_LEWISBURG_C625: + case PCI_DEVICE_ID_INTEL_LEWISBURG_C626: + case PCI_DEVICE_ID_INTEL_LEWISBURG_C627: + case PCI_DEVICE_ID_INTEL_LEWISBURG_C628: case PCI_DEVICE_ID_INTEL_DNV_LPC: p2sb = pci_get_dev(sb->access, 0, 0, 0x1f, 1); break; -- To view, visit https://review.coreboot.org/c/coreboot/+/34942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43f8f3701de6ab7f89a78c2f5b939b5edd6d5b9d Gerrit-Change-Number: 34942 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

5 21

Change in coreboot[master]: mb/google/octopus: Load custom SAR values by SKU ID for Bloog
by Tony Huang (Code Review) 05 Sep '19

05 Sep '19

Tony Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35097 ) Change subject: mb/google/octopus: Load custom SAR values by SKU ID for Bloog ...................................................................... mb/google/octopus: Load custom SAR values by SKU ID for Bloog Use sku-id to load the SAR values. SKU ID map 33 to 36 for Bloog 49 to 52 for Blooguard BUG=b:138180187 BRANCH=octopus TEST=build and verify SAR load by sku-id Change-Id: Id0bc2609fd1c4eaeb380f8f1532ab30d34e2aeb3 Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/octopus/variants/bloog/variant.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/35097/1 diff --git a/src/mainboard/google/octopus/variants/bloog/variant.c b/src/mainboard/google/octopus/variants/bloog/variant.c index 58b3bc4..6484080 100644 --- a/src/mainboard/google/octopus/variants/bloog/variant.c +++ b/src/mainboard/google/octopus/variants/bloog/variant.c @@ -29,6 +29,9 @@ if (sku_id == SKU_UNKNOWN) return NULL; + if (sku_id == 33 || sku_id == 34 || sku_id == 35 || sku_id == 36) + filename = "wifi_sar-bloog.hex"; + if (sku_id == 49 || sku_id == 50 || sku_id == 51 || sku_id == 52) filename = "wifi_sar-blooguard.hex"; -- To view, visit https://review.coreboot.org/c/coreboot/+/35097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0bc2609fd1c4eaeb380f8f1532ab30d34e2aeb3 Gerrit-Change-Number: 35097 Gerrit-PatchSet: 1 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: cpu/intel/car: Skip stack integrity check if FSP_USES_CB_STACK is enable
by Subrata Banik (Code Review) 05 Sep '19

05 Sep '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35165 ) Change subject: cpu/intel/car: Skip stack integrity check if FSP_USES_CB_STACK is enable ...................................................................... cpu/intel/car: Skip stack integrity check if FSP_USES_CB_STACK is enable With FSP2.1 FSP_USES_CB_STACK likely to be enable. Impacted platforms are CML and ICL. Don't need to run code logic to check the integrity of stack if FSP and coreboot both likely to make use of common stack. Notified by CONFIG_FSP_USES_CB_STACK, its expected to print "Smashed stack detected in romstage!" msg multiple time in that case. This patch fixes CML/ICL platform printing "Smashed stack detected in romstage!" multiple times. This prints might be misleading. TEST=Build and boot CML-Hatch With this CL No "Smashed stack detected in romstage!" msg in serial log. Without this CL "Smashed stack detected in romstage!" 64 times in serial log after FSP-M returns into coreboot. Change-Id: I943eff1225b976dc4440a6ca6d02ceea378319f8 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/cpu/intel/car/romstage.c 1 file changed, 13 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/35165/1 diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 547b121..78b2b8d 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -54,10 +54,19 @@ mainboard_romstage_entry(); /* Check the stack. */ - for (i = 0; i < num_guards; i++) { - if (stack_base[i] == stack_guard) - continue; - printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n"); + /* + * Don't need to run below logic to check the integrity of stack + * if FSP and coreboot both likely to make use of common stack. + * Notified by CONFIG_FSP_USES_CB_STACK, its expected to print + * "Smashed stack detected in romstage!" msg many times in that case. + */ + if (!CONFIG(FSP_USES_CB_STACK)) { + for (i = 0; i < num_guards; i++) { + if (stack_base[i] == stack_guard) + continue; + printk(BIOS_DEBUG, "Smashed stack detected in" + "romstage!\n"); + } } if (CONFIG(SMM_TSEG)) -- To view, visit https://review.coreboot.org/c/coreboot/+/35165 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I943eff1225b976dc4440a6ca6d02ceea378319f8 Gerrit-Change-Number: 35165 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

10 64

Change in ...coreboot[master]: mediatek: Pass board specific message to BL31
by Tristan Hsieh (Code Review) 05 Sep '19

05 Sep '19

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31604 Change subject: mediatek: Pass board specific message to BL31 ...................................................................... mediatek: Pass board specific message to BL31 Sometimes we need to pass board specific messages to BL31, so that BL31 can do board specific operation based on common code. BUG=b:80501386 BRANCH=none TEST=emerge-kukui coreboot Change-Id: I60b09423d479b356ac5c04517906042fc8d512ca Signed-off-by: Tristan Shieh <tristan.shieh(a)mediatek.com> --- A src/soc/mediatek/common/bl31_plat_params.c A src/soc/mediatek/common/include/soc/bl31_plat_params.h M src/soc/mediatek/mt8183/Makefile.inc 3 files changed, 54 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/31604/1 diff --git a/src/soc/mediatek/common/bl31_plat_params.c b/src/soc/mediatek/common/bl31_plat_params.c new file mode 100644 index 0000000..eb7477a --- /dev/null +++ b/src/soc/mediatek/common/bl31_plat_params.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arm_tf.h> +#include <soc/bl31_plat_params.h> + +static struct bl31_plat_param *plat_params; + +void register_bl31_param(struct bl31_plat_param *param) +{ + param->next = plat_params; + plat_params = param; +} + +void *soc_get_bl31_plat_params(bl31_params_t *bl31_params) +{ + return plat_params; +} diff --git a/src/soc/mediatek/common/include/soc/bl31_plat_params.h b/src/soc/mediatek/common/include/soc/bl31_plat_params.h new file mode 100644 index 0000000..399b0d5 --- /dev/null +++ b/src/soc/mediatek/common/include/soc/bl31_plat_params.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __BL31_PLAT_PARAMS_H__ +#define __BL31_PLAT_PARAMS_H__ + +#include <arm-trusted-firmware/plat/mediatek/common/plat_params.h> + +void register_bl31_param(struct bl31_plat_param *param); + +#endif diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index 8af3d68..fc2bbe2 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -50,6 +50,7 @@ ramstage-y += ../common/usb.c ramstage-y += ../common/wdt.c +ramstage-y += ../common/bl31_plat_params.c BL31_MAKEARGS += PLAT=mt8183 CPPFLAGS_common += -Isrc/soc/mediatek/mt8183/include -- To view, visit https://review.coreboot.org/c/coreboot/+/31604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60b09423d479b356ac5c04517906042fc8d512ca Gerrit-Change-Number: 31604 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-MessageType: newchange

6 11

Change in ...coreboot[master]: soc/mediatek: Register coreboot table for ATF
by Hung-Te Lin (Code Review) 05 Sep '19

05 Sep '19

Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32541 Change subject: soc/mediatek: Register coreboot table for ATF ...................................................................... soc/mediatek: Register coreboot table for ATF Register coreboot table into BL31 parameter so ATF can find coreboot information and use it (for example, use memory console). BUG=None TEST=emerge-kukui coreboot; Boots on Kukui. Change-Id: I6e39495988159608c1c4bbf16a97c86e526bd82b Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/soc/mediatek/common/bl31_plat_params.c 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/32541/1 diff --git a/src/soc/mediatek/common/bl31_plat_params.c b/src/soc/mediatek/common/bl31_plat_params.c index eb7477a..51edab3 100644 --- a/src/soc/mediatek/common/bl31_plat_params.c +++ b/src/soc/mediatek/common/bl31_plat_params.c @@ -14,6 +14,7 @@ */ #include <arm_tf.h> +#include <cbmem.h> #include <soc/bl31_plat_params.h> static struct bl31_plat_param *plat_params; @@ -26,5 +27,13 @@ void *soc_get_bl31_plat_params(bl31_params_t *bl31_params) { + static struct bl31_u64_param cbtable_param = { + .h = { .type = PARAM_COREBOOT_TABLE, }, + }; + if (!cbtable_param.value) { + cbtable_param.value = (uint64_t)cbmem_find(CBMEM_ID_CBTABLE); + if (cbtable_param.value) + register_bl31_param(&cbtable_param.h); + } return plat_params; } -- To view, visit https://review.coreboot.org/c/coreboot/+/32541 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e39495988159608c1c4bbf16a97c86e526bd82b Gerrit-Change-Number: 32541 Gerrit-PatchSet: 1 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: arch/ppc64: add arch_timer
by Marty E. Plummer (Code Review) 05 Sep '19

05 Sep '19

Marty E. Plummer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35171 ) Change subject: arch/ppc64: add arch_timer ...................................................................... arch/ppc64: add arch_timer Based on code from hostboot's timemgr.C file. looks right and the resultant assembly looks correct. Change-Id: I65d7be0fd384e69a069fe8278c313db914763b80 Signed-off-by: Marty E. Plummer <hanetzer(a)startmail.com> --- M src/arch/ppc64/Kconfig M src/arch/ppc64/Makefile.inc A src/arch/ppc64/arch_timer.c A src/arch/ppc64/include/arch/asm.h 4 files changed, 101 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/35171/1 diff --git a/src/arch/ppc64/Kconfig b/src/arch/ppc64/Kconfig index 0f65c0c..41ff074 100644 --- a/src/arch/ppc64/Kconfig +++ b/src/arch/ppc64/Kconfig @@ -20,3 +20,9 @@ select ARCH_PPC64 source "src/arch/ppc64/power8/Kconfig" +source "src/arch/ppc64/power9/Kconfig" + +config PPC64_USE_ARCH_TIMER + bool + default n + diff --git a/src/arch/ppc64/Makefile.inc b/src/arch/ppc64/Makefile.inc index 7a069cd..d6f0b77 100644 --- a/src/arch/ppc64/Makefile.inc +++ b/src/arch/ppc64/Makefile.inc @@ -30,6 +30,7 @@ bootblock-y += stages.c bootblock-y += boot.c bootblock-y += rom_media.c +bootblock-$(CONFIG_PPC64_USE_ARCH_TIMER) += arch_timer.c bootblock-y += \ $(top)/src/lib/memchr.c \ $(top)/src/lib/memcmp.c \ @@ -55,6 +56,7 @@ romstage-y += boot.c romstage-y += stages.c romstage-y += rom_media.c +romstage-$(CONFIG_PPC64_USE_ARCH_TIMER) += arch_timer.c romstage-y += \ $(top)/src/lib/memchr.c \ $(top)/src/lib/memcmp.c \ @@ -84,6 +86,7 @@ ramstage-y += stages.c ramstage-y += boot.c ramstage-y += tables.c +ramstage-$(CONFIG_PPC64_USE_ARCH_TIMER) += arch_timer.c ramstage-y += \ $(top)/src/lib/memchr.c \ $(top)/src/lib/memcmp.c \ diff --git a/src/arch/ppc64/arch_timer.c b/src/arch/ppc64/arch_timer.c new file mode 100644 index 0000000..c988a34 --- /dev/null +++ b/src/arch/ppc64/arch_timer.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <timer.h> +#include <arch/asm.h> + +void timer_monotonic_get(struct mono_time *mt) +{ + // TODO: see src/kernel/timemgr.C + // looks right for now... + uint64_t value = raw_read_tb(); + uint64_t freq = 512000000ULL; + long usecs = (value * 1000000) / freq; + mono_time_set_usecs(mt, usecs); +} diff --git a/src/arch/ppc64/include/arch/asm.h b/src/arch/ppc64/include/arch/asm.h new file mode 100644 index 0000000..4692f87 --- /dev/null +++ b/src/arch/ppc64/include/arch/asm.h @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __PPC_PPC64_ASM_H +#define __PPC_PPC64_ASM_H + +#define ENDPROC(name) \ + .type name, % function; \ + END(name) + +#define ENTRY_WITH_ALIGN(name, bits) \ + .section.text.name, "ax", % progbits; \ + .global name; \ + .align bits; \ + name: + +#define ENTRY(name) ENTRY_WITH_ALIGN(name, 2) + +#define END(name) .size name, .- name + +/* Special Purpose Registers */ +#define SPRN_TBRL 268 +#define SPRN_TBRU 269 + + +#ifndef __ASSEMBLER__ + +#include <stdint.h> + +#define MAKE_REGISTER_READ(reg) \ + static inline uint64_t raw_read_##reg(void) \ + { \ + uint64_t value; \ + __asm__ __volatile__("mfspr %0, " #reg "\n\t" : "=r"(value)); \ + return value; \ + } + +#define MAKE_REGISTER_WRITE(reg) \ + static inline void raw_write_##reg(uint64_t value) \ + { \ + __asm__ __volatile__("mtspr " #reg ", %0\n\t" : : "r"(value) : "memory"); \ + } + +#define MAKE_REGISTER_ACCESSORS(reg) \ + MAKE_REGISTER_READ(##reg) \ + MAKE_REGISTER_WRITE(##reg) + +static inline uint64_t raw_read_tb(void) +{ + uint64_t value; + __asm__ __volatile__("mfspr %0, %1\n\t" : "=r"(value) : "i"(SPRN_TBRL)); + return value; +} + +#endif /* __ASSEMBLER__ */ + +#endif /* __PPC_PPC64_ASM_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35171 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65d7be0fd384e69a069fe8278c313db914763b80 Gerrit-Change-Number: 35171 Gerrit-PatchSet: 1 Gerrit-Owner: Marty E. Plummer <hanetzer(a)startmail.com> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: [TEST-ONLY]Update the memory timing table for Treeya to the 2T table....
by Peichao Li (Code Review) 05 Sep '19

05 Sep '19

Peichao Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35116 ) Change subject: [TEST-ONLY]Update the memory timing table for Treeya to the 2T table. Rename the table from Liara specific to simply specifying that it's using 2T command rate ...................................................................... [TEST-ONLY]Update the memory timing table for Treeya to the 2T table. Rename the table from Liara specific to simply specifying that it's using 2T command rate BUG=139841929 TEST=build and do stress test Change-Id: I6e10b95c8aea50e68d8a3b710f30dda4f6b807d3 --- M src/mainboard/google/kahlee/OemCustomize.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/35116/1 diff --git a/src/mainboard/google/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/OemCustomize.c index 886e14f..1b33b03 100644 --- a/src/mainboard/google/kahlee/OemCustomize.c +++ b/src/mainboard/google/kahlee/OemCustomize.c @@ -39,7 +39,7 @@ PSO_END }; /* Liara-specific 2T memory configuration */ -static const PSO_ENTRY DDR4LiaraMemoryConfiguration[] = { +static const PSO_ENTRY DDR4_T2_MemoryConfiguration[] = { DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY), NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, DIMMS_PER_CHANNEL), NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, MAX_DRAM_CH), @@ -58,9 +58,9 @@ void OemPostParams(AMD_POST_PARAMS *PostParams) { - if (CONFIG(BOARD_GOOGLE_LIARA)) + if (CONFIG(BOARD_GOOGLE_LIARA) || CONFIG(BOARD_GOOGLE_TREEYA)) PostParams->MemConfig.PlatformMemoryConfiguration = - (PSO_ENTRY *)DDR4LiaraMemoryConfiguration; + (PSO_ENTRY *)DDR4_T2_MemoryConfiguration; else PostParams->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)DDR4PlatformMemoryConfiguration; -- To view, visit https://review.coreboot.org/c/coreboot/+/35116 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e10b95c8aea50e68d8a3b710f30dda4f6b807d3 Gerrit-Change-Number: 35116 Gerrit-PatchSet: 1 Gerrit-Owner: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com> Gerrit-MessageType: newchange

4 18

Change in coreboot[master]: mb/google/hatch/var/kindred: Update DPTF parameters and TDP PL1/PL2
by David Wu (Code Review) 04 Sep '19

04 Sep '19

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35131 ) Change subject: mb/google/hatch/var/kindred: Update DPTF parameters and TDP PL1/PL2 ...................................................................... mb/google/hatch/var/kindred: Update DPTF parameters and TDP PL1/PL2 Add TEMP_SENSOR_3 to DPTF, Update DPTF parameters and TDP PL1/PL2 values Cq-Depend: chromium:1751304 BUG=b:140127035 TEST=FW_NAME=kindred emerge-hatch coreboot chromeos-ec chromeos-bootimage Change-Id: I1817e277f4641db6bedc8b640b1dc5d57502d5dd Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> --- M src/mainboard/google/hatch/variants/kindred/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/kindred/overridetree.cb 2 files changed, 121 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/35131/1 diff --git a/src/mainboard/google/hatch/variants/kindred/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/kindred/include/variant/acpi/dptf.asl index f1f0943..6f79cd5 100644 --- a/src/mainboard/google/hatch/variants/kindred/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/kindred/include/variant/acpi/dptf.asl @@ -13,4 +13,121 @@ * GNU General Public License for more details. */ -#include <baseboard/acpi/dptf.asl> +#define DPTF_CPU_PASSIVE 90 +#define DPTF_CPU_CRITICAL 105 +#define DPTF_CPU_ACTIVE_AC0 95 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor - Charger" +#define DPTF_TSR0_PASSIVE 65 +#define DPTF_TSR0_CRITICAL 75 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor - CPU" +#define DPTF_TSR1_PASSIVE 60 +#define DPTF_TSR1_CRITICAL 75 +#define DPTF_TSR1_ACTIVE_AC0 51 +#define DPTF_TSR1_ACTIVE_AC1 48 +#define DPTF_TSR1_ACTIVE_AC2 45 +#define DPTF_TSR1_ACTIVE_AC3 42 +#define DPTF_TSR1_ACTIVE_AC4 39 +#define DPTF_TSR1_ACTIVE_AC5 36 +#define DPTF_TSR1_ACTIVE_AC6 33 + +#define DPTF_TSR2_SENSOR_ID 2 +#define DPTF_TSR2_SENSOR_NAME "Thermal Sensor - WIFI" +#define DPTF_TSR2_PASSIVE 65 +#define DPTF_TSR2_CRITICAL 75 +#define DPTF_TSR2_ACTIVE_AC0 55 +#define DPTF_TSR2_ACTIVE_AC1 50 + +#define DPTF_ENABLE_CHARGER +#define DPTF_ENABLE_FAN_CONTROL + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ +}) + +/* DFPS: Fan Performance States */ +Name (DFPS, Package () { + 0, // Revision + /* + * TODO : Need to update this Table after characterization. + * These are initial reference values. + */ + /* Control, Trip Point, Speed, NoiseLevel, Power */ + Package () {90, 0xFFFFFFFF, 6700, 220, 2200}, + Package () {80, 0xFFFFFFFF, 5800, 180, 1800}, + Package () {70, 0xFFFFFFFF, 5000, 145, 1450}, + Package () {60, 0xFFFFFFFF, 4900, 115, 1150}, + Package () {50, 0xFFFFFFFF, 3838, 90, 900}, + Package () {40, 0xFFFFFFFF, 2904, 55, 550}, + Package () {30, 0xFFFFFFFF, 2337, 30, 300}, + Package () {20, 0xFFFFFFFF, 1608, 15, 150}, + Package () {10, 0xFFFFFFFF, 800, 10, 100}, + Package () {0, 0xFFFFFFFF, 0, 0, 50} +}) + +Name (DART, Package () { + /* Fan effect on CPU */ + 0, // Revision + Package () { + /* + * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, + * AC7, AC8, AC9 + */ + \_SB.DPTF.TFN1, \_SB.PCI0.TCPU, 100, 100, 80, 70, 60, 50, 40, 30, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 100, 80, 70, 60, 50, 40, 30, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 90, 80, 70, 60, 50, 40, 30, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR2, 100, 100, 80, 0, 0, 0, 0, 0, + 0, 0, 0 + } +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, + + /* Charger Throttle Effect on Charger (TSR0) */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on CPU (TSR1) */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on WIFI (TSR2) */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 100, 60, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 3000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 15000, /* PowerLimitMinimum */ + 51000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/google/hatch/variants/kindred/overridetree.cb b/src/mainboard/google/hatch/variants/kindred/overridetree.cb index a4ca176..f3f926d 100644 --- a/src/mainboard/google/hatch/variants/kindred/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kindred/overridetree.cb @@ -49,6 +49,9 @@ # Enable eMMC HS400 register "ScsEmmcHs400Enabled" = "1" + register "tdp_pl1_override" = "15" + register "tdp_pl2_override" = "51" + device domain 0 on device pci 15.0 on chip drivers/i2c/generic -- To view, visit https://review.coreboot.org/c/coreboot/+/35131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1817e277f4641db6bedc8b640b1dc5d57502d5dd Gerrit-Change-Number: 35131 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

7 16

Change in ...coreboot[master]: mainboard/amd: Add padmelon board code
by Richard Spiegel (Code Review) 04 Sep '19

04 Sep '19

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33993 Change subject: mainboard/amd: Add padmelon board code ...................................................................... mainboard/amd: Add padmelon board code With almost everything in place, it's time to add padmelon board. There are 2 versions, one using a fanned version of 00670F00 and one using merlinfalcon (00660F01, also fanned), both SOC FP4 sockets. This code was intended for merlinfalcon version, but as there are some legal issues (documentation) blocking its merge to coreboot, it'll be released for 00670F00, being replaced later with merlinfalcon when the binaries can be merged to coreboot (PSP, video and AGESA). Even both use fanned versions of SOC, the actual fan control is done through a SIO, fintek f81803a. BUG=b:none. TEST=Both versions tested and boot to Linux using SeaBIOS. Change-Id: I5a366ddeb4cfebd177a8744f6edb87aecd4787dd Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- A src/mainboard/amd/padmelon/BiosCallOuts.c A src/mainboard/amd/padmelon/BiosCallOuts.h A src/mainboard/amd/padmelon/Kconfig A src/mainboard/amd/padmelon/Kconfig.name A src/mainboard/amd/padmelon/Makefile.inc A src/mainboard/amd/padmelon/OemCustomize.c A src/mainboard/amd/padmelon/acpi/gpe.asl A src/mainboard/amd/padmelon/acpi/mainboard.asl A src/mainboard/amd/padmelon/acpi/routing.asl A src/mainboard/amd/padmelon/acpi/sleep.asl A src/mainboard/amd/padmelon/acpi/superio.asl A src/mainboard/amd/padmelon/acpi/usb_oc.asl A src/mainboard/amd/padmelon/acpi_tables.c A src/mainboard/amd/padmelon/board_info.txt A src/mainboard/amd/padmelon/bootblock/OemCustomize.c A src/mainboard/amd/padmelon/bootblock/bootblock.c A src/mainboard/amd/padmelon/devicetree.cb A src/mainboard/amd/padmelon/dsdt.asl A src/mainboard/amd/padmelon/fan_init.c A src/mainboard/amd/padmelon/gpio.c A src/mainboard/amd/padmelon/gpio.h A src/mainboard/amd/padmelon/irq_tables.c A src/mainboard/amd/padmelon/mainboard.c A src/mainboard/amd/padmelon/mptable.c A src/mainboard/amd/padmelon/romstage.c 25 files changed, 1,962 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/33993/1 diff --git a/src/mainboard/amd/padmelon/BiosCallOuts.c b/src/mainboard/amd/padmelon/BiosCallOuts.c new file mode 100644 index 0000000..522a63f --- /dev/null +++ b/src/mainboard/amd/padmelon/BiosCallOuts.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <amdblocks/agesawrapper.h> +#include <amdblocks/BiosCallOuts.h> +#include <soc/southbridge.h> +#include <stdlib.h> +#include <string.h> + +void platform_FchParams_env(FCH_DATA_BLOCK *FchParams_env) +{ + +} diff --git a/src/mainboard/amd/padmelon/BiosCallOuts.h b/src/mainboard/amd/padmelon/BiosCallOuts.h new file mode 100644 index 0000000..8c2a047 --- /dev/null +++ b/src/mainboard/amd/padmelon/BiosCallOuts.h @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define FAN_INPUT_INTERNAL_DIODE 0 +#define FAN_INPUT_TEMP0 1 +#define FAN_INPUT_TEMP1 2 +#define FAN_INPUT_TEMP2 3 +#define FAN_INPUT_TEMP3 4 +#define FAN_INPUT_TEMP0_FILTER 5 +#define FAN_INPUT_ZERO 6 +#define FAN_INPUT_DISABLED 7 + +#define FAN_AUTOMODE (1 << 0) +#define FAN_LINEARMODE (1 << 1) +#define FAN_STEPMODE ~(1 << 1) +#define FAN_POLARITY_HIGH (1 << 2) +#define FAN_POLARITY_LOW ~(1 << 2) + +/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */ +#define FREQ_28KHZ 0x0 +#define FREQ_25KHZ 0x1 +#define FREQ_23KHZ 0x2 +#define FREQ_21KHZ 0x3 +#define FREQ_29KHZ 0x4 +#define FREQ_18KHZ 0x5 +#define FREQ_100HZ 0xF7 +#define FREQ_87HZ 0xF8 +#define FREQ_58HZ 0xF9 +#define FREQ_44HZ 0xFA +#define FREQ_35HZ 0xFB +#define FREQ_29HZ 0xFC +#define FREQ_22HZ 0xFD +#define FREQ_14HZ 0xFE +#define FREQ_11HZ 0xFF diff --git a/src/mainboard/amd/padmelon/Kconfig b/src/mainboard/amd/padmelon/Kconfig new file mode 100644 index 0000000..df4f9f1 --- /dev/null +++ b/src/mainboard/amd/padmelon/Kconfig @@ -0,0 +1,76 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015-2018 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +if BOARD_AMD_PADMELON + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y +# select SOC_AMD_MERLINFALCON # missing binaries + select SOC_AMD_STONEYRIDGE_FP4 # alternative version + select BOARD_ROMSIZE_KB_8192 + select DRIVERS_I2C_GENERIC + select DRIVERS_PS2_KEYBOARD + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_ACPI_TABLES + select GFXUMA + select STONEYRIDGE_LEGACY_FREE + select ONBOARD_VGA_IS_PRIMARY + select BOOTBLOCK_CONSOLE + select SUPERIO_FINTEK_F81803A + select SUPERIO_FINTEK_COMMON_PRE_RAM + select SUPERIO_FINTEK_F81803A_FAN_CONTROL + select VGA_BIOS + +config VGA_BIOS_FILE + string + default "3rdparty/blobs/soc/amd/merlinfalcon/VBIOS.bin" + +config MAINBOARD_DIR + string + default amd/padmelon + +config MAINBOARD_PART_NUMBER + string + default "Padmelon" + +config MAX_CPUS + int + default 4 + +config IRQ_SLOT_COUNT + int + default 11 + +config HWM_IO_WINDOW + hex + default 0x0100 + help + Select a bit within LPC_IO_PORT_DECODE_ENABLE that will enable + access to IO port HWM_PORT, which is programmed at bootblock. + +config HWM_PORT + hex + default 0x0225 + help + Oddly enough, HWM base address must be and odd address. Hardware + monitor used addresses are HWM_PORT for index and HWM_PORT + 1 + for data. + +# Don't use AMD's Secure OS +config USE_PSPSECUREOS + def_bool n + +endif # BOARD_AMD_PADMELON diff --git a/src/mainboard/amd/padmelon/Kconfig.name b/src/mainboard/amd/padmelon/Kconfig.name new file mode 100644 index 0000000..fb88c39 --- /dev/null +++ b/src/mainboard/amd/padmelon/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_AMD_PADMELON + bool "Padmelon" diff --git a/src/mainboard/amd/padmelon/Makefile.inc b/src/mainboard/amd/padmelon/Makefile.inc new file mode 100644 index 0000000..aabc221 --- /dev/null +++ b/src/mainboard/amd/padmelon/Makefile.inc @@ -0,0 +1,32 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015-2017 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +bootblock-y += bootblock/bootblock.c +bootblock-y += bootblock/OemCustomize.c +bootblock-y += gpio.c + +romstage-y += BiosCallOuts.c +romstage-y += bootblock/OemCustomize.c +romstage-y += OemCustomize.c + +ramstage-y += BiosCallOuts.c +ramstage-y += gpio.c +ramstage-y += OemCustomize.c +ramstage-$(CONFIG_SUPERIO_FINTEK_F81803A_FAN_CONTROL) += fan_init.c + +CPPFLAGS_common += -I$(src)/vendorcode/amd/pi/00670F00 +CPPFLAGS_common += -I$(src)/vendorcode/amd/pi/00670F00/Proc/Fch/Common +CPPFLAGS_common += -I$(src)/vendorcode/amd/pi/00670F00/Proc/Common +CPPFLAGS_common += -I$(src)/vendorcode/amd/pi/00670F00/binaryPI diff --git a/src/mainboard/amd/padmelon/OemCustomize.c b/src/mainboard/amd/padmelon/OemCustomize.c new file mode 100644 index 0000000..bb92733 --- /dev/null +++ b/src/mainboard/amd/padmelon/OemCustomize.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <chip.h> +#include <amdblocks/agesawrapper.h> + +#define DIMMS_PER_CHANNEL 1 +#if DIMMS_PER_CHANNEL > MAX_DIMMS_PER_CH +#error "Too many DIMM sockets defined for the mainboard" +#endif + +static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = { + DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY), + NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, CHANNEL_A, 1), + NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, CHANNEL_B, 1), + NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, MAX_DRAM_CH), + MOTHER_BOARD_LAYERS(LAYERS_6), + MEMCLK_DIS_MAP(ANY_SOCKET, CHANNEL_A, 0x01, 0x02, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00), + MEMCLK_DIS_MAP(ANY_SOCKET, CHANNEL_B, 0x01, 0x02, 0x08, 0x04, + 0x00, 0x00, 0x00, 0x00), + CKE_TRI_MAP(ANY_SOCKET, CHANNEL_A, 0x01, 0x02, 0x00, 0x00), + CKE_TRI_MAP(ANY_SOCKET, CHANNEL_B, 0x05, 0x0A, 0x00, 0x00), + ODT_TRI_MAP(ANY_SOCKET, CHANNEL_A, 0x01, 0x00, 0x02, 0x00), + ODT_TRI_MAP(ANY_SOCKET, CHANNEL_B, 0x01, 0x04, 0x02, 0x08), + CS_TRI_MAP(ANY_SOCKET, CHANNEL_A, 0x01, 0x02, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00), + CS_TRI_MAP(ANY_SOCKET, CHANNEL_B, 0x01, 0x02, 0x04, 0x08, 0x00, + 0x00, 0x00, 0x00), + PSO_END +}; + +void OemPostParams(AMD_POST_PARAMS *PostParams) +{ + PostParams->MemConfig.PlatformMemoryConfiguration = + (PSO_ENTRY *)DDR4PlatformMemoryConfiguration; + PostParams->MemConfig.CfgUmaAbove4G = TRUE; +} diff --git a/src/mainboard/amd/padmelon/acpi/gpe.asl b/src/mainboard/amd/padmelon/acpi/gpe.asl new file mode 100644 index 0000000..03bbc38 --- /dev/null +++ b/src/mainboard/amd/padmelon/acpi/gpe.asl @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope(\_GPE) { /* Start Scope GPE */ + + /* General event 3 */ + Method(_L03) { + /* DBGO("\\_GPE\\_L03\n") */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Legacy PM event - Power Button */ + Method(_L08) { + /* DBGO("\\_GPE\\_L08\n") */ + \_SB.SIO0.CPSI() /* clear psin state in sio */ + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + /* DBGO("\\_GPE\\_L09\n") */ + /* Notify (\_TZ.TZ00, 0x80) */ + } + + /* USB controller PME# */ + Method(_L0B) { + /* DBGO("\\_GPE\\_L0B\n") */ + Notify(\_SB.PCI0.EHC0, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* ExtEvent0 SCI event */ + Method(_L10) { + /* DBGO("\\_GPE\\_L10\n") */ + } + + /* ExtEvent1 SCI event */ + Method(_L11) { + /* DBGO("\\_GPE\\_L11\n") */ + } + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + /* DBGO("\\_GPE\\_L18\n") */ + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Azalia SCI event */ + Method(_L1B) { + /* DBGO("\\_GPE\\_L1B\n") */ + Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } +} /* End Scope GPE */ diff --git a/src/mainboard/amd/padmelon/acpi/mainboard.asl b/src/mainboard/amd/padmelon/acpi/mainboard.asl new file mode 100644 index 0000000..db5731f --- /dev/null +++ b/src/mainboard/amd/padmelon/acpi/mainboard.asl @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Memory related values */ +Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ +Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ +Name(PBLN, 0x0) /* Length of BIOS area */ + +Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ +Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ +Name(HPBA, 0xFED00000) /* Base address of HPET table */ + +/* Some global data */ +Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ +Name(OSV, Ones) /* Assume nothing */ +Name(PMOD, One) /* Assume APIC */ diff --git a/src/mainboard/amd/padmelon/acpi/routing.asl b/src/mainboard/amd/padmelon/acpi/routing.asl new file mode 100644 index 0000000..37b9613 --- /dev/null +++ b/src/mainboard/amd/padmelon/acpi/routing.asl @@ -0,0 +1,251 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "routing.asl" + } +*/ + +/* Routing is in System Bus scope */ +Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - F15 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + /* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */ + Package(){0x0001FFFF, 0, INTG, 0 }, + Package(){0x0001FFFF, 1, INTH, 0 }, + + + /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */ + Package(){0x0002FFFF, 0, INTH, 0 }, + Package(){0x0002FFFF, 1, INTA, 0 }, + Package(){0x0002FFFF, 2, INTB, 0 }, + Package(){0x0002FFFF, 3, INTC, 0 }, + + Package(){0x0003FFFF, 0, INTH, 0 }, + Package(){0x0003FFFF, 1, INTA, 0 }, + Package(){0x0003FFFF, 2, INTB, 0 }, + Package(){0x0003FFFF, 3, INTC, 0 }, + + Package(){0x0008FFFF, 0, INTG, 0 }, + Package(){0x0008FFFF, 1, INTH, 0 }, + Package(){0x0008FFFF, 2, INTE, 0 }, + Package(){0x0008FFFF, 3, INTF, 0 }, + + /* Bus 0, Dev 9, Func 2 - HDAudio */ + Package(){0x0009FFFF, 0, INTG, 0 }, + Package(){0x0009FFFF, 1, INTH, 0 }, + Package(){0x0009FFFF, 2, INTE, 0 }, + Package(){0x0009FFFF, 3, INTF, 0 }, + + /* FCH devices */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + + /* Bus 0, Dev 18 Func 0 - USB: EHCI */ + Package(){0x0012FFFF, 0, INTC, 0 }, + Package(){0x0012FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 16 Func 0 - USB: xHCI */ + Package(){0x0010FFFF, 0, INTC, 0 }, + Package(){0x0010FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, INTD, 0 }, +}) + +Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - F15 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + Package(){0x0001FFFF, 0, 0, 30 }, + Package(){0x0001FFFF, 1, 0, 31 }, + Package(){0x0001FFFF, 2, 0, 28 }, + Package(){0x0001FFFF, 3, 0, 29 }, + + /* Bus 0, Dev 2 - PCIe Bridges */ + Package(){0x0002FFFF, 0, 0, 47 }, + Package(){0x0002FFFF, 1, 0, 48 }, + Package(){0x0002FFFF, 2, 0, 49 }, + Package(){0x0002FFFF, 3, 0, 50 }, + + Package(){0x0003FFFF, 0, 0, 39 }, + Package(){0x0003FFFF, 1, 0, 40 }, + Package(){0x0003FFFF, 2, 0, 41 }, + Package(){0x0003FFFF, 3, 0, 42 }, + + Package(){0x0008FFFF, 0, 0, 38 }, + Package(){0x0008FFFF, 1, 0, 39 }, + Package(){0x0008FFFF, 2, 0, 36 }, + Package(){0x0008FFFF, 3, 0, 37 }, + + /* Bus 0, Dev 9, Func 2 - HDAudio */ + Package(){0x0009FFFF, 0, 0, 46 }, + Package(){0x0009FFFF, 1, 0, 47 }, + Package(){0x0009FFFF, 2, 0, 44 }, + Package(){0x0009FFFF, 3, 0, 45 }, + + /* SB devices in APIC mode */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, + + /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */ + Package(){0x0012FFFF, 0, 0, 18 }, + Package(){0x0012FFFF, 1, 0, 17 }, + + /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */ + Package(){0x0010FFFF, 0, 0, 18}, + Package(){0x0010FFFF, 1, 0, 17}, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, 0, 19 }, +}) + +Name(PS4, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, 0, 24 }, + Package(){0x0000FFFF, 1, 0, 25 }, + Package(){0x0000FFFF, 2, 0, 26 }, + Package(){0x0000FFFF, 3, 0, 27 }, +}) + +/* GPP 1 */ +Name(PS5, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APS5, Package(){ + Package(){0x0000FFFF, 0, 0, 32 }, + Package(){0x0000FFFF, 1, 0, 33 }, + Package(){0x0000FFFF, 2, 0, 34 }, + Package(){0x0000FFFF, 3, 0, 35 }, +}) + +/* GPP 2 */ +Name(PS6, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APS6, Package(){ + Package(){0x0000FFFF, 0, 0, 40 }, + Package(){0x0000FFFF, 1, 0, 41 }, + Package(){0x0000FFFF, 2, 0, 42 }, + Package(){0x0000FFFF, 3, 0, 43 }, +}) + +/* GPP 3 */ +Name(PS7, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APS7, Package(){ + Package(){0x0000FFFF, 0, 0, 48 }, + Package(){0x0000FFFF, 1, 0, 49 }, + Package(){0x0000FFFF, 2, 0, 50 }, + Package(){0x0000FFFF, 3, 0, 51 }, +}) + +/* GPP 4 */ +Name(PS8, Package(){ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, +}) +Name(APS8, Package(){ + Package(){0x0000FFFF, 0, 0, 27 }, + Package(){0x0000FFFF, 1, 0, 24 }, + Package(){0x0000FFFF, 2, 0, 25 }, + Package(){0x0000FFFF, 3, 0, 26 }, +}) + +Name(PS9, Package(){ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, +}) +Name(APS9, Package(){ + Package(){0x0000FFFF, 0, 0, 35 }, + Package(){0x0000FFFF, 1, 0, 32 }, + Package(){0x0000FFFF, 2, 0, 33 }, + Package(){0x0000FFFF, 3, 0, 34 }, +}) + +/* GFX 2 */ +Name(PSA, Package(){ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, +}) +Name(APSA, Package(){ + Package(){0x0000FFFF, 0, 0, 51 }, + Package(){0x0000FFFF, 1, 0, 48 }, + Package(){0x0000FFFF, 2, 0, 49 }, + Package(){0x0000FFFF, 3, 0, 50 }, +}) + +/* GFX 3 */ +Name(PSB, Package(){ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, +}) +Name(APSB, Package(){ + Package(){0x0000FFFF, 0, 0, 26 }, + Package(){0x0000FFFF, 1, 0, 27 }, + Package(){0x0000FFFF, 2, 0, 24 }, + Package(){0x0000FFFF, 3, 0, 25 }, +}) + +/* GFX 4 */ +Name(PSC, Package(){ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, +}) +Name(APSC, Package(){ + Package(){0x0000FFFF, 0, 0, 34 }, + Package(){0x0000FFFF, 1, 0, 35 }, + Package(){0x0000FFFF, 2, 0, 32 }, + Package(){0x0000FFFF, 3, 0, 33 }, +}) diff --git a/src/mainboard/amd/padmelon/acpi/sleep.asl b/src/mainboard/amd/padmelon/acpi/sleep.asl new file mode 100644 index 0000000..58f0752 --- /dev/null +++ b/src/mainboard/amd/padmelon/acpi/sleep.asl @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Wake status package */ +Name(WKST,Package(){Zero, Zero}) + +/* +* \_PTS - Prepare to Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2, etc +* +* Exit: +* -none- +* +* The _PTS control method is executed at the beginning of the sleep process +* for S1-S5. The sleeping value is passed to the _PTS control method. This +* control method may be executed a relatively long time before entering the +* sleep state and the OS may abort the operation without notification to +* the ACPI driver. This method cannot modify the configuration or power +* state of any device in the system. +*/ +Method(_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Clear wake status structure. */ + Store(0, PEWD) + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + Store(7, UPWS) +} /* End Method(\_PTS) */ + +/* +* \_BFS OEM Back From Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* -none- +*/ +Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ +} + +/* +* \_WAK System Wake method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* Return package of 2 DWords +* Dword 1 - Status +* 0x00000000 wake succeeded +* 0x00000001 Wake was signaled but failed due to lack of power +* 0x00000002 Wake was signaled but failed due to thermal condition +* Dword 2 - Power Supply state +* if non-zero the effective S-state the power supply entered +*/ +Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + + Return(WKST) +} /* End Method(\_WAK) */ diff --git a/src/mainboard/amd/padmelon/acpi/superio.asl b/src/mainboard/amd/padmelon/acpi/superio.asl new file mode 100644 index 0000000..9befcce --- /dev/null +++ b/src/mainboard/amd/padmelon/acpi/superio.asl @@ -0,0 +1,183 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Christoph Grenz <christophg+cb(a)grenz-bonn.de> + * Copyright (C) 2013 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Include this file into a mainboard's DSDT _SB device tree and it will + * expose the W83627DHG SuperIO and some of its functionality. + * + * It allows the change of IO ports, IRQs and DMA settings on logical + * devices, disabling and reenabling logical devices and controlling power + * saving mode on logical devices or the whole chip. + * + * LDN State + * 0x1 UARTA Implemented, partially tested + * 0x2 UARTB UART only, partially tested + * 0x4 HWM Resources, PM only + * 0x5 KBC Implemented, untested + * 0x6 GPIO6 Not implemented + * 0x7 WDT0&PLED Not implemented + * 0x9 GPIO2-5 Not implemented + * 0xa ACPI/PME/ERP Not implemented + * + * Controllable through preprocessor defines: + * SUPERIO_DEV Device identifier for this SIO (e.g. SIO0) + * SUPERIO_PNP_BASE I/o address of the first PnP configuration register + * F81803A_SHOW_UARTA If defined, UARTA will be exposed. + * F81803A_SHOW_UARTB If defined, UARTB will be exposed. + * F81803A_SHOW_KBC If defined, the KBC will be exposed. + * F81803A_SHOW_PS2M If defined, PS/2 mouse support will be exposed. + * F81803A_SHOW_HWMON If defined, the hardware monitor will be exposed. + * F81803A_SHOW_PME If defined, the PME/EARP/ACPI will be exposed. + */ +#undef SUPERIO_DEV +#define SUPERIO_DEV SIO0 +#undef SUPERIO_CHIP_NAME +#define SUPERIO_CHIP_NAME F81803A +#define SUPERIO_PNP_BASE 0x4E +#include <superio/acpi/pnp.asl> + +Device(SUPERIO_DEV) { + Name (_HID, EisaId("PNP0A05")) + Name (_STR, Unicode("Fintek F81803A Super I/O")) + Name (_UID, SUPERIO_UID(SUPERIO_DEV,)) + + /* Mutex for accesses to the configuration ports */ + Mutex(CRMX, 1) + + /* SuperIO configuration ports */ + OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02) + Field (CREG, ByteAcc, NoLock, Preserve) + { + PNP_ADDR_REG, 8, + PNP_DATA_REG, 8 + } + IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve) + { + Offset (0x07), + PNP_LOGICAL_DEVICE, 8, /* Logical device selector */ + + + Offset (0x30), + PNP_DEVICE_ACTIVE, 1, /* Logical device activation */ + + Offset (0x60), + PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */ + PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */ + Offset (0x62), + PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */ + PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */ + + Offset (0x70), + PNP_IRQ0, 8, /* First IRQ */ + + offset(0xFB), + APC5, 8, /* PME ACPI Control Register 5 */ + } + + /* PMx-- registers to get the addresses of the ACPI Registers */ + IndexField(PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve) + { + Offset(0x60), /* AcpiPmEvBlk */ + P1EB, 16, /* AcpiPmEvtBlk */ + P1CB, 16, /* AcpiPm1CntBlk */ + Offset(0xEE), + UPWS, 3, + } + + /* AcpiPmEvtBlk registers*/ + OperationRegion(P1E0, SystemIO, P1EB, 0x04) + Field(P1E0, ByteAcc, Nolock, Preserve) + { + Offset(0x02), /* Pm1Enable */ + , 14, + PEWD, 1, /* bit 1: PciExpWakeDis*/ + } + + + /* AcpiPm1CntBlk registers*/ + OperationRegion(P1C0, SystemIO, P1CB, 0x04) + Field(P1C0, ByteAcc, Nolock, Preserve) + { + Offset(0x00), /* PmControl */ + , 10, + P1ST, 3, /* Bits SlpTyp */ + P1SE, 1, /* SlpTypEn*/ + } + + OperationRegion(APCx, SystemIO, APC5, 0x01) + Field(APCx, ByteAcc, Nolock, Preserve) /* bits in PME ACPI CONTROL Reg 5*/ + { + Offset(0x00), /*Control Reg 5 */ + , 7, + PSIN, 1, /* PSIN_FLAG */ + } + + /* routine to clear PSIN_FLAG in ACPI_CONTROL_REG_5 of SIO */ + Method(CPSI, 0, Serialized) + { + /* DBG0("SIO CPSI")*/ + ENTER_CONFIG_MODE(10) + Store(1, PSIN) + EXIT_CONFIG_MODE() + } + + Method(_CRS) + { + /* Announce the used i/o ports to the OS */ + Return (ResourceTemplate () { + IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02) + }) + } + + #undef PNP_ENTER_MAGIC_1ST + #undef PNP_ENTER_MAGIC_2ND + #undef PNP_ENTER_MAGIC_3RD + #undef PNP_ENTER_MAGIC_4TH + #undef PNP_EXIT_MAGIC_1ST + #undef PNP_EXIT_SPECIAL_REG + #undef PNP_EXIT_SPECIAL_VAL + #define PNP_ENTER_MAGIC_1ST 0x87 + #define PNP_ENTER_MAGIC_2ND 0x87 + #define PNP_EXIT_MAGIC_1ST 0xaa + #include <superio/acpi/pnp_config.asl> + +#ifdef F81803A_SHOW_UARTA + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_DDN + #undef SUPERIO_UART_PM_REG + #undef SUPERIO_UART_PM_VAL + #undef SUPERIO_UART_PM_LDN + #define SUPERIO_UART_LDN 1 + #define SUPERIO_UART_PM_REG UAPW + #define SUPERIO_UART_PM_VAL 0 + #define SUPERIO_UART_PM_LDN PNP_NO_LDN_CHANGE + #include <superio/acpi/pnp_uart.asl> +#endif + +#ifdef F81803A_SHOW_UARTB + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_DDN + #undef SUPERIO_UART_PM_REG + #undef SUPERIO_UART_PM_VAL + #undef SUPERIO_UART_PM_LDN + #define SUPERIO_UART_LDN 2 + #define SUPERIO_UART_PM_REG UBPW + #define SUPERIO_UART_PM_VAL 0 + #define SUPERIO_UART_PM_LDN PNP_NO_LDN_CHANGE + #include <superio/acpi/pnp_uart.asl> +#endif + +} diff --git a/src/mainboard/amd/padmelon/acpi/usb_oc.asl b/src/mainboard/amd/padmelon/acpi/usb_oc.asl new file mode 100644 index 0000000..9566bc4 --- /dev/null +++ b/src/mainboard/amd/padmelon/acpi/usb_oc.asl @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* simple name description */ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "usb.asl" + } +*/ + +/* USB overcurrent mapping pins. */ +Name(UOM0, 0) +Name(UOM1, 2) +Name(UOM2, 0) +Name(UOM3, 7) +Name(UOM4, 2) +Name(UOM5, 2) +Name(UOM6, 6) +Name(UOM7, 2) +Name(UOM8, 6) +Name(UOM9, 6) + +/* USB Overcurrent GPEs */ +/* TODO: Update for Gardenia */ diff --git a/src/mainboard/amd/padmelon/acpi_tables.c b/src/mainboard/amd/padmelon/acpi_tables.c new file mode 100644 index 0000000..8d4d1cf --- /dev/null +++ b/src/mainboard/amd/padmelon/acpi_tables.c @@ -0,0 +1,14 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Blank file required by build system assumptions of this file being present. + */ diff --git a/src/mainboard/amd/padmelon/board_info.txt b/src/mainboard/amd/padmelon/board_info.txt new file mode 100644 index 0000000..b351b8e --- /dev/null +++ b/src/mainboard/amd/padmelon/board_info.txt @@ -0,0 +1 @@ +Category: eval diff --git a/src/mainboard/amd/padmelon/bootblock/OemCustomize.c b/src/mainboard/amd/padmelon/bootblock/OemCustomize.c new file mode 100644 index 0000000..5d82988 --- /dev/null +++ b/src/mainboard/amd/padmelon/bootblock/OemCustomize.c @@ -0,0 +1,192 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <amdblocks/agesawrapper.h> + +#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE + +static const PCIe_PORT_DESCRIPTOR PortList[] = { + /* + * Init Port descriptor (PCIe port, Lanes 8-15, + * PCI Device Number 3, ...) + */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 15), + PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, + 3, 1, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x02, 0) + }, + + /* + * Initialize Port descriptor (PCIe port, Lane 7, + * PCI Device Number 2, ...) + */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7), + PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, + 2, 5, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x03, 0) + }, + /* + * Initialize Port descriptor (PCIe port, Lane 6, + * PCI Device Number 2, ...) + */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6), + PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, + 2, 4, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x04, 0) + }, + /* + * Initialize Port descriptor (PCIe port, Lane 5, + * PCI Device Number 2, ...) + */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 5, 5), + PCIE_PORT_DATA_INITIALIZER_V2(PortDisabled, ChannelTypeExt6db, + 2, 3, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x04, 0) + }, + /* + * Initialize Port descriptor (PCIe port, Lane4, + * PCI Device Number 2, ...) + */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4), + PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, + 2, 2, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x06, 0) + }, + /* + * Initialize Port descriptor (PCIe port, Lanes 0-3, + * PCI Device Number 2, ...) + */ + { + /* + * Descriptor flags !!!IMPORTANT!!! Terminate last element + * of array + */ + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 0, 3), + PCIE_PORT_DATA_INITIALIZER_V2(PortDisabled, ChannelTypeExt6db, + 2, 1, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x07, 0) + }, + +}; + + +static const PCIe_DDI_DESCRIPTOR DdiList[] = { + /* DP0 */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1) + }, + /* DP1 */ + { + 0, /*DESCRIPTOR_TERMINATE_LIST, */ + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 20, 23), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2) + }, + /* DP2 */ + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux3, Hdp3) + }, +}; + +static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { + .Flags = DESCRIPTOR_TERMINATE_LIST, + .SocketId = 0, + .PciePortList = (void *)PortList, + .DdiLinkList = (void *)DdiList +}; + +static const UINT32 AzaliaCodecAlc286Table[] = { + 0x00172051, 0x001721C7, 0x00172222, 0x00172310, + 0x0017FF00, 0x0017FF00, 0x0017FF00, 0x0017FF00, + 0x01271C50, 0x01271D01, 0x01271EA6, 0x01271FB7, + 0x01371C00, 0x01371D00, 0x01371E00, 0x01371F40, + 0x01471C10, 0x01471D01, 0x01471E17, 0x01471F90, + 0x01771CF0, 0x01771D11, 0x01771E11, 0x01771F41, + 0x01871C40, 0x01871D10, 0x01871EA1, 0x01871F04, + 0x01971CF0, 0x01971D11, 0x01971E11, 0x01971F41, + 0x01A71CF0, 0x01A71D11, 0x01A71E11, 0x01A71F41, + 0x01D71C2D, 0x01D71DA5, 0x01D71E67, 0x01D71F40, + 0x01E71C30, 0x01E71D11, 0x01E71E45, 0x01E71F04, + 0x02171C20, 0x02171D10, 0x02171E21, 0x02171F04, + 0x02050071, 0x02040014, 0x02050010, 0x02040C22, + 0x0205004F, 0x0204B029, 0x0205002B, 0x02040C50, + 0x0205002D, 0x02041020, 0x02050020, 0x02040000, + 0x02050019, 0x02040817, 0x02050035, 0x02041AA5, + 0x02050063, 0x02042906, 0x02050063, 0x02042906, + 0xffffffff +}; + +static CONST CODEC_VERB_TABLE_LIST CodecTableList[] = { + { 0x10ec0286, AzaliaCodecAlc286Table}, + { 0x10ec0288, AzaliaCodecAlc286Table}, + { 0x10ec0888, AzaliaCodecAlc286Table}, + { 0x0FFFFFFFF, (void *)0x0FFFFFFFF} +}; + +/*---------------------------------------------------------------------------*/ +/** + * OemCustomizeInitEarly + * + * Description: + * This is the stub function will call the host environment through the + * binary block interface (call-out port) to provide a user hook opportunity. + * + * Parameters: + * @param[in] **PeiServices + * @param[in] *InitEarly + * + * @retval VOID + * + **/ +/*---------------------------------------------------------------------------*/ +VOID OemCustomizeInitEarly(AMD_EARLY_PARAMS *InitEarly) +{ + InitEarly->GnbConfig.PcieComplexList = (void *)&PcieComplex; + InitEarly->PlatformConfig.AzaliaCodecVerbTable = + (uint64_t)(uintptr_t)CodecTableList; + InitEarly->PlatformConfig.AzaliaSsid = 0x157A1022ul; +} diff --git a/src/mainboard/amd/padmelon/bootblock/bootblock.c b/src/mainboard/amd/padmelon/bootblock/bootblock.c new file mode 100644 index 0000000..3ef34d3 --- /dev/null +++ b/src/mainboard/amd/padmelon/bootblock/bootblock.c @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017-2018 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <soc/southbridge.h> +#include <amdblocks/lpc.h> +#include <superio/fintek/common/fintek.h> +#include <superio/fintek/f81803a/f81803a.h> +#include <device/pci.h> +#include <device/pci_ops.h> +#include <soc/pci_devs.h> + +#include "../gpio.h" + +#define SERIAL_DEV PNP_DEV(0x4e, F81803A_SP1) + +/* Enable UAT control pins, assuming base address 0x03f8 */ +static void full_serial(void) +{ + u32 temp; + u8 reg; + temp = pci_read_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE); + temp |= DECODE_ENABLE_SERIAL_PORT0; + pci_write_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE, temp); + reg = inb(0x3fb); + reg |= 3; + outb(reg, 0x3fb); + reg = inb(0x3fc); + reg |= 3; + outb(reg, 0x3fc); +} + +void bootblock_mainboard_early_init(void) +{ + sb_clk_output_48Mhz(2); + /* + * UART enabled by default at reset, just need control pins such as + * RTS, CTS, etc... + */ + full_serial(); +} + +void bootblock_mainboard_init(void) +{ + size_t num_gpios; + const struct soc_amd_gpio *gpios; + + gpios = early_gpio_table(&num_gpios); + program_gpios(gpios, num_gpios); +} diff --git a/src/mainboard/amd/padmelon/devicetree.cb b/src/mainboard/amd/padmelon/devicetree.cb new file mode 100644 index 0000000..c6df430 --- /dev/null +++ b/src/mainboard/amd/padmelon/devicetree.cb @@ -0,0 +1,80 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015-2017 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +chip soc/amd/stoneyridge + + register "spd_addr_lookup" = " + { + { {0xA0, 0x00} }, // socket 0 - Channel 0, slot 0 + }" + + register "uma_mode" = "UMAMODE_AUTO_LEGACY" + #register "uma_size" = "512 * MiB" + + device cpu_cluster 0 on + device lapic 10 on end + end + + device domain 0 on + subsystemid 0x1022 0x1410 inherit + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x9874 + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 on end # No x4 PCIe slot + device pci 2.2 on end # Half mPCIe slot + device pci 2.3 on end # NC + device pci 2.4 on end # RTL8111F + device pci 3.0 on end # PCIe Host Bridge + device pci 8.0 on end # PSP + device pci 9.0 on end # HDA + device pci 9.2 on end # HDA + device pci 10.0 on end # USB + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + end # SM + device pci 14.3 on # LPC 0x439d + chip superio/fintek/f81803a + register "conf_key_mode" = "0x77" + device pnp 4e.1 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.2 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 4e.4 off end # HWM + device pnp 4e.5 off end # KBC + device pnp 4e.6 off end # GPIO + device pnp 4e.7 off end # WDT + device pnp 4e.a on end # PME + end # f81803a + end # LPC + device pci 14.7 on end # SD + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + end #domain +end #soc/amd/stoneyridge diff --git a/src/mainboard/amd/padmelon/dsdt.asl b/src/mainboard/amd/padmelon/dsdt.asl new file mode 100644 index 0000000..e4d89b1 --- /dev/null +++ b/src/mainboard/amd/padmelon/dsdt.asl @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* DefinitionBlock Statement */ +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "AMD ", /* OEMID */ + "COREBOOT", /* TABLE ID */ + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include <arch/x86/acpi/debug.asl> */ /* as needed */ + + /* global NVS and variables */ + #include <globalnvs.asl> + + /* Globals for the platform */ + #include "acpi/mainboard.asl" + + /* Describe the USB Overcurrent pins */ + #include "acpi/usb_oc.asl" + + /* PCI IRQ mapping for the Southbridge */ + #include <pcie.asl> + + /* Describe the processor tree (\_PR) */ + #include <cpu.asl> + + /* Contains the supported sleep states for this chipset */ + #include <sleepstates.asl> + + /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ + #include "acpi/sleep.asl" + + /* System Bus */ + Scope(\_SB) { /* Start \_SB scope */ + /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> + + /* IRQ Routing mapping for this platform (in \_SB scope) */ + #include "acpi/routing.asl" + + Device(PWRB) { + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) + Name(_STA, 0x0B) + } + + /* Describe the SOC */ + #include <soc.asl> + + /* Describe the Fintek F81803A SIO */ + #include <superio/fintek/f81803a/acpi/superio.asl> + + } /* End \_SB scope */ + + /* Define the General Purpose Events for the platform */ + #include "acpi/gpe.asl" +} +/* End of ASL file */ diff --git a/src/mainboard/amd/padmelon/fan_init.c b/src/mainboard/amd/padmelon/fan_init.c new file mode 100644 index 0000000..0675dc4 --- /dev/null +++ b/src/mainboard/amd/padmelon/fan_init.c @@ -0,0 +1,151 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Richard Spiegel <richard.spiegel(a)silverbackltd.com> + * Copyright (C) 2019 Silverback ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <bootstate.h> +#include <device/pci_ops.h> +#include <amdblocks/lpc.h> +#include <superio/fintek/common/fan_control.h> +#include <soc/southbridge.h> +#include <soc/pci_devs.h> + +#define CPU_FAN 1 +#define SYSTEM_FAN 2 + +/* Boundaries in celcius, sections in percent */ +u8 cpu_boudaries[] = { + 80, + 65, + 50, + 35 +}; + +u8 system_boudaries[] = { + 70, + 55, + 40, + 25 +}; + +u8 cpu_section[] = { + 100, + 85, + 70, + 55, + 40 +}; + +u8 system_section[] = { + 100, + 85, + 70, + 55, + 40 +}; + +static int check_status(const char *name, int status) +{ + if (status != HWM_STATUS_SUCCESS) + printk(BIOS_DEBUG, "%s returned %d\n", name, status); + if (status < HWM_STATUS_SUCCESS) + return status; + return HWM_STATUS_SUCCESS; /* positive values are warnings only */ +} + +static void set_fan(uint8_t fan, external_sensor sensor, temp_sensor_type stype, + fan_temp_source temp_source, fan_type ftype, + fan_mode fmode, fan_pwm_freq fan_freq, + fan_rate_up rate_up, fan_rate_down rate_down, + u8 *boundaries, u8 *sections) +{ + int s; + printk(BIOS_DEBUG, "Set sensor type\n"); + if (sensor != IGNORE_SENSOR) { + s = set_sensor_type(CONFIG_HWM_PORT, sensor, stype); + if (check_status("set_sensor_type", s) < HWM_STATUS_SUCCESS) + return; + } + + printk(BIOS_DEBUG, "Set temperature source\n"); + s = set_fan_temperature_source(CONFIG_HWM_PORT, fan, temp_source); + if (check_status("set_fan_temperature_source", s) < HWM_STATUS_SUCCESS) + return; + + printk(BIOS_DEBUG, "Set fan type mode\n"); + s = set_fan_type_mode(CONFIG_HWM_PORT, fan, ftype, fmode); + if (check_status("fan_type_mode", s) < HWM_STATUS_SUCCESS) + return; + + printk(BIOS_DEBUG, "Set PWM frequency\n"); + s = set_pwm_frequency(CONFIG_HWM_PORT, fan, fan_freq); + if (check_status("set_pwm_frequency", s) < HWM_STATUS_SUCCESS) + return; + + printk(BIOS_DEBUG, "Set fan speed change rate\n"); + s = set_fan_speed_change_rate(CONFIG_HWM_PORT, fan, rate_up, rate_down); + if (check_status("set_fan_speed_change_rate", s) < HWM_STATUS_SUCCESS) + return; + + printk(BIOS_DEBUG, "Set sections\n"); + s = set_sections(CONFIG_HWM_PORT, fan, boundaries, sections); + printk(BIOS_DEBUG, "set_sections returned %d\n", s); + if (check_status("set_sections", s) < HWM_STATUS_SUCCESS) + return; + + printk(BIOS_DEBUG, "Fan %d completed\n", fan); +} + +/* Todo - move this code to SIO */ +static void init_hwm(void) +{ + outb(0x87, 0x4e); + outb(0x87, 0x4e); + outb(0x7, 0x4e); + outb(4, 0x4f); + outb(0x60, 0x4e); + outb(2, 0x4f); + outb(0x61, 0x4e); + outb(0x20, 0x4f); + outb(0x30, 0x4e); + outb(1, 0x4f); + outb(0xaa, 0x4e); +} + +static void init_fan_control(void *unused) +{ + uint32_t reg, t; + + init_hwm(); + /* Open a LPC window to access the hardware monitor */ + reg = pci_read_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE); + t = reg | CONFIG_HWM_IO_WINDOW; + pci_write_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE, t); + + set_fan(CPU_FAN, IGNORE_SENSOR, TEMP_SENSOR_DEFAULT, + FAN_TEMP_TSI, FAN_TYPE_PWM_PUSH_PULL, FAN_MODE_DEFAULT, + FAN_PWM_FREQ_23500, FAN_UP_RATE_10HZ, FAN_DOWN_RATE_10HZ, + cpu_boudaries, cpu_section); + + set_fan(SYSTEM_FAN, EXTERNAL_SENSOR2, TEMP_SENSOR_BJT, + FAN_TEMP_EXTERNAL_2, FAN_TYPE_DAC_POWER, FAN_MODE_DEFAULT, + FAN_PWM_FREQ_23500, FAN_UP_RATE_10HZ, FAN_DOWN_RATE_10HZ, + system_boudaries, system_section); + + /* restore register */ + pci_write_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE, reg); +} + +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, init_fan_control, NULL); diff --git a/src/mainboard/amd/padmelon/gpio.c b/src/mainboard/amd/padmelon/gpio.c new file mode 100644 index 0000000..88d2925 --- /dev/null +++ b/src/mainboard/amd/padmelon/gpio.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <amdblocks/agesawrapper.h> +#include <amdblocks/BiosCallOuts.h> +#include <soc/southbridge.h> +#include <stdlib.h> +#include <soc/gpio.h> + +#include "gpio.h" + +/* + * As a rule of thumb, GPIO pins used by coreboot should be initialized at + * bootblock while GPIO pins used only by the OS should be initialized at + * ramstage. + */ +const struct soc_amd_gpio gpio_set_stage_reset[] = { + /* NFC PU */ + PAD_GPO(GPIO_64, HIGH), + /* PCIe presence detect */ + PAD_GPO(GPIO_64, HIGH), + /* MUX for Power Express Eval */ + PAD_GPI(GPIO_116, PULL_DOWN), + /* SD power */ + PAD_GPO(GPIO_64, HIGH), +}; + +const struct soc_amd_gpio gpio_set_stage_ram[] = { + /* BT radio disable */ + PAD_GPO(GPIO_14, HIGH), + /* NFC wake */ + PAD_GPO(GPIO_65, HIGH), + /* Webcam */ + PAD_GPO(GPIO_66, HIGH), + /* GPS sleep */ + PAD_GPO(GPIO_70, HIGH), +}; + +const struct soc_amd_gpio *early_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(gpio_set_stage_reset); + return gpio_set_stage_reset; +} + +const struct soc_amd_gpio *gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(gpio_set_stage_ram); + return gpio_set_stage_ram; +} diff --git a/src/mainboard/amd/padmelon/gpio.h b/src/mainboard/amd/padmelon/gpio.h new file mode 100644 index 0000000..1d3a8a2 --- /dev/null +++ b/src/mainboard/amd/padmelon/gpio.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +const struct soc_amd_gpio *early_gpio_table(size_t *size); +const struct soc_amd_gpio *gpio_table(size_t *size); + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/amd/padmelon/irq_tables.c b/src/mainboard/amd/padmelon/irq_tables.c new file mode 100644 index 0000000..31cfbc1 --- /dev/null +++ b/src/mainboard/amd/padmelon/irq_tables.c @@ -0,0 +1,100 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#include <arch/pirq_routing.h> + +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + u32 slot_num; + u8 *v; + + u8 sum = 0; + int i; + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be between 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (u8 *) (addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x1002; + pirq->rtr_device = 0x4384; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + + /* pci bridge */ + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), + 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, + 0); + pirq_info++; + + slot_num++; + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) + pirq->checksum = sum; + + printk(BIOS_INFO, "%s done.\n", __func__); + + return (unsigned long)pirq_info; +} diff --git a/src/mainboard/amd/padmelon/mainboard.c b/src/mainboard/amd/padmelon/mainboard.c new file mode 100644 index 0000000..11cf6b0 --- /dev/null +++ b/src/mainboard/amd/padmelon/mainboard.c @@ -0,0 +1,132 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <arch/acpi.h> +#include <amdblocks/agesawrapper.h> +#include <amdblocks/amd_pci_util.h> +#include <soc/pci_devs.h> +#include <soc/southbridge.h> + +#include "gpio.h" + +/*********************************************************** + * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. + * This table is responsible for physically routing the PIC and + * IOAPIC IRQs to the different PCI devices on the system. It + * is read and written via registers 0xC00/0xC01 as an + * Index/Data pair. These values are chipset and mainboard + * dependent and should be updated accordingly. + * + * These values are used by the PCI configuration space, + * MP Tables. TODO: Make ACPI use these values too. + */ +const u8 mainboard_picr_data[] = { + [0x00] = 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F, + [0x08] = 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + [0x10] = 0x1F, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x1F, + [0x18] = 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, + [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x30] = 0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05, + [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x40] = 0x04, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x50] = 0x03, 0x04, 0x05, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, + [0x58] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + [0x60] = 0x1F, 0x1F, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + [0x68] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F, + [0x78] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, +}; + +const u8 mainboard_intr_data[] = { + [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x1F, 0x1F, 0x10, + [0x18] = 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, + [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, + [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x40] = 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x50] = 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, + [0x58] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x60] = 0x1F, 0x1F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x68] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F, + [0x78] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; + +/* + * This table defines the index into the picr/intr_data tables for each + * device. Any enabled device and slot that uses hardware interrupts should + * have an entry in this table to define its index into the FCH PCI_INTR + * register 0xC00/0xC01. This index will define the interrupt that it should + * use. Putting PIRQ_A into the PIN A index for a device will tell that + * device to use PIC IRQ 10 if it uses PIN A for its hardware INT. + */ +static const struct pirq_struct mainboard_pirq_data[] = { + { GFX_DEVFN, { PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, + { HDA0_DEVFN, { PIRQ_NC, PIRQ_HDA, PIRQ_NC, PIRQ_NC } }, + { PCIE0_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, + { PCIE1_DEVFN, { PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A } }, + { PCIE2_DEVFN, { PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B } }, + { PCIE3_DEVFN, { PIRQ_D, PIRQ_A, PIRQ_B, PIRQ_C } }, + { PCIE4_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, + { PSP_DEVFN, { PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, + { HDA1_DEVFN, { PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, + { SD_DEVFN, { PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, + { SMBUS_DEVFN, { PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, + { SATA_DEVFN, { PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, + { EHCI1_DEVFN, { PIRQ_EHCI, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, + { XHCI_DEVFN, { PIRQ_XHCI, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, +}; + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + pirq_data_ptr = mainboard_pirq_data; + pirq_data_size = ARRAY_SIZE(mainboard_pirq_data); + intr_data_ptr = mainboard_intr_data; + picr_data_ptr = mainboard_picr_data; +} + +static void mainboard_init(void *chip_info) +{ + size_t num_gpios; + const struct soc_amd_gpio *gpios; + gpios = gpio_table(&num_gpios); + program_gpios(gpios, num_gpios); +} + +/************************************************* + * enable the dedicated function in padmelon board. + *************************************************/ +static void padmelon_enable(struct device *dev) +{ + printk(BIOS_INFO, "Mainboard " + CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + + /* Initialize the PIRQ data structures for consumption */ + pirq_setup(); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, + .enable_dev = padmelon_enable, +}; diff --git a/src/mainboard/amd/padmelon/mptable.c b/src/mainboard/amd/padmelon/mptable.c new file mode 100644 index 0000000..63f17f2 --- /dev/null +++ b/src/mainboard/amd/padmelon/mptable.c @@ -0,0 +1,165 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <arch/io.h> +#include <arch/ioapic.h> +#include <string.h> +#include <stdint.h> +#include <arch/cpu.h> +#include <cpu/x86/lapic.h> +#include <soc/southbridge.h> +#include <amdblocks/amd_pci_util.h> + +static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) +{ + mc->mpc_length += length; + mc->mpc_entry_count++; +} + +static void my_smp_write_bus(struct mp_config_table *mc, + unsigned char id, const char *bustype) +{ + struct mpc_config_bus *mpc; + mpc = smp_next_mpc_entry(mc); + memset(mpc, '\0', sizeof(*mpc)); + mpc->mpc_type = MP_BUS; + mpc->mpc_busid = id; + memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); + smp_add_mpc_entry(mc, sizeof(*mpc)); +} + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + + /* + * By the time this function gets called, the IOAPIC registers + * have been written so they can be read to get the correct + * APIC ID and Version + */ + u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); + u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LOCAL_APIC_ADDR); + memcpy(mc->mpc_oem, "AMD ", 8); + + smp_write_processors(mc); + + my_smp_write_bus(mc, 0, "PCI "); + my_smp_write_bus(mc, 1, "PCI "); + bus_isa = 0x02; + my_smp_write_bus(mc, bus_isa, "ISA "); + + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); + + smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000); + + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), \ + MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, \ + (intr), (apicid), (pin)) + mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); + + /* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ +#define PCI_INT(bus, dev, int_sign, pin) \ + smp_write_intsrc(mc, mp_INT, \ + MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), \ + (((dev)<<2)|(int_sign)), ioapic_id, (pin)) + + /* Internal VGA */ + PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); + PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); + + /* SMBUS */ + PCI_INT(0x0, 0x14, 0x0, 0x10); + + /* HD Audio */ + PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); + + /* USB */ + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); + PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); + PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); + PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); + PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); + PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); + + /* sata */ + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); + + /* on board NIC & Slot PCIE. */ + + /* PCI slots */ + struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + if (dev && dev->enabled) { + u8 bus_pci = dev->link_list->secondary; + /* PCI_SLOT 0. */ + PCI_INT(bus_pci, 0x5, 0x0, 0x14); + PCI_INT(bus_pci, 0x5, 0x1, 0x15); + PCI_INT(bus_pci, 0x5, 0x2, 0x16); + PCI_INT(bus_pci, 0x5, 0x3, 0x17); + + /* PCI_SLOT 1. */ + PCI_INT(bus_pci, 0x6, 0x0, 0x15); + PCI_INT(bus_pci, 0x6, 0x1, 0x16); + PCI_INT(bus_pci, 0x6, 0x2, 0x17); + PCI_INT(bus_pci, 0x6, 0x3, 0x14); + + /* PCI_SLOT 2. */ + PCI_INT(bus_pci, 0x7, 0x0, 0x16); + PCI_INT(bus_pci, 0x7, 0x1, 0x17); + PCI_INT(bus_pci, 0x7, 0x2, 0x14); + PCI_INT(bus_pci, 0x7, 0x3, 0x15); + } + + /* PCIe Lan*/ + PCI_INT(0x0, 0x06, 0x0, 0x13); + + /* FCH PCIe PortA */ + PCI_INT(0x0, 0x15, 0x0, 0x10); + /* FCH PCIe PortB */ + PCI_INT(0x0, 0x15, 0x1, 0x11); + /* FCH PCIe PortC */ + PCI_INT(0x0, 0x15, 0x2, 0x12); + /* FCH PCIe PortD */ + PCI_INT(0x0, 0x15, 0x3, 0x13); + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/amd/padmelon/romstage.c b/src/mainboard/amd/padmelon/romstage.c new file mode 100644 index 0000000..644c7cc --- /dev/null +++ b/src/mainboard/amd/padmelon/romstage.c @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ -- To view, visit https://review.coreboot.org/c/coreboot/+/33993 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a366ddeb4cfebd177a8744f6edb87aecd4787dd Gerrit-Change-Number: 33993 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: newchange

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coreboot-gerrit August 2019