coreboot-gerrit August 2019

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Change in coreboot[master]: Makefile: Turn off SSE instructions for x86_32 architecture
by Kyösti Mälkki (Code Review) 06 Aug '19

06 Aug '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32887 ) Change subject: Makefile: Turn off SSE instructions for x86_32 architecture ...................................................................... Patch Set 5: Please abandon, we merged alternative solution. -- To view, visit https://review.coreboot.org/c/coreboot/+/32887 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia9e86900004a285e9a21a300894624b128e6b4d0 Gerrit-Change-Number: 32887 Gerrit-PatchSet: 5 Gerrit-Owner: Alan Green <avg(a)google.com> Gerrit-Reviewer: Alan Green <avg(a)google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Tue, 06 Aug 2019 17:18:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Kconfig: remove CAR global migration when ramstage stage is used
by Subrata Banik (Code Review) 06 Aug '19

06 Aug '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34750 ) Change subject: Kconfig: remove CAR global migration when ramstage stage is used ...................................................................... Kconfig: remove CAR global migration when ramstage stage is used When a platform is not using postcar stage (!HAVE_POSTCAR) it will use ramstage hence it's by definition not tearing down cache-as-ram from within romstage prior to loading ramstage. Because of this property there's no need to migrate CAR_GLOBAL variables to cbmem. Change-Id: I9bd9c53ca2404b66445d4c558e1a4b151bc2fe41 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/34750/1 diff --git a/src/Kconfig b/src/Kconfig index 2bb5bfe..62c2f0d 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1208,3 +1208,4 @@ bool default n if RAMPAYLOAD default y + select NO_CAR_GLOBAL_MIGRATION if !HAVE_POSTCAR -- To view, visit https://review.coreboot.org/c/coreboot/+/34750 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9bd9c53ca2404b66445d4c558e1a4b151bc2fe41 Gerrit-Change-Number: 34750 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common: Implement MAINBOARD_POWER_STATE_PREVIOUS
by build bot (Jenkins) (Code Review) 06 Aug '19

06 Aug '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34728 ) Change subject: soc/intel/common: Implement MAINBOARD_POWER_STATE_PREVIOUS ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/34728/3/src/soc/intel/common/block… File src/soc/intel/common/block/include/intelblocks/pmclib.h: https://review.coreboot.org/c/coreboot/+/34728/3/src/soc/intel/common/block… PS3, Line 227: void pmc_set_power_failure_state(pci_devfn_t, bool target_on); function definition argument 'pci_devfn_t' should also have an identifier name -- To view, visit https://review.coreboot.org/c/coreboot/+/34728 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22bd71e4f3b67309c1aa0cb6faeb5959521bf656 Gerrit-Change-Number: 34728 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Aug 2019 12:19:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/mainboard/up/squared: Add Support for iTPM
by Christian Walter (Code Review) 06 Aug '19

06 Aug '19

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34443 ) Change subject: src/mainboard/up/squared: Add Support for iTPM ...................................................................... src/mainboard/up/squared: Add Support for iTPM Add Support for the integrated TPM in KConfig and update Device Tree. Change-Id: I3a51545c493674aeed9aef72db24f77315d033ce Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- M src/mainboard/up/squared/Kconfig M src/mainboard/up/squared/devicetree.cb 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/34443/1 diff --git a/src/mainboard/up/squared/Kconfig b/src/mainboard/up/squared/Kconfig index b9f5b27..59bd2ce 100644 --- a/src/mainboard/up/squared/Kconfig +++ b/src/mainboard/up/squared/Kconfig @@ -13,6 +13,7 @@ select BOARD_ROMSIZE_KB_16384 select ONBOARD_VGA_IS_PRIMARY select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_CRB_TPM config VBOOT select VBOOT_NO_BOARD_SUPPORT diff --git a/src/mainboard/up/squared/devicetree.cb b/src/mainboard/up/squared/devicetree.cb index 2a49db6..66be75c 100644 --- a/src/mainboard/up/squared/devicetree.cb +++ b/src/mainboard/up/squared/devicetree.cb @@ -49,4 +49,7 @@ device pci 1f.0 on end # - LPC device pci 1f.1 on end # - SMBUS end + chip drivers/crb + device mmio 0xfed40000 on end + end end -- To view, visit https://review.coreboot.org/c/coreboot/+/34443 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a51545c493674aeed9aef72db24f77315d033ce Gerrit-Change-Number: 34443 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/arch/x86/acpi.c: Change TPM ACPI Table to support CRB
by Christian Walter (Code Review) 06 Aug '19

06 Aug '19

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34333 ) Change subject: src/arch/x86/acpi.c: Change TPM ACPI Table to support CRB ...................................................................... src/arch/x86/acpi.c: Change TPM ACPI Table to support CRB Change the TPM ACPI Table to support CRB Interface when selected. Change-Id: Ide3af348fd4676f2d04e1d0b9ad83f9124e09dcc Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- M src/arch/x86/acpi.c 1 file changed, 8 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/34333/1 diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 8ab993e..18c517a 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -386,10 +386,14 @@ /* Hard to detect for coreboot. Just set it to 0 */ tpm2->platform_class = 0; - /* Must be set to 0 for TIS interface support */ - tpm2->control_area = 0; - /* coreboot only supports the TIS interface driver. */ - tpm2->start_method = 6; + if (CONFIG(CRB_TPM)) { + tpm2->control_area = 0xfed40000; + tpm2->start_method = 7; + } else { + /* Must be set to 0 for TIS interface support */ + tpm2->control_area = 0; + tpm2->start_method = 6; + } memset(tpm2->msp, 0, sizeof(tpm2->msp)); /* Fill the log area size and start address fields. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/34333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide3af348fd4676f2d04e1d0b9ad83f9124e09dcc Gerrit-Change-Number: 34333 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/security/tpm/tss: Add Support for PTT
by Christian Walter (Code Review) 06 Aug '19

06 Aug '19

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34381 ) Change subject: src/security/tpm/tss: Add Support for PTT ...................................................................... src/security/tpm/tss: Add Support for PTT When we use Intel Platform Trust Technologies, we need to verify that the enable bit is set before we use the integrated TPM Change-Id: I3b262a5d5253648fb96fb1fd9ba3995f92755bb1 Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- M src/security/tpm/tss/tcg-2.0/tss.c 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/34381/1 diff --git a/src/security/tpm/tss/tcg-2.0/tss.c b/src/security/tpm/tss/tcg-2.0/tss.c index c4b5538..5cba43d 100644 --- a/src/security/tpm/tss/tcg-2.0/tss.c +++ b/src/security/tpm/tss/tcg-2.0/tss.c @@ -11,6 +11,7 @@ #include <vb2_api.h> #include <security/tpm/tis.h> #include <security/tpm/tss.h> +#include <drivers/ptt/ptt.h> #include "tss_structures.h" #include "tss_marshaling.h" @@ -190,6 +191,13 @@ printk(BIOS_ERR, "%s: tis_open returned error\n", __func__); return VB2_ERROR_UNKNOWN; } + if (CONFIG(INTEL_PTT)) { + if (ptt_active()) { + printk(BIOS_ERR, "%s: Intel PTT is not active.\n", __func__); + return VB2_ERROR_UNKNOWN; + } + printk(BIOS_SPEW, "%s: Intel PTT is active.\n", __func__); + } car_set_var(tlcl_init_done, 1); -- To view, visit https://review.coreboot.org/c/coreboot/+/34381 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b262a5d5253648fb96fb1fd9ba3995f92755bb1 Gerrit-Change-Number: 34381 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: tegra210: Increased size of verstage due to overflow
by Christian Walter (Code Review) 06 Aug '19

06 Aug '19

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34640 ) Change subject: tegra210: Increased size of verstage due to overflow ...................................................................... tegra210: Increased size of verstage due to overflow When imlpementing chagnes in VBOOT, within the build process, tegra210 overflows into the romstage. Reduced the size of Romstage from 104 to 100 and increase the size from verstage from 66 to 70. Change-Id: Ie00498838a644a6f92881db85833dd0a94b87f53 Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- M src/soc/nvidia/tegra210/include/soc/memlayout.ld 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/34640/1 diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout.ld b/src/soc/nvidia/tegra210/include/soc/memlayout.ld index 5d7481b..6091dd8 100644 --- a/src/soc/nvidia/tegra210/include/soc/memlayout.ld +++ b/src/soc/nvidia/tegra210/include/soc/memlayout.ld @@ -39,8 +39,8 @@ #endif TIMESTAMP(0x4000D800, 2K) BOOTBLOCK(0x4000E000, 30K) - VERSTAGE(0x40015800, 66K) - ROMSTAGE(0x40026000, 104K) + VERSTAGE(0x40015800, 70K) + ROMSTAGE(0x40026000, 100K) SRAM_END(0x40040000) DRAM_START(0x80000000) -- To view, visit https://review.coreboot.org/c/coreboot/+/34640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie00498838a644a6f92881db85833dd0a94b87f53 Gerrit-Change-Number: 34640 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: configs: Buildtest OpenSBI
by Patrick Rudolph (Code Review) 06 Aug '19

06 Aug '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34691 ) Change subject: configs: Buildtest OpenSBI ...................................................................... configs: Buildtest OpenSBI Build test OpenSBI on qemu-riscv-rv64. Change-Id: I23b9a1b06987d8d8ebb90655162ba4abce1557fa Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- A configs/config.emulation_qemu_riscv_rv64 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/34691/1 diff --git a/configs/config.emulation_qemu_riscv_rv64 b/configs/config.emulation_qemu_riscv_rv64 new file mode 100644 index 0000000..d41963c --- /dev/null +++ b/configs/config.emulation_qemu_riscv_rv64 @@ -0,0 +1,2 @@ +CONFIG_BOARD_EMULATION_QEMU_RISCV_RV64=y +CONFIG_RISCV_OPENSBI=y -- To view, visit https://review.coreboot.org/c/coreboot/+/34691 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23b9a1b06987d8d8ebb90655162ba4abce1557fa Gerrit-Change-Number: 34691 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation: Advertise support for OpenSBI
by Patrick Rudolph (Code Review) 06 Aug '19

06 Aug '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34690 ) Change subject: Documentation: Advertise support for OpenSBI ...................................................................... Documentation: Advertise support for OpenSBI Change-Id: Ie990bb95fcdcfab0246e8c694704022d9b8b5195 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Documentation/arch/riscv/index.md M Documentation/mainboard/sifive/hifive-unleashed.md 2 files changed, 16 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/34690/1 diff --git a/Documentation/arch/riscv/index.md b/Documentation/arch/riscv/index.md index 9a5de34..528b691 100644 --- a/Documentation/arch/riscv/index.md +++ b/Documentation/arch/riscv/index.md @@ -23,8 +23,20 @@ ## Additional payload handoff requirements The location of cbmem should be placed in a node in the FDT. +## OpenSBI +In case the payload doesn't install it's own SBI, like the [RISCV-PK] does, +[OpenSBI] can be used instead. +It's loaded into RAM after coreboot has finished loading the payload. +coreboot then will jump to OpenSBI providing a pointer to the real payload, +which OpenSBI will jump to once the SBI is installed. + +Besides providing SBI it also sets protected memory regions and provides +a platform independend console. + +The OpenSBI code is always run in M mode. + ## Trap delegation -Traps are delegated in the ramstage. +Traps are delegated to the payload. ## SMP within a stage At the beginning of each stage, all harts save 0 are spinning in a loop on @@ -44,3 +56,6 @@ will panic if possible, but behavior is largely undefined. Only hart 0 runs through most of the code in each stage. + +[RISCV-PK]: https://github.com/riscv/riscv-pk +[OpenSBI]: https://github.com/riscv/opensbi diff --git a/Documentation/mainboard/sifive/hifive-unleashed.md b/Documentation/mainboard/sifive/hifive-unleashed.md index 495dade..4dbbf0e 100644 --- a/Documentation/mainboard/sifive/hifive-unleashed.md +++ b/Documentation/mainboard/sifive/hifive-unleashed.md @@ -17,7 +17,6 @@ - Provide serial number to payload (e.g. in device tree) - Implement instruction emulation - Support for booting Linux on RISC-V -- Add support to run OpenSBI payload in m-mode - SMP support in trap handler ## Configuration -- To view, visit https://review.coreboot.org/c/coreboot/+/34690 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie990bb95fcdcfab0246e8c694704022d9b8b5195 Gerrit-Change-Number: 34690 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/*: Report mp_init errors
by Patrick Rudolph (Code Review) 06 Aug '19

06 Aug '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34586 ) Change subject: soc/*: Report mp_init errors ...................................................................... soc/*: Report mp_init errors Print or return errors if mp_run_on_all_cpus failed. Change-Id: I740505e3b6a46ebb3311d0e6b9669e7f929f9ab9 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/amd/common/block/pi/def_callouts.c M src/soc/intel/skylake/cpu.c 2 files changed, 10 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/34586/1 diff --git a/src/soc/amd/common/block/pi/def_callouts.c b/src/soc/amd/common/block/pi/def_callouts.c index 6734b55..e45b5fd 100644 --- a/src/soc/amd/common/block/pi/def_callouts.c +++ b/src/soc/amd/common/block/pi/def_callouts.c @@ -220,8 +220,8 @@ agesadata.Func = Func; agesadata.Data = Data; agesadata.ConfigPtr = ConfigPtr; - mp_run_on_aps(callout_ap_entry, NULL, MP_RUN_ON_ALL_CPUS, - 100 * USECS_PER_MSEC); + if (mp_run_on_aps(callout_ap_entry, NULL, MP_RUN_ON_ALL_CPUS, 100 * USECS_PER_MSEC)) + return AGESA_ERROR; return AGESA_SUCCESS; } diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 2fd01b4..a558447 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -476,6 +476,8 @@ static void post_mp_init(void) { + int ret = 0; + /* Set Max Ratio */ cpu_set_max_ratio(); @@ -489,11 +491,14 @@ if (CONFIG(HAVE_SMI_HANDLER)) smm_lock(); - mp_run_on_all_cpus(vmx_configure, NULL, 2 * USECS_PER_MSEC); + ret |= mp_run_on_all_cpus(vmx_configure, NULL, 2 * USECS_PER_MSEC); - mp_run_on_all_cpus(sgx_configure, NULL, 14 * USECS_PER_MSEC); + ret |= mp_run_on_all_cpus(sgx_configure, NULL, 14 * USECS_PER_MSEC); - mp_run_on_all_cpus(fc_lock_configure, NULL, 2 * USECS_PER_MSEC); + ret |= mp_run_on_all_cpus(fc_lock_configure, NULL, 2 * USECS_PER_MSEC); + + if (ret) + printk(BIOS_CRIT, "CRITICAL ERROR: MP post init failed\n"); } static const struct mp_ops mp_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/34586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I740505e3b6a46ebb3311d0e6b9669e7f929f9ab9 Gerrit-Change-Number: 34586 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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coreboot-gerrit August 2019