coreboot-gerrit August 2019

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Change in coreboot[master]: intel/haswell,broadwell,fsp_broadwell_de: Drop unused parameter
by Kyösti Mälkki (Code Review) 06 Aug '19

06 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34746 ) Change subject: intel/haswell,broadwell,fsp_broadwell_de: Drop unused parameter ...................................................................... intel/haswell,broadwell,fsp_broadwell_de: Drop unused parameter Change-Id: I3f2c89f1b7d5980640cceca02a25d2903b17a78c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/haswell/smmrelocate.c M src/soc/intel/broadwell/smmrelocate.c M src/soc/intel/fsp_broadwell_de/smmrelocate.c 3 files changed, 6 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/34746/1 diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index ca2c68f..a9954ec 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -210,8 +210,7 @@ } } -static void fill_in_relocation_params(struct device *dev, - struct smm_relocation_params *params) +static void fill_in_relocation_params(struct smm_relocation_params *params) { uintptr_t tseg_base; size_t tseg_size; @@ -290,11 +289,9 @@ void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { - struct device *dev = pcidev_on_root(0, 0); - printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - fill_in_relocation_params(dev, &smm_reloc_params); + fill_in_relocation_params(&smm_reloc_params); setup_ied_area(&smm_reloc_params); diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c index 7e893c1..981b42b 100644 --- a/src/soc/intel/broadwell/smmrelocate.c +++ b/src/soc/intel/broadwell/smmrelocate.c @@ -179,8 +179,7 @@ } } -static void fill_in_relocation_params(struct device *dev, - struct smm_relocation_params *params) +static void fill_in_relocation_params(struct smm_relocation_params *params) { uintptr_t tseg_base; size_t tseg_size; @@ -251,11 +250,9 @@ void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { - struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); - printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - fill_in_relocation_params(dev, &smm_reloc_params); + fill_in_relocation_params(&smm_reloc_params); setup_ied_area(&smm_reloc_params); diff --git a/src/soc/intel/fsp_broadwell_de/smmrelocate.c b/src/soc/intel/fsp_broadwell_de/smmrelocate.c index 3086acb..a7b06dc 100644 --- a/src/soc/intel/fsp_broadwell_de/smmrelocate.c +++ b/src/soc/intel/fsp_broadwell_de/smmrelocate.c @@ -190,8 +190,7 @@ write_prmrr(relo_params); } -static void fill_in_relocation_params(pci_devfn_t dev, - struct smm_relocation_params *params) +static void fill_in_relocation_params(struct smm_relocation_params *params) { uintptr_t tseg_base; size_t tseg_size; @@ -261,11 +260,9 @@ void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { - pci_devfn_t dev = PCI_DEV(BUS0, VTD_DEV, VTD_FUNC); - printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - fill_in_relocation_params(dev, &smm_reloc_params); + fill_in_relocation_params(&smm_reloc_params); setup_ied_area(&smm_reloc_params); -- To view, visit https://review.coreboot.org/c/coreboot/+/34746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f2c89f1b7d5980640cceca02a25d2903b17a78c Gerrit-Change-Number: 34746 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib: Call extract() only when initrd.size is more than 0
by Asami Doi (Code Review) 06 Aug '19

06 Aug '19

Asami Doi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34535 ) Change subject: lib: Call extract() only when initrd.size is more than 0 ...................................................................... lib: Call extract() only when initrd.size is more than 0 This CL avoid the fail that happens when initrd.size is 0. extract() returns false even though initrd.size is already 0. In the case of size is 0, we don't know extract it, so call extract() only when initrd.size is more than 0. Signed-off-by: Asami Doi <d0iasm.pub(a)gmail.com> Change-Id: I85aa33d2c2846b6b3a58df834dda18c47433257d --- M src/lib/fit_payload.c 1 file changed, 7 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/34535/1 diff --git a/src/lib/fit_payload.c b/src/lib/fit_payload.c index a4d3705..57cd4a5 100644 --- a/src/lib/fit_payload.c +++ b/src/lib/fit_payload.c @@ -246,12 +246,13 @@ /* Repack FDT for handoff to kernel */ pack_fdt(&fdt, dt); - if (config->ramdisk && - extract(&initrd, config->ramdisk)) { - printk(BIOS_ERR, "ERROR: Failed to extract initrd\n"); - prog_set_entry(payload, NULL, NULL); - rdev_munmap(prog_rdev(payload), data); - return; + if (config->ramdisk && initrd.size > 0) { + if (extract(&initrd, config->ramdisk)) { + printk(BIOS_ERR, "ERROR: Failed to extract initrd\n"); + prog_set_entry(payload, NULL, NULL); + rdev_munmap(prog_rdev(payload), data); + return; + } } timestamp_add_now(TS_KERNEL_DECOMPRESSION); -- To view, visit https://review.coreboot.org/c/coreboot/+/34535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85aa33d2c2846b6b3a58df834dda18c47433257d Gerrit-Change-Number: 34535 Gerrit-PatchSet: 1 Gerrit-Owner: Asami Doi <d0iasm.pub(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: dram: Add basic DDR4 SPD parsing
by Matt DeVillier (Code Review) 06 Aug '19

06 Aug '19

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34680 ) Change subject: dram: Add basic DDR4 SPD parsing ...................................................................... Patch Set 3: Code-Review+1 (1 comment) https://review.coreboot.org/c/coreboot/+/34680/3/src/device/dram/ddr4.c File src/device/dram/ddr4.c: https://review.coreboot.org/c/coreboot/+/34680/3/src/device/dram/ddr4.c@46 PS3, Line 46: DDR3 DDR4 -- To view, visit https://review.coreboot.org/c/coreboot/+/34680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3befbc55cf37e1018baa432cb2f03743b929211 Gerrit-Change-Number: 34680 Gerrit-PatchSet: 3 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 06 Aug 2019 19:31:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/fsp_broadwell_de: Populate SMBIOS tables with memory inform...
by build bot (Jenkins) (Code Review) 06 Aug '19

06 Aug '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34681 ) Change subject: soc/intel/fsp_broadwell_de: Populate SMBIOS tables with memory information ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/34681/3/src/soc/intel/fsp_broadwel… File src/soc/intel/fsp_broadwell_de/romstage/memory.c: https://review.coreboot.org/c/coreboot/+/34681/3/src/soc/intel/fsp_broadwel… PS3, Line 40: SPD_SLAVE_ADDR(1, 0), SPD_SLAVE_ADDR(1, 1)}}; space required after that close brace '}' -- To view, visit https://review.coreboot.org/c/coreboot/+/34681 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1162eb4484dab46f1ab9fe3426eecc4d9378e8e2 Gerrit-Change-Number: 34681 Gerrit-PatchSet: 3 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 06 Aug 2019 18:21:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: lib/spd_bin: Fix bug with rank parsing for DDR4
by Andrey Petrov (Code Review) 06 Aug '19

06 Aug '19

Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34684 ) Change subject: lib/spd_bin: Fix bug with rank parsing for DDR4 ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/34684 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3184c5a7fd4b5ae5882914e62d1cb0c28bb881e7 Gerrit-Change-Number: 34684 Gerrit-PatchSet: 1 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Aug 2019 18:13:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/fsp_broadwell_de: Populate SMBIOS tables with memory inform...
by Andrey Petrov (Code Review) 06 Aug '19

06 Aug '19

Hello Patrick Rudolph, Matt DeVillier, David Hendricks, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/34681 to look at the new patch set (#3). Change subject: soc/intel/fsp_broadwell_de: Populate SMBIOS tables with memory information ...................................................................... soc/intel/fsp_broadwell_de: Populate SMBIOS tables with memory information Add code to read SPD data, parse it and save into SMBIOS table. This is implemented for socketed DDR4 chips only. For soldered-down memory this is not implemented and probably won't be ever needed. TEST=tested on OCP Monolake mainboard, and found dmidecode -t memory to work. The stack has also been tested on an out-of-tree board. Signed-off-by: Andrey Petrov <anpetrov(a)fb.com> Change-Id: I1162eb4484dab46f1ab9fe3426eecc4d9378e8e2 --- M src/soc/intel/fsp_broadwell_de/Kconfig A src/soc/intel/fsp_broadwell_de/include/soc/memory.h M src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h M src/soc/intel/fsp_broadwell_de/romstage/Makefile.inc A src/soc/intel/fsp_broadwell_de/romstage/memory.c M src/soc/intel/fsp_broadwell_de/romstage/romstage.c 6 files changed, 110 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/34681/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/34681 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1162eb4484dab46f1ab9fe3426eecc4d9378e8e2 Gerrit-Change-Number: 34681 Gerrit-PatchSet: 3 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: dram: Add basic DDR4 SPD parsing
by Andrey Petrov (Code Review) 06 Aug '19

06 Aug '19

Hello Arthur Heymans, Matt DeVillier, David Hendricks, Stefan Reinauer, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/34680 to look at the new patch set (#3). Change subject: dram: Add basic DDR4 SPD parsing ...................................................................... dram: Add basic DDR4 SPD parsing Add ability to decode basic fields of DDR4 SPDs and produce SMBIOS table 17. CRC check, XMP, extended field parising is totally not yet implemented. Signed-off-by: Andrey Petrov <anpetrov(a)fb.com> Change-Id: If3befbc55cf37e1018baa432cb2f03743b929211 --- M src/device/dram/Makefile.inc A src/device/dram/ddr4.c A src/include/device/dram/ddr4.h 3 files changed, 243 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/34680/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/34680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3befbc55cf37e1018baa432cb2f03743b929211 Gerrit-Change-Number: 34680 Gerrit-PatchSet: 3 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: common/block/imc: Add Integrated Memory Controller (IMC) driver
by Andrey Petrov (Code Review) 06 Aug '19

06 Aug '19

Hello Kyösti Mälkki, Alexandru Gagniuc, Amol N Sukerkar, Subrata Banik, Aamir Bohra, Matt DeVillier, David Hendricks, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/34678 to look at the new patch set (#3). Change subject: common/block/imc: Add Integrated Memory Controller (IMC) driver ...................................................................... common/block/imc: Add Integrated Memory Controller (IMC) driver IMC is found on certain Xeon processors. On such platforms SPDs are not connected to SMBus on PCH but to dedicated IMC-owned pins. The purpose of this driver is to expose access to the i2c/smbus controller associated with IMC. Datasheet used: Intel Xeon Processor D-1500 Product Family, Volume 2, reference 332051-001 This driver is largely based on i2c-imc.c Linux driver. https://lwn.net/Articles/685475/ TEST=single/double reads and single writes on Xeon-D1500. Hardware: Open Compute Project Monolake platform. Signed-off-by: Andrey Petrov <anpetrov(a)fb.com> Change-Id: Idbcda1c2273b9a5721fcd9470b4de182192779e7 --- A src/soc/intel/common/block/imc/Kconfig A src/soc/intel/common/block/imc/Makefile.inc A src/soc/intel/common/block/imc/imc.c A src/soc/intel/common/block/include/intelblocks/imc.h M src/soc/intel/fsp_broadwell_de/Kconfig 5 files changed, 219 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/34678/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/34678 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idbcda1c2273b9a5721fcd9470b4de182192779e7 Gerrit-Change-Number: 34678 Gerrit-PatchSet: 3 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Gerrit-Reviewer: Amol N Sukerkar <amol.n.sukerkar(a)intel.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/picasso: Create a hybrid romstage to begin in DRAM
by build bot (Jenkins) (Code Review) 06 Aug '19

06 Aug '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33759 ) Change subject: soc/amd/picasso: Create a hybrid romstage to begin in DRAM ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/c/coreboot/+/33759/8/src/soc/amd/picasso/romsta… File src/soc/amd/picasso/romstage.c: https://review.coreboot.org/c/coreboot/+/33759/8/src/soc/amd/picasso/romsta… PS8, Line 48: || (CONFIG_DCACHE_RAM_BASE >= CONFIG_ROMSTAGE_ADDR \ Comparisons should place the constant on the right side of the test -- To view, visit https://review.coreboot.org/c/coreboot/+/33759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8c6175de34a0728ad41085e9c7cd310bd280976 Gerrit-Change-Number: 33759 Gerrit-PatchSet: 8 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 06 Aug 2019 17:20:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: Create a hybrid romstage to begin in DRAM
by Marshall Dawson (Code Review) 06 Aug '19

06 Aug '19

Hello Edward O'Callaghan, Julius Werner, Richard Spiegel, build bot (Jenkins), Furquan Shaikh, Martin Roth, Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/33759 to look at the new patch set (#8). Change subject: soc/amd/picasso: Create a hybrid romstage to begin in DRAM ...................................................................... soc/amd/picasso: Create a hybrid romstage to begin in DRAM Add the support files to begin execution in romstage and located in DRAM. Details for this implementation are found in Documentation/amd/picasso/family17.md. Combine steps typically found in bootblock, containing the reset vector and protected mode enable, with the parts of romstage that enable the console and cbmem. Duplicate the ROMSTAGE_ADDR and ROMSTAGE_MAX_SIZE items into Kconfig and give them safe default values in DRAM. The DCACHE values are kept and DRAM is used as a CAR substitute. Add a romstage.ld file that positions the reset vector and describes the additional items needed for the hybrid romstage. Change-Id: Id8c6175de34a0728ad41085e9c7cd310bd280976 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc M src/soc/amd/picasso/include/soc/cpu.h M src/soc/amd/picasso/include/soc/romstage.h A src/soc/amd/picasso/include/soc/romstage.ld A src/soc/amd/picasso/reset_vector.S M src/soc/amd/picasso/romstage.c 7 files changed, 400 insertions(+), 72 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/33759/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/33759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8c6175de34a0728ad41085e9c7cd310bd280976 Gerrit-Change-Number: 33759 Gerrit-PatchSet: 8 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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coreboot-gerrit August 2019