coreboot-gerrit August 2019

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Change in ...coreboot[master]: google/krane: turn off backlight before config display
by jitao shi (Code Review) 06 Aug '19

06 Aug '19

jitao shi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33572 Change subject: google/krane: turn off backlight before config display ...................................................................... google/krane: turn off backlight before config display Turn off backlight before display config and then turn on backlight after display config. Avoid flash white screen when configuring display. BUG=b:129299873 BRANCH=none Change-Id: I91ae2fabdf1c00b0683085a03d3f48ad3b6b7879 Signed-off-by: Jitao Shi <jitao.shi(a)mediatek.com> --- M src/mainboard/google/kukui/panel_krane.c 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/33572/1 diff --git a/src/mainboard/google/kukui/panel_krane.c b/src/mainboard/google/kukui/panel_krane.c index cb6e9cf..55c7ff5 100644 --- a/src/mainboard/google/kukui/panel_krane.c +++ b/src/mainboard/google/kukui/panel_krane.c @@ -388,10 +388,11 @@ return false; }; +/* Setup backlight control pins as output pin and power-off by default */ static int krane_backlight(struct board_display_intf *intf) { - gpio_output(GPIO(PERIPHERAL_EN13), 1); - gpio_output(GPIO(DISP_PWM), 1); /* DISP_PWM0 */ + gpio_output(GPIO(PERIPHERAL_EN13), 0); + gpio_output(GPIO(DISP_PWM), 0); return 0; }; -- To view, visit https://review.coreboot.org/c/coreboot/+/33572 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91ae2fabdf1c00b0683085a03d3f48ad3b6b7879 Gerrit-Change-Number: 33572 Gerrit-PatchSet: 1 Gerrit-Owner: jitao shi <jitao.shi(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/hatch/variants/helios: Update DPTF parameters and TDP PL1/PL2
by Frank Chu (Code Review) 06 Aug '19

06 Aug '19

Frank Chu has removed Philipp Deppenwiese from this change. ( https://review.coreboot.org/c/coreboot/+/34743 ) Change subject: mb/google/hatch/variants/helios: Update DPTF parameters and TDP PL1/PL2 ...................................................................... Removed reviewer Philipp Deppenwiese. -- To view, visit https://review.coreboot.org/c/coreboot/+/34743 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7a96c33ce710c32b57e2ad8066830ff83398c57 Gerrit-Change-Number: 34743 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: intel/fsp_rangeley: Rename raminit.c to memmap.c
by David Guckian (Code Review) 06 Aug '19

06 Aug '19

David Guckian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34698 ) Change subject: intel/fsp_rangeley: Rename raminit.c to memmap.c ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/34698 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I704d7cb637e4e12039ade99f57e10af794c8be97 Gerrit-Change-Number: 34698 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 06 Aug 2019 08:18:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Select USE_LEGACY_8254_TIMER
by Patrick Rudolph (Code Review) 06 Aug '19

06 Aug '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34736 ) Change subject: soc/intel/common: Select USE_LEGACY_8254_TIMER ...................................................................... soc/intel/common: Select USE_LEGACY_8254_TIMER Always select USE_LEGACY_8254_TIMER if we know we have to. Default to y as there might be legacy software not under our control that needs the 8254 timer. Add a comment to evaluate if this should be changed to 'default n' in 10 years from now. The following software needs 8254 timer: * SeaBios * Option ROMs * GRUB <2.03 * Linux <5.3 References: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git/commit/?id=c8c4… http://git.savannah.gnu.org/cgit/grub.git/commit/?id=446794de8da4329ea532cb… Fixes boot failure on SeaBios and GRUB2 bootloader on X11SSH-TF using SeaBIOS as payload. Change-Id: I3eae8249e87a54c877e320ebce6595030c48fe2f Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M payloads/external/SeaBIOS/Kconfig.name M src/device/Kconfig M src/soc/intel/common/block/timer/Kconfig 3 files changed, 12 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/34736/1 diff --git a/payloads/external/SeaBIOS/Kconfig.name b/payloads/external/SeaBIOS/Kconfig.name index bb1f30c..8f92997 100644 --- a/payloads/external/SeaBIOS/Kconfig.name +++ b/payloads/external/SeaBIOS/Kconfig.name @@ -1,6 +1,7 @@ config PAYLOAD_SEABIOS bool "SeaBIOS" depends on ARCH_X86 + select USE_LEGACY_8254_TIMER if SOC_INTEL_COMMON_BLOCK help Select this option if you want to build a coreboot image with a SeaBIOS payload. If you don't know what this is diff --git a/src/device/Kconfig b/src/device/Kconfig index e605bc2..ebf6bfb 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -86,6 +86,7 @@ bool "Run VGA Option ROMs" depends on PCI && (ARCH_X86 || ARCH_PPC64) && !MAINBOARD_FORCE_NATIVE_VGA_INIT select HAVE_VGA_TEXT_FRAMEBUFFER + select USE_LEGACY_8254_TIMER if SOC_INTEL_COMMON_BLOCK help Execute VGA Option ROMs in coreboot if found. This can be used to enable PCI/AGP/PCI-E video cards when not using a SeaBIOS diff --git a/src/soc/intel/common/block/timer/Kconfig b/src/soc/intel/common/block/timer/Kconfig index a214ef0..50c7677 100644 --- a/src/soc/intel/common/block/timer/Kconfig +++ b/src/soc/intel/common/block/timer/Kconfig @@ -5,10 +5,16 @@ config USE_LEGACY_8254_TIMER bool "Use Legacy 8254 Timer" - default y if PAYLOAD_SEABIOS || VGA_ROM_RUN - default n + default y help This sets the FSP UPD to enable Legacy 8254 clock gating. As per the FSP Integration guide Legacy 8254 timer clock gating UPD needs - to be disabled in order to boot SeaBIOS or run OpRom, - but should otherwise be enabled. + to be disabled in order to boot legacy software. + TODO after 2029: Evaluate if this should be changed to 'default n'. + +if !USE_LEGACY_8254_TIMER + +comment "Warning: The following software won't run due to disabled 8254 timer" +comment " GRUB <2.03, Linux <5.3, SeaBios, Option ROMs" + +endif -- To view, visit https://review.coreboot.org/c/coreboot/+/34736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3eae8249e87a54c877e320ebce6595030c48fe2f Gerrit-Change-Number: 34736 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: northbridge/intel: Rename ram_calc.c to memmap.c
by Arthur Heymans (Code Review) 06 Aug '19

06 Aug '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34699 ) Change subject: northbridge/intel: Rename ram_calc.c to memmap.c ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/34699 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie69583f28f384eb49517203e1c3867f27e6272de Gerrit-Change-Number: 34699 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 06 Aug 2019 06:06:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: intel/fsp_rangeley: Rename raminit.c to memmap.c
by Arthur Heymans (Code Review) 06 Aug '19

06 Aug '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34698 ) Change subject: intel/fsp_rangeley: Rename raminit.c to memmap.c ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/34698 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I704d7cb637e4e12039ade99f57e10af794c8be97 Gerrit-Change-Number: 34698 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 06 Aug 2019 06:06:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: Kconfig: Make CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM dependent on ARC...
by Subrata Banik (Code Review) 06 Aug '19

06 Aug '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33116 Change subject: Kconfig: Make CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM dependent on ARCH_RAMSTAGE_X86_32 ...................................................................... Kconfig: Make CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM dependent on ARCH_RAMSTAGE_X86_32 Change-Id: I45e894ad335a4661cc7916b3768e1614a038b31c Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/cpu/intel/model_2065x/Kconfig M src/cpu/intel/model_206ax/Kconfig M src/northbridge/intel/gm45/Kconfig M src/northbridge/intel/haswell/Kconfig M src/northbridge/intel/i945/Kconfig M src/northbridge/intel/pineview/Kconfig M src/northbridge/intel/x4x/Kconfig M src/soc/amd/stoneyridge/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/broadwell/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/skylake/Kconfig 14 files changed, 14 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/33116/1 diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index d8c0168..e7679a6 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -21,7 +21,7 @@ select CPU_INTEL_COMMON select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if ARCH_RAMSTAGE_X86_32 config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index dbb8982..951f45b 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -20,7 +20,7 @@ #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE select CPU_INTEL_COMMON - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if ARCH_RAMSTAGE_X86_32 select PARALLEL_MP select NO_FIXED_XIP_ROM_SIZE diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index f1318eb..a704467 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -30,7 +30,7 @@ select POSTCAR_CONSOLE select SMM_TSEG select PARALLEL_MP - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if ARCH_RAMSTAGE_X86_32 config CBFS_SIZE hex diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index e1067c5..3081c28 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -19,7 +19,7 @@ select CACHE_MRC_SETTINGS select INTEL_DDI select INTEL_GMA_ACPI - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if ARCH_RAMSTAGE_X86_32 select POSTCAR_STAGE select POSTCAR_CONSOLE select C_ENVIRONMENT_BOOTBLOCK diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index 2c21420..d3b760d 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -31,7 +31,7 @@ select POSTCAR_CONSOLE select SMM_TSEG select PARALLEL_MP - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if ARCH_RAMSTAGE_X86_32 config NORTHBRIDGE_INTEL_SUBTYPE_I945GC def_bool n diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index 2b4f502..b8f6761 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -32,7 +32,7 @@ select POSTCAR_CONSOLE select SMM_TSEG select PARALLEL_MP - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if ARCH_RAMSTAGE_X86_32 select C_ENVIRONMENT_BOOTBLOCK config BOOTBLOCK_NORTHBRIDGE_INIT diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index 7cae91e..a8b492c 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -30,7 +30,7 @@ select POSTCAR_CONSOLE select SMM_TSEG select PARALLEL_MP - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if ARCH_RAMSTAGE_X86_32 config CBFS_SIZE hex diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index d4e1feb..99fd33b 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -55,7 +55,7 @@ select C_ENVIRONMENT_BOOTBLOCK select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if ARCH_RAMSTAGE_X86_32 select PARALLEL_MP select PARALLEL_MP_AP_WORK select HAVE_SMI_HANDLER diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 217d1ea..0bfbf03 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -40,7 +40,7 @@ # Misc options select C_ENVIRONMENT_BOOTBLOCK select CACHE_MRC_SETTINGS - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if ARCH_RAMSTAGE_X86_32 select COLLECT_TIMESTAMPS select COMMON_FADT select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index ed5c972..0c082d0 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -14,7 +14,7 @@ select ARCH_VERSTAGE_X86_32 select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if ARCH_RAMSTAGE_X86_32 select COLLECT_TIMESTAMPS select SUPPORT_CPU_UCODE_IN_CBFS select MICROCODE_BLOB_NOT_IN_BLOB_REPO diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index d81ab8a..9c99569 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -15,7 +15,7 @@ select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select MRC_SETTINGS_PROTECT - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if ARCH_RAMSTAGE_X86_32 select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_MONOTONIC_TIMER diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index e524275..7448e3f 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -57,7 +57,7 @@ select BOOT_DEVICE_SUPPORTS_WRITES select C_ENVIRONMENT_BOOTBLOCK select CACHE_MRC_SETTINGS - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if ARCH_RAMSTAGE_X86_32 select COMMON_FADT select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index a4b46ba..5e7a659 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -16,7 +16,7 @@ select BOOT_DEVICE_SUPPORTS_WRITES select C_ENVIRONMENT_BOOTBLOCK select CACHE_MRC_SETTINGS - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if ARCH_RAMSTAGE_X86_32 select COMMON_FADT select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select FSP_M_XIP diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index fcfe2b6..b403540 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -23,7 +23,7 @@ select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if ARCH_RAMSTAGE_X86_32 select COLLECT_TIMESTAMPS select COMMON_FADT select CPU_INTEL_COMMON -- To view, visit https://review.coreboot.org/c/coreboot/+/33116 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45e894ad335a4661cc7916b3768e1614a038b31c Gerrit-Change-Number: 33116 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Hack up per-board user selectable 64bit scheme
by Martin Roth (Code Review) 06 Aug '19

06 Aug '19

Martin Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/11109 ) Change subject: Hack up per-board user selectable 64bit scheme ...................................................................... Abandoned This patch was not touched in over 18 months. Anyone who wants to take over work on this patch, please feel free to restore it and do what you'd like. If you create a new patch based on this work, please credit the original author. -- To view, visit https://review.coreboot.org/c/coreboot/+/11109 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91b1316896e69b081c861d99ff0c04be3c1d90c1 Gerrit-Change-Number: 11109 Gerrit-PatchSet: 2 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: soc/intel/broadwell: Fix UART compilation
by Martin Roth (Code Review) 06 Aug '19

06 Aug '19

Martin Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/13554 ) Change subject: soc/intel/broadwell: Fix UART compilation ...................................................................... Abandoned This patch was not touched in over 18 months. Anyone who wants to take over work on this patch, please feel free to restore it and do what you'd like. If you create a new patch based on this work, please credit the original author. -- To view, visit https://review.coreboot.org/c/coreboot/+/13554 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7fe356041c6ac69a30e0e87d9a8649abef6996b7 Gerrit-Change-Number: 13554 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: drivers/uart: Export uart8250_mem_init from uart8250mem.c
by Martin Roth (Code Review) 06 Aug '19

06 Aug '19

Martin Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/13553 ) Change subject: drivers/uart: Export uart8250_mem_init from uart8250mem.c ...................................................................... Abandoned This patch was not touched in over 18 months. Anyone who wants to take over work on this patch, please feel free to restore it and do what you'd like. If you create a new patch based on this work, please credit the original author. -- To view, visit https://review.coreboot.org/c/coreboot/+/13553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc5b5c43475bf59d0d54cba2afd9362e75fa360c Gerrit-Change-Number: 13553 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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coreboot-gerrit August 2019