coreboot-gerrit August 2019

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Change in ...coreboot[master]: src/superio/aspeed/common: Add ACPI Template for Autogen Feature
by Christian Walter (Code Review) 07 Aug '19

07 Aug '19

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33250 Change subject: src/superio/aspeed/common: Add ACPI Template for Autogen Feature ...................................................................... src/superio/aspeed/common: Add ACPI Template for Autogen Feature Add ACPI Template for Autogen Feature. Change-Id: Ic356af269e381bd5310d9be057bc16f9d5186934 Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- A src/superio/aspeed/common/acpi/superio.asl 1 file changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/33250/1 diff --git a/src/superio/aspeed/common/acpi/superio.asl b/src/superio/aspeed/common/acpi/superio.asl new file mode 100644 index 0000000..6b8b8f6 --- /dev/null +++ b/src/superio/aspeed/common/acpi/superio.asl @@ -0,0 +1,21 @@ +## +## This file is part of the coreboot project. +## +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +Device (SIO0) +{ + Name (_HID, EisaId ("PNP0C02") /* PNP Motherboard Resources */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + +} \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/33250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic356af269e381bd5310d9be057bc16f9d5186934 Gerrit-Change-Number: 33250 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: dram: Add basic DDR4 SPD parsing
by Christian Walter (Code Review) 07 Aug '19

07 Aug '19

Christian Walter has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34680 ) Change subject: dram: Add basic DDR4 SPD parsing ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/34680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3befbc55cf37e1018baa432cb2f03743b929211 Gerrit-Change-Number: 34680 Gerrit-PatchSet: 3 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 07 Aug 2019 08:47:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: intel/braswell: Drop config IED_REGION_SIZE
by Kyösti Mälkki (Code Review) 07 Aug '19

07 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34695 ) Change subject: intel/braswell: Drop config IED_REGION_SIZE ...................................................................... intel/braswell: Drop config IED_REGION_SIZE Platform does not setup IED. Change-Id: Ied72888c6406b59332bc3d68eccb50bf1eab3419 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/braswell/Kconfig 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/34695/1 diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 87b9c5b..76adae1 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -129,10 +129,6 @@ configure the pads and enable it. This serial port can be used for the debug console. -config IED_REGION_SIZE - hex - default 0x400000 - config DISABLE_HPET bool "Disable the HPET device" default n -- To view, visit https://review.coreboot.org/c/coreboot/+/34695 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied72888c6406b59332bc3d68eccb50bf1eab3419 Gerrit-Change-Number: 34695 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: southbridge/amd: Rename ramtop.c to memmap.c
by Kyösti Mälkki (Code Review) 07 Aug '19

07 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34700 ) Change subject: southbridge/amd: Rename ramtop.c to memmap.c ...................................................................... southbridge/amd: Rename ramtop.c to memmap.c Use a name consistent with the more recent soc/intel. Change-Id: Ia5076ed1a59acc5a77c1a6cf5510b11e9d0a925f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/northbridge/amd/pi/Makefile.inc R src/northbridge/amd/pi/memmap.c M src/southbridge/amd/agesa/hudson/Makefile.inc R src/southbridge/amd/agesa/hudson/memmap.c M src/southbridge/amd/cimx/sb800/Makefile.inc R src/southbridge/amd/cimx/sb800/memmap.c M src/southbridge/amd/cimx/sb900/Makefile.inc R src/southbridge/amd/cimx/sb900/memmap.c M src/southbridge/amd/sb700/Makefile.inc R src/southbridge/amd/sb700/memmap.c M src/southbridge/amd/sb800/Makefile.inc R src/southbridge/amd/sb800/memmap.c 12 files changed, 16 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/34700/1 diff --git a/src/northbridge/amd/pi/Makefile.inc b/src/northbridge/amd/pi/Makefile.inc index c2c8d88..3380b63 100644 --- a/src/northbridge/amd/pi/Makefile.inc +++ b/src/northbridge/amd/pi/Makefile.inc @@ -24,7 +24,7 @@ ramstage-y += agesawrapper.c endif -romstage-y += ramtop.c -postcar-y += ramtop.c -ramstage-y += ramtop.c +romstage-y += memmap.c +postcar-y += memmap.c +ramstage-y += memmap.c endif diff --git a/src/northbridge/amd/pi/ramtop.c b/src/northbridge/amd/pi/memmap.c similarity index 100% rename from src/northbridge/amd/pi/ramtop.c rename to src/northbridge/amd/pi/memmap.c diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index cd0a1d5..042d34d 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -23,10 +23,10 @@ romstage-y += early_setup.c ramstage-$(CONFIG_SPI_FLASH) += spi.c -ramstage-y += resume.c ramtop.c +ramstage-y += resume.c memmap.c -romstage-y += ramtop.c -postcar-y += ramtop.c +romstage-y += memmap.c +postcar-y += memmap.c romstage-y += imc.c ramstage-y += imc.c diff --git a/src/southbridge/amd/agesa/hudson/ramtop.c b/src/southbridge/amd/agesa/hudson/memmap.c similarity index 100% rename from src/southbridge/amd/agesa/hudson/ramtop.c rename to src/southbridge/amd/agesa/hudson/memmap.c diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc index 418110b..10c682a 100644 --- a/src/southbridge/amd/cimx/sb800/Makefile.inc +++ b/src/southbridge/amd/cimx/sb800/Makefile.inc @@ -30,9 +30,9 @@ ramstage-$(CONFIG_SPI_FLASH) += spi.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c -postcar-y += ramtop.c -romstage-y += ramtop.c -ramstage-y += ramtop.c +postcar-y += memmap.c +romstage-y += memmap.c +ramstage-y += memmap.c bootblock-$(CONFIG_USBDEBUG) += ../../sb800/enable_usbdebug.c romstage-$(CONFIG_USBDEBUG) += ../../sb800/enable_usbdebug.c diff --git a/src/southbridge/amd/cimx/sb800/ramtop.c b/src/southbridge/amd/cimx/sb800/memmap.c similarity index 100% rename from src/southbridge/amd/cimx/sb800/ramtop.c rename to src/southbridge/amd/cimx/sb800/memmap.c diff --git a/src/southbridge/amd/cimx/sb900/Makefile.inc b/src/southbridge/amd/cimx/sb900/Makefile.inc index ff9ada6..4125d5f 100644 --- a/src/southbridge/amd/cimx/sb900/Makefile.inc +++ b/src/southbridge/amd/cimx/sb900/Makefile.inc @@ -20,15 +20,15 @@ romstage-y += early.c romstage-y += smbus.c smbus_spd.c romstage-y += reset.c -romstage-y += ramtop.c +romstage-y += memmap.c -postcar-y += ramtop.c +postcar-y += memmap.c ramstage-y += cfg.c ramstage-y += early.c ramstage-y += late.c ramstage-y += reset.c -ramstage-y += ramtop.c +ramstage-y += memmap.c ramstage-y += smbus.c ramstage-y += lpc.c diff --git a/src/southbridge/amd/cimx/sb900/ramtop.c b/src/southbridge/amd/cimx/sb900/memmap.c similarity index 100% rename from src/southbridge/amd/cimx/sb900/ramtop.c rename to src/southbridge/amd/cimx/sb900/memmap.c diff --git a/src/southbridge/amd/sb700/Makefile.inc b/src/southbridge/amd/sb700/Makefile.inc index 17d0a3a..f11092f 100644 --- a/src/southbridge/amd/sb700/Makefile.inc +++ b/src/southbridge/amd/sb700/Makefile.inc @@ -21,7 +21,7 @@ romstage-y += early_setup.c romstage-y += smbus.c -romstage-y += ramtop.c -ramstage-y += ramtop.c +romstage-y += memmap.c +ramstage-y += memmap.c endif diff --git a/src/southbridge/amd/sb700/ramtop.c b/src/southbridge/amd/sb700/memmap.c similarity index 100% rename from src/southbridge/amd/sb700/ramtop.c rename to src/southbridge/amd/sb700/memmap.c diff --git a/src/southbridge/amd/sb800/Makefile.inc b/src/southbridge/amd/sb800/Makefile.inc index fd2577c..9dc2eaa 100644 --- a/src/southbridge/amd/sb800/Makefile.inc +++ b/src/southbridge/amd/sb800/Makefile.inc @@ -16,7 +16,7 @@ romstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c -romstage-y += ramtop.c -ramstage-y += ramtop.c +romstage-y += memmap.c +ramstage-y += memmap.c endif diff --git a/src/southbridge/amd/sb800/ramtop.c b/src/southbridge/amd/sb800/memmap.c similarity index 100% rename from src/southbridge/amd/sb800/ramtop.c rename to src/southbridge/amd/sb800/memmap.c -- To view, visit https://review.coreboot.org/c/coreboot/+/34700 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5076ed1a59acc5a77c1a6cf5510b11e9d0a925f Gerrit-Change-Number: 34700 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd: Rename smm_region_info() to smm_region()
by Kyösti Mälkki (Code Review) 07 Aug '19

07 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34703 ) Change subject: soc/amd: Rename smm_region_info() to smm_region() ...................................................................... soc/amd: Rename smm_region_info() to smm_region() Change-Id: I361fb0e02fd0bd92bb1e13fe84c898a1ac85aa40 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/include/cpu/x86/smm.h M src/soc/amd/picasso/cpu.c M src/soc/amd/picasso/ramtop.c M src/soc/amd/picasso/romstage.c M src/soc/amd/stoneyridge/cpu.c M src/soc/amd/stoneyridge/ramtop.c M src/soc/amd/stoneyridge/romstage.c 7 files changed, 6 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34703/1 diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index edd1be8..9e631b8 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -588,7 +588,6 @@ * protections. e.g. TSEG. */ void smm_region(void **start, size_t *size); -void smm_region_info(void **start, size_t *size); enum { /* SMM handler area. */ diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index 84f4729..c1d2aff 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -69,7 +69,7 @@ size_t handler_size; /* Initialize global tracking state. */ - smm_region_info(&smm_base, &smm_size); + smm_region(&smm_base, &smm_size); smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size); relo_attrs.smbase = (uint32_t)smm_base; diff --git a/src/soc/amd/picasso/ramtop.c b/src/soc/amd/picasso/ramtop.c index 8eb2e39..4ff4252 100644 --- a/src/soc/amd/picasso/ramtop.c +++ b/src/soc/amd/picasso/ramtop.c @@ -91,7 +91,7 @@ } } -void smm_region_info(void **start, size_t *size) +void smm_region(void **start, size_t *size) { *start = (void *)smm_region_start(); *size = smm_region_size(); diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 458886d..64c18d2 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -91,7 +91,7 @@ * when relocating the SMM handler as well as using the TSEG * region for other purposes. */ - smm_region_info(&smm_base, &smm_size); + smm_region(&smm_base, &smm_size); tseg_base = (uintptr_t)smm_base; postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK); diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 9961153..26d9f7f 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -69,7 +69,7 @@ size_t handler_size; /* Initialize global tracking state. */ - smm_region_info(&smm_base, &smm_size); + smm_region(&smm_base, &smm_size); smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size); relo_attrs.smbase = (uint32_t)smm_base; diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/stoneyridge/ramtop.c index 8eb2e39..4ff4252 100644 --- a/src/soc/amd/stoneyridge/ramtop.c +++ b/src/soc/amd/stoneyridge/ramtop.c @@ -91,7 +91,7 @@ } } -void smm_region_info(void **start, size_t *size) +void smm_region(void **start, size_t *size) { *start = (void *)smm_region_start(); *size = smm_region_size(); diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 4f38dbf..3c97e5e 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -176,7 +176,7 @@ * when relocating the SMM handler as well as using the TSEG * region for other purposes. */ - smm_region_info(&smm_base, &smm_size); + smm_region(&smm_base, &smm_size); tseg_base = (uintptr_t)smm_base; postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK); -- To view, visit https://review.coreboot.org/c/coreboot/+/34703 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I361fb0e02fd0bd92bb1e13fe84c898a1ac85aa40 Gerrit-Change-Number: 34703 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: intel/apollolake: Replace smm_region_info() with smm_region()
by Kyösti Mälkki (Code Review) 07 Aug '19

07 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34702 ) Change subject: intel/apollolake: Replace smm_region_info() with smm_region() ...................................................................... intel/apollolake: Replace smm_region_info() with smm_region() Implementation remains the same. Change-Id: I8483bb8e5bba66b4854597f58ddcfe59aac17ae0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/apollolake/cpu.c M src/soc/intel/apollolake/memmap.c M src/soc/intel/apollolake/romstage.c M src/soc/intel/common/block/smm/smm.c 4 files changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/34702/1 diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index f3aa40c..f402dfe 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -214,7 +214,7 @@ const uint32_t rmask = ~((1 << 12) - 1); /* Initialize global tracking state. */ - smm_region_info(&smm_base, &smm_size); + smm_region(&smm_base, &smm_size); smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size); relo_attrs.smbase = (uint32_t)smm_base; diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index a4101b7..3daac3c 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -43,6 +43,12 @@ return tolum; } +void smm_region(void **start, size_t *size) +{ + *start = (void *)sa_get_tseg_base(); + *size = sa_get_tseg_size(); +} + int smm_subregion(int sub, void **start, size_t *size) { uintptr_t sub_base; @@ -50,7 +56,7 @@ void *smm_base; const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; - smm_region_info(&smm_base, &sub_size); + smm_region(&smm_base, &sub_size); sub_base = (uintptr_t)smm_base; assert(sub_size > CONFIG_SMM_RESERVED_SIZE); diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 97e2f83..62eb1db 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -257,7 +257,7 @@ * when relocating the SMM handler as well as using the TSEG * region for other purposes. */ - smm_region_info(&smm_base, &smm_size); + smm_region(&smm_base, &smm_size); tseg_base = (uintptr_t)smm_base; postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK); diff --git a/src/soc/intel/common/block/smm/smm.c b/src/soc/intel/common/block/smm/smm.c index 8ccd13a..489462d 100644 --- a/src/soc/intel/common/block/smm/smm.c +++ b/src/soc/intel/common/block/smm/smm.c @@ -104,9 +104,3 @@ "d" (APM_CNT) ); } - -void smm_region_info(void **start, size_t *size) -{ - *start = (void *)sa_get_tseg_base(); - *size = sa_get_tseg_size(); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/34702 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8483bb8e5bba66b4854597f58ddcfe59aac17ae0 Gerrit-Change-Number: 34702 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86/smm: Promote smm_subregion()
by Kyösti Mälkki (Code Review) 07 Aug '19

07 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34701 ) Change subject: cpu/x86/smm: Promote smm_subregion() ...................................................................... cpu/x86/smm: Promote smm_subregion() No need to limit these declarations to FSP. Both PARALLEL_MP_INIT smm_relocate() and TSEG_STAGE_CACHE can be built on top of this. Change-Id: I7b0b9b8c8bee03aabe251c50c47dc42f6596e169 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/intel/fsp1_1/car.c D src/drivers/intel/fsp1_1/include/fsp/memmap.h M src/drivers/intel/fsp1_1/raminit.c M src/drivers/intel/fsp1_1/ramstage.c M src/drivers/intel/fsp1_1/stage_cache.c D src/drivers/intel/fsp2_0/include/fsp/memmap.h M src/include/cpu/x86/smm.h M src/soc/amd/picasso/cpu.c M src/soc/amd/picasso/include/soc/northbridge.h M src/soc/amd/picasso/ramtop.c M src/soc/amd/picasso/romstage.c M src/soc/amd/stoneyridge/cpu.c M src/soc/amd/stoneyridge/include/soc/northbridge.h M src/soc/amd/stoneyridge/ramtop.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/apollolake/cpu.c M src/soc/intel/apollolake/memmap.c M src/soc/intel/apollolake/romstage.c M src/soc/intel/braswell/cpu.c M src/soc/intel/braswell/memmap.c M src/soc/intel/braswell/northcluster.c M src/soc/intel/cannonlake/include/soc/smm.h M src/soc/intel/common/block/smm/smm.c M src/soc/intel/denverton_ns/cpu.c M src/soc/intel/denverton_ns/include/soc/smm.h M src/soc/intel/denverton_ns/memmap.c M src/soc/intel/denverton_ns/romstage.c M src/soc/intel/icelake/include/soc/smm.h M src/soc/intel/skylake/include/soc/smm.h M src/soc/intel/skylake/memmap.c M src/soc/intel/skylake/romstage/romstage_fsp20.c 31 files changed, 45 insertions(+), 159 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/34701/1 diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index 19eb041..1b6f62c 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -19,9 +19,9 @@ #include <commonlib/helpers.h> #include <cpu/intel/romstage.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/smm.h> #include <fsp/car.h> #include <fsp/util.h> -#include <fsp/memmap.h> #include <program_loading.h> /* platform_enter_postcar() determines the stack to use after diff --git a/src/drivers/intel/fsp1_1/include/fsp/memmap.h b/src/drivers/intel/fsp1_1/include/fsp/memmap.h deleted file mode 100644 index 3f3850f..0000000 --- a/src/drivers/intel/fsp1_1/include/fsp/memmap.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015-2016 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _COMMON_MEMMAP_H_ -#define _COMMON_MEMMAP_H_ - -#include <types.h> - -/* Fills in the arguments for the entire SMM region covered by chipset - * protections. e.g. TSEG. */ -void smm_region(void **start, size_t *size); - -enum { - /* SMM handler area. */ - SMM_SUBREGION_HANDLER, - /* SMM cache region. */ - SMM_SUBREGION_CACHE, - /* Chipset specific area. */ - SMM_SUBREGION_CHIPSET, - /* Total sub regions supported. */ - SMM_SUBREGION_NUM, -}; - -/* Fills in the start and size for the requested SMM subregion. Returns - * 0 on susccess, < 0 on failure. */ -int smm_subregion(int sub, void **start, size_t *size); - -#endif /* _COMMON_MEMMAP_H_ */ diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index 21f4ab9..2f53957 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -19,7 +19,7 @@ #include <cf9_reset.h> #include <commonlib/helpers.h> #include <console/console.h> -#include <fsp/memmap.h> +#include <cpu/x86/smm.h> #include <fsp/romstage.h> #include <fsp/util.h> #include <lib.h> /* hexdump */ diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index 52a886c..049dfd0 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -17,7 +17,7 @@ #include <bootmode.h> #include <arch/acpi.h> #include <console/console.h> -#include <fsp/memmap.h> +#include <cpu/x86/smm.h> #include <fsp/ramstage.h> #include <fsp/util.h> #include <lib.h> diff --git a/src/drivers/intel/fsp1_1/stage_cache.c b/src/drivers/intel/fsp1_1/stage_cache.c index 2d594e6..ab0c1c0 100644 --- a/src/drivers/intel/fsp1_1/stage_cache.c +++ b/src/drivers/intel/fsp1_1/stage_cache.c @@ -15,7 +15,7 @@ */ #include <console/console.h> -#include <fsp/memmap.h> +#include <cpu/x86/smm.h> #include <stage_cache.h> void stage_cache_external_region(void **base, size_t *size) diff --git a/src/drivers/intel/fsp2_0/include/fsp/memmap.h b/src/drivers/intel/fsp2_0/include/fsp/memmap.h deleted file mode 100644 index 3f3850f..0000000 --- a/src/drivers/intel/fsp2_0/include/fsp/memmap.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015-2016 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _COMMON_MEMMAP_H_ -#define _COMMON_MEMMAP_H_ - -#include <types.h> - -/* Fills in the arguments for the entire SMM region covered by chipset - * protections. e.g. TSEG. */ -void smm_region(void **start, size_t *size); - -enum { - /* SMM handler area. */ - SMM_SUBREGION_HANDLER, - /* SMM cache region. */ - SMM_SUBREGION_CACHE, - /* Chipset specific area. */ - SMM_SUBREGION_CHIPSET, - /* Total sub regions supported. */ - SMM_SUBREGION_NUM, -}; - -/* Fills in the start and size for the requested SMM subregion. Returns - * 0 on susccess, < 0 on failure. */ -int smm_subregion(int sub, void **start, size_t *size); - -#endif /* _COMMON_MEMMAP_H_ */ diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 3071106..edd1be8 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -583,4 +583,26 @@ void *backup_default_smm_area(void); void restore_default_smm_area(void *smm_save_area); +/* + * Fills in the arguments for the entire SMM region covered by chipset + * protections. e.g. TSEG. + */ +void smm_region(void **start, size_t *size); +void smm_region_info(void **start, size_t *size); + +enum { + /* SMM handler area. */ + SMM_SUBREGION_HANDLER, + /* SMM cache region. */ + SMM_SUBREGION_CACHE, + /* Chipset specific area. */ + SMM_SUBREGION_CHIPSET, + /* Total sub regions supported. */ + SMM_SUBREGION_NUM, +}; + +/* Fills in the start and size for the requested SMM subregion. Returns + * 0 on success, < 0 on failure. */ +int smm_subregion(int sub, void **start, size_t *size); + #endif /* CPU_X86_SMM_H */ diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index bee2b4b..84f4729 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -18,6 +18,7 @@ #include <cpu/x86/mp.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> +#include <cpu/x86/smm.h> #include <cpu/amd/msr.h> #include <cpu/x86/lapic.h> #include <device/device.h> diff --git a/src/soc/amd/picasso/include/soc/northbridge.h b/src/soc/amd/picasso/include/soc/northbridge.h index 65705b9..57373c9 100644 --- a/src/soc/amd/picasso/include/soc/northbridge.h +++ b/src/soc/amd/picasso/include/soc/northbridge.h @@ -99,29 +99,8 @@ #define NB_CAPABILITIES2 0x84 #define CMP_CAP_MASK 0xff -enum { - /* SMM handler area. */ - SMM_SUBREGION_HANDLER, - /* SMM cache region. */ - SMM_SUBREGION_CACHE, - /* Chipset specific area. */ - SMM_SUBREGION_CHIPSET, - /* Total sub regions supported. */ - SMM_SUBREGION_NUM, -}; - void amd_initcpuio(void); -/* - * Fills in the arguments for the entire SMM region covered by chipset - * protections. e.g. TSEG. - */ -void smm_region_info(void **start, size_t *size); -/* - * Fills in the start and size for the requested SMM subregion. Returns - * 0 on success, < 0 on failure. - */ -int smm_subregion(int sub, void **start, size_t *size); void domain_enable_resources(struct device *dev); void domain_set_resources(struct device *dev); void fam15_finalize(void *chip_info); diff --git a/src/soc/amd/picasso/ramtop.c b/src/soc/amd/picasso/ramtop.c index 7c855bb..8eb2e39 100644 --- a/src/soc/amd/picasso/ramtop.c +++ b/src/soc/amd/picasso/ramtop.c @@ -19,6 +19,7 @@ #include <stdint.h> #include <console/console.h> #include <cpu/x86/msr.h> +#include <cpu/x86/smm.h> #include <cpu/amd/msr.h> #include <cpu/amd/mtrr.h> #include <cbmem.h> diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 950b41f..458886d 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -19,6 +19,7 @@ #include <arch/acpi.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/smm.h> #include <cpu/amd/mtrr.h> #include <cbmem.h> #include <commonlib/helpers.h> diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index f751dc8..9961153 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -18,6 +18,7 @@ #include <cpu/x86/mp.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> +#include <cpu/x86/smm.h> #include <cpu/amd/msr.h> #include <cpu/x86/lapic.h> #include <device/device.h> diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h index 60a6ea2..a0d7ce8 100644 --- a/src/soc/amd/stoneyridge/include/soc/northbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h @@ -99,27 +99,6 @@ #define NB_CAPABILITIES2 0x84 #define CMP_CAP_MASK 0xff -enum { - /* SMM handler area. */ - SMM_SUBREGION_HANDLER, - /* SMM cache region. */ - SMM_SUBREGION_CACHE, - /* Chipset specific area. */ - SMM_SUBREGION_CHIPSET, - /* Total sub regions supported. */ - SMM_SUBREGION_NUM, -}; - -/* - * Fills in the arguments for the entire SMM region covered by chipset - * protections. e.g. TSEG. - */ -void smm_region_info(void **start, size_t *size); -/* - * Fills in the start and size for the requested SMM subregion. Returns - * 0 on success, < 0 on failure. - */ -int smm_subregion(int sub, void **start, size_t *size); void domain_enable_resources(struct device *dev); void domain_set_resources(struct device *dev); void fam15_finalize(void *chip_info); diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/stoneyridge/ramtop.c index 7c855bb..8eb2e39 100644 --- a/src/soc/amd/stoneyridge/ramtop.c +++ b/src/soc/amd/stoneyridge/ramtop.c @@ -19,6 +19,7 @@ #include <stdint.h> #include <console/console.h> #include <cpu/x86/msr.h> +#include <cpu/x86/smm.h> #include <cpu/amd/msr.h> #include <cpu/amd/mtrr.h> #include <cbmem.h> diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 000d100..4f38dbf 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -19,6 +19,7 @@ #include <arch/acpi.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/smm.h> #include <cpu/amd/mtrr.h> #include <cbmem.h> #include <commonlib/helpers.h> diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 625d956..f3aa40c 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -29,10 +29,10 @@ #include <cpu/intel/turbo.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/smm.h> #include <device/device.h> #include <device/pci.h> #include <fsp/api.h> -#include <fsp/memmap.h> #include <intelblocks/cpulib.h> #include <intelblocks/fast_spi.h> #include <intelblocks/mp_init.h> diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index 66f4dda..a4101b7 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -18,8 +18,8 @@ #include <assert.h> #include <cbmem.h> #include <console/console.h> +#include <cpu/x86/smm.h> #include <device/pci.h> -#include <fsp/memmap.h> #include <intelblocks/smm.h> #include <soc/systemagent.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 7b10222..97e2f83 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -27,10 +27,10 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/pae.h> #include <delay.h> +#include <cpu/x86/smm.h> #include <device/pci_def.h> #include <device/resource.h> #include <fsp/api.h> -#include <fsp/memmap.h> #include <fsp/util.h> #include <intelblocks/cpulib.h> #include <intelblocks/lpc_lib.h> diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index 5f86a11..bde4b1c 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -26,7 +26,6 @@ #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> -#include <fsp/memmap.h> #include <reg_script.h> #include <soc/iosf.h> #include <soc/msr.h> diff --git a/src/soc/intel/braswell/memmap.c b/src/soc/intel/braswell/memmap.c index a4692ce..69bbe58 100644 --- a/src/soc/intel/braswell/memmap.c +++ b/src/soc/intel/braswell/memmap.c @@ -15,7 +15,7 @@ */ #include <cbmem.h> -#include <fsp/memmap.h> +#include <cpu/x86/smm.h> #include <soc/iosf.h> #include <soc/smm.h> diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c index 9267448..e37e0d6 100644 --- a/src/soc/intel/braswell/northcluster.c +++ b/src/soc/intel/braswell/northcluster.c @@ -21,8 +21,8 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <fsp/memmap.h> #include <cpu/x86/lapic.h> +#include <cpu/x86/smm.h> #include <fsp/util.h> #include <soc/iomap.h> #include <soc/iosf.h> diff --git a/src/soc/intel/cannonlake/include/soc/smm.h b/src/soc/intel/cannonlake/include/soc/smm.h index 605cc99..bafcbd0 100644 --- a/src/soc/intel/cannonlake/include/soc/smm.h +++ b/src/soc/intel/cannonlake/include/soc/smm.h @@ -19,7 +19,7 @@ #include <stdint.h> #include <cpu/x86/msr.h> -#include <fsp/memmap.h> +#include <cpu/x86/smm.h> #include <soc/gpio.h> struct ied_header { diff --git a/src/soc/intel/common/block/smm/smm.c b/src/soc/intel/common/block/smm/smm.c index a2a7c16..8ccd13a 100644 --- a/src/soc/intel/common/block/smm/smm.c +++ b/src/soc/intel/common/block/smm/smm.c @@ -18,7 +18,6 @@ #include <bootstate.h> #include <console/console.h> #include <cpu/x86/smm.h> -#include <fsp/memmap.h> #include <intelblocks/pmclib.h> #include <intelblocks/smm.h> #include <intelblocks/systemagent.h> diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index fc1024a..d6ddcc0 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -21,6 +21,7 @@ #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/smm.h> #include <cpu/intel/turbo.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/soc/intel/denverton_ns/include/soc/smm.h b/src/soc/intel/denverton_ns/include/soc/smm.h index ca01cf8..a020891 100644 --- a/src/soc/intel/denverton_ns/include/soc/smm.h +++ b/src/soc/intel/denverton_ns/include/soc/smm.h @@ -24,25 +24,6 @@ uint32_t smrr_mask; }; -/* Fills in the arguments for the entire SMM region covered by chipset - * protections. e.g. TSEG. */ -void smm_region(void **start, size_t *size); - -enum { - /* SMM handler area. */ - SMM_SUBREGION_HANDLER, - /* SMM cache region. */ - SMM_SUBREGION_CACHE, - /* Chipset specific area. */ - SMM_SUBREGION_CHIPSET, - /* Total sub regions supported. */ - SMM_SUBREGION_NUM, -}; - -/* Fills in the start and size for the requested SMM subregion. Returns - * 0 on success, < 0 on failure. */ -int smm_subregion(int sub, void **start, size_t *size); - #if !defined(__PRE_RAM__) && !defined(__SMM___) #include <stdint.h> void southcluster_smm_clear_state(void); diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c index 2561922..d94d1f3 100644 --- a/src/soc/intel/denverton_ns/memmap.c +++ b/src/soc/intel/denverton_ns/memmap.c @@ -16,12 +16,12 @@ #include <cbmem.h> #include <assert.h> +#include <cpu/x86/smm.h> #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> #include <soc/pci_devs.h> #include <soc/systemagent.h> -#include <soc/smm.h> #include <lib.h> /* Returns base of requested region encoded in the system agent. */ diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index 2ad78a0..6950620 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -20,6 +20,7 @@ #include <cf9_reset.h> #include <console/console.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/smm.h> #include <device/pci_ops.h> #include <soc/fiamux.h> #include <device/mmio.h> @@ -29,7 +30,6 @@ #include <soc/pmc.h> #include <soc/romstage.h> #include <soc/smbus.h> -#include <soc/smm.h> #include <soc/soc_util.h> #include <soc/hob_mem.h> diff --git a/src/soc/intel/icelake/include/soc/smm.h b/src/soc/intel/icelake/include/soc/smm.h index 2887c5b..974aec1 100644 --- a/src/soc/intel/icelake/include/soc/smm.h +++ b/src/soc/intel/icelake/include/soc/smm.h @@ -18,7 +18,7 @@ #include <stdint.h> #include <cpu/x86/msr.h> -#include <fsp/memmap.h> +#include <cpu/x86/smm.h> #include <soc/gpio.h> struct ied_header { diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h index 9d8e24e..406b937 100644 --- a/src/soc/intel/skylake/include/soc/smm.h +++ b/src/soc/intel/skylake/include/soc/smm.h @@ -19,7 +19,7 @@ #include <stdint.h> #include <cpu/x86/msr.h> -#include <fsp/memmap.h> +#include <cpu/x86/smm.h> #include <intelblocks/smihandler.h> #include <soc/gpio.h> diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index d2c223e..8639a93 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -18,9 +18,9 @@ #include <device/mmio.h> #include <cbmem.h> #include <console/console.h> +#include <cpu/x86/smm.h> #include <device/device.h> #include <device/pci.h> -#include <fsp/memmap.h> #include <intelblocks/ebda.h> #include <intelblocks/systemagent.h> #include <soc/msr.h> diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index b6e3551..5e957ac 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -18,11 +18,11 @@ #include <assert.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> +#include <cpu/x86/smm.h> #include <cbmem.h> #include <console/console.h> #include <device/pci_def.h> #include <fsp/util.h> -#include <fsp/memmap.h> #include <intelblocks/pmclib.h> #include <memory_info.h> #include <smbios.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/34701 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b0b9b8c8bee03aabe251c50c47dc42f6596e169 Gerrit-Change-Number: 34701 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: northbridge/intel: Rename ram_calc.c to memmap.c
by Kyösti Mälkki (Code Review) 07 Aug '19

07 Aug '19

Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34699 ) Change subject: northbridge/intel: Rename ram_calc.c to memmap.c ...................................................................... northbridge/intel: Rename ram_calc.c to memmap.c Use a name consistent with the more recent soc/intel. Change-Id: Ie69583f28f384eb49517203e1c3867f27e6272de Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34699 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/gm45/Makefile.inc R src/northbridge/intel/gm45/memmap.c M src/northbridge/intel/haswell/Makefile.inc R src/northbridge/intel/haswell/memmap.c M src/northbridge/intel/i440bx/Makefile.inc R src/northbridge/intel/i440bx/memmap.c M src/northbridge/intel/i945/Makefile.inc R src/northbridge/intel/i945/memmap.c M src/northbridge/intel/nehalem/Makefile.inc R src/northbridge/intel/nehalem/memmap.c M src/northbridge/intel/pineview/Makefile.inc R src/northbridge/intel/pineview/memmap.c M src/northbridge/intel/sandybridge/Makefile.inc R src/northbridge/intel/sandybridge/memmap.c M src/northbridge/intel/x4x/Makefile.inc R src/northbridge/intel/x4x/memmap.c 16 files changed, 24 insertions(+), 24 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/northbridge/intel/gm45/Makefile.inc b/src/northbridge/intel/gm45/Makefile.inc index b59a7c3..0ab1c94 100644 --- a/src/northbridge/intel/gm45/Makefile.inc +++ b/src/northbridge/intel/gm45/Makefile.inc @@ -25,18 +25,18 @@ romstage-y += thermal.c romstage-y += igd.c romstage-y += pm.c -romstage-y += ram_calc.c +romstage-y += memmap.c romstage-y += iommu.c romstage-y += romstage.c ramstage-y += acpi.c -ramstage-y += ram_calc.c +ramstage-y += memmap.c ramstage-y += northbridge.c ramstage-y += gma.c smm-y += ../../../cpu/x86/lapic/apic_timer.c -postcar-y += ram_calc.c +postcar-y += memmap.c endif diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/memmap.c similarity index 100% rename from src/northbridge/intel/gm45/ram_calc.c rename to src/northbridge/intel/gm45/memmap.c diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc index ca1c04f..b986336 100644 --- a/src/northbridge/intel/haswell/Makefile.inc +++ b/src/northbridge/intel/haswell/Makefile.inc @@ -17,14 +17,14 @@ bootblock-y += bootblock.c -ramstage-y += ram_calc.c +ramstage-y += memmap.c ramstage-y += northbridge.c ramstage-y += gma.c ramstage-y += acpi.c ramstage-y += minihd.c -romstage-y += ram_calc.c +romstage-y += memmap.c romstage-y += raminit.c romstage-y += early_init.c romstage-y += report_platform.c @@ -37,6 +37,6 @@ mrc.bin-position := 0xfffa0000 mrc.bin-type := mrc -postcar-y += ram_calc.c +postcar-y += memmap.c endif diff --git a/src/northbridge/intel/haswell/ram_calc.c b/src/northbridge/intel/haswell/memmap.c similarity index 100% rename from src/northbridge/intel/haswell/ram_calc.c rename to src/northbridge/intel/haswell/memmap.c diff --git a/src/northbridge/intel/i440bx/Makefile.inc b/src/northbridge/intel/i440bx/Makefile.inc index d41f65d..2c503c6 100644 --- a/src/northbridge/intel/i440bx/Makefile.inc +++ b/src/northbridge/intel/i440bx/Makefile.inc @@ -17,12 +17,12 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I440BX),y) ramstage-y += northbridge.c -ramstage-y += ram_calc.c +ramstage-y += memmap.c romstage-y += raminit.c romstage-$(CONFIG_DEBUG_RAM_SETUP) += debug.c -romstage-y += ram_calc.c +romstage-y += memmap.c -postcar-y += ram_calc.c +postcar-y += memmap.c endif diff --git a/src/northbridge/intel/i440bx/ram_calc.c b/src/northbridge/intel/i440bx/memmap.c similarity index 100% rename from src/northbridge/intel/i440bx/ram_calc.c rename to src/northbridge/intel/i440bx/memmap.c diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc index ffeabdc..47b4c51 100644 --- a/src/northbridge/intel/i945/Makefile.inc +++ b/src/northbridge/intel/i945/Makefile.inc @@ -15,12 +15,12 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I945),y) -ramstage-y += ram_calc.c +ramstage-y += memmap.c ramstage-y += northbridge.c ramstage-y += gma.c ramstage-y += acpi.c -romstage-y += ram_calc.c +romstage-y += memmap.c romstage-y += raminit.c romstage-y += early_init.c romstage-y += errata.c @@ -29,6 +29,6 @@ smm-y += udelay.c -postcar-y += ram_calc.c +postcar-y += memmap.c endif diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/memmap.c similarity index 100% rename from src/northbridge/intel/i945/ram_calc.c rename to src/northbridge/intel/i945/memmap.c diff --git a/src/northbridge/intel/nehalem/Makefile.inc b/src/northbridge/intel/nehalem/Makefile.inc index c0d46c9..52374ac 100644 --- a/src/northbridge/intel/nehalem/Makefile.inc +++ b/src/northbridge/intel/nehalem/Makefile.inc @@ -15,20 +15,20 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_NEHALEM),y) -ramstage-y += ram_calc.c +ramstage-y += memmap.c ramstage-y += northbridge.c ramstage-y += smi.c ramstage-y += gma.c ramstage-y += acpi.c -romstage-y += ram_calc.c +romstage-y += memmap.c romstage-y += raminit.c romstage-y += early_init.c romstage-y += ../../../arch/x86/walkcbfs.S smm-y += finalize.c -postcar-y += ram_calc.c +postcar-y += memmap.c endif diff --git a/src/northbridge/intel/nehalem/ram_calc.c b/src/northbridge/intel/nehalem/memmap.c similarity index 100% rename from src/northbridge/intel/nehalem/ram_calc.c rename to src/northbridge/intel/nehalem/memmap.c diff --git a/src/northbridge/intel/pineview/Makefile.inc b/src/northbridge/intel/pineview/Makefile.inc index 8348771..81ee783 100644 --- a/src/northbridge/intel/pineview/Makefile.inc +++ b/src/northbridge/intel/pineview/Makefile.inc @@ -19,16 +19,16 @@ bootblock-y += ../../../cpu/x86/early_reset.S bootblock-y += bootblock.c -ramstage-y += ram_calc.c +ramstage-y += memmap.c ramstage-y += northbridge.c ramstage-y += gma.c ramstage-y += acpi.c romstage-y += romstage.c -romstage-y += ram_calc.c +romstage-y += memmap.c romstage-y += raminit.c romstage-y += early_init.c -postcar-y += ram_calc.c +postcar-y += memmap.c endif diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/memmap.c similarity index 100% rename from src/northbridge/intel/pineview/ram_calc.c rename to src/northbridge/intel/pineview/memmap.c diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index 8a0b67b..77d1fdb 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -15,14 +15,14 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE),y) -ramstage-y += ram_calc.c +ramstage-y += memmap.c ramstage-y += northbridge.c ramstage-y += pcie.c ramstage-y += gma.c ramstage-y += acpi.c -romstage-y += ram_calc.c +romstage-y += memmap.c ramstage-y += common.c romstage-y += common.c @@ -48,6 +48,6 @@ smm-y += finalize.c -postcar-y += ram_calc.c +postcar-y += memmap.c endif diff --git a/src/northbridge/intel/sandybridge/ram_calc.c b/src/northbridge/intel/sandybridge/memmap.c similarity index 100% rename from src/northbridge/intel/sandybridge/ram_calc.c rename to src/northbridge/intel/sandybridge/memmap.c diff --git a/src/northbridge/intel/x4x/Makefile.inc b/src/northbridge/intel/x4x/Makefile.inc index 3118b09..b7fd2fe 100644 --- a/src/northbridge/intel/x4x/Makefile.inc +++ b/src/northbridge/intel/x4x/Makefile.inc @@ -19,16 +19,16 @@ romstage-y += early_init.c romstage-y += raminit.c romstage-y += raminit_ddr23.c -romstage-y += ram_calc.c +romstage-y += memmap.c romstage-y += rcven.c romstage-y += raminit_tables.c romstage-y += dq_dqs.c ramstage-y += acpi.c -ramstage-y += ram_calc.c +ramstage-y += memmap.c ramstage-y += gma.c ramstage-y += northbridge.c -postcar-y += ram_calc.c +postcar-y += memmap.c endif diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/memmap.c similarity index 100% rename from src/northbridge/intel/x4x/ram_calc.c rename to src/northbridge/intel/x4x/memmap.c -- To view, visit https://review.coreboot.org/c/coreboot/+/34699 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie69583f28f384eb49517203e1c3867f27e6272de Gerrit-Change-Number: 34699 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: intel/fsp_rangeley: Rename raminit.c to memmap.c
by Kyösti Mälkki (Code Review) 07 Aug '19

07 Aug '19

Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34698 ) Change subject: intel/fsp_rangeley: Rename raminit.c to memmap.c ...................................................................... intel/fsp_rangeley: Rename raminit.c to memmap.c Use a name consistent with the more recent soc/intel. Change-Id: I704d7cb637e4e12039ade99f57e10af794c8be97 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34698 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: David Guckian --- M src/northbridge/intel/fsp_rangeley/Makefile.inc R src/northbridge/intel/fsp_rangeley/memmap.c 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved David Guckian: Looks good to me, but someone else must approve diff --git a/src/northbridge/intel/fsp_rangeley/Makefile.inc b/src/northbridge/intel/fsp_rangeley/Makefile.inc index f9bf050..a2f8054 100644 --- a/src/northbridge/intel/fsp_rangeley/Makefile.inc +++ b/src/northbridge/intel/fsp_rangeley/Makefile.inc @@ -18,12 +18,12 @@ subdirs-y += fsp ramstage-y += northbridge.c -ramstage-y += raminit.c +ramstage-y += memmap.c ramstage-y += acpi.c ramstage-y += port_access.c -romstage-y += raminit.c +romstage-y += memmap.c romstage-y += ../../../arch/x86/walkcbfs.S romstage-y += port_access.c diff --git a/src/northbridge/intel/fsp_rangeley/raminit.c b/src/northbridge/intel/fsp_rangeley/memmap.c similarity index 100% rename from src/northbridge/intel/fsp_rangeley/raminit.c rename to src/northbridge/intel/fsp_rangeley/memmap.c -- To view, visit https://review.coreboot.org/c/coreboot/+/34698 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I704d7cb637e4e12039ade99f57e10af794c8be97 Gerrit-Change-Number: 34698 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: intel/icelake,skylake,cannonlake: Drop unused parameter
by Kyösti Mälkki (Code Review) 07 Aug '19

07 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34697 ) Change subject: intel/icelake,skylake,cannonlake: Drop unused parameter ...................................................................... intel/icelake,skylake,cannonlake: Drop unused parameter Change-Id: I0900c3b893d72063cc8df5d8ac370cf9d54df17a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/cannonlake/smmrelocate.c M src/soc/intel/icelake/smmrelocate.c M src/soc/intel/skylake/smmrelocate.c 3 files changed, 6 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/34697/1 diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c index 980702f..3ee94e7 100644 --- a/src/soc/intel/cannonlake/smmrelocate.c +++ b/src/soc/intel/cannonlake/smmrelocate.c @@ -171,8 +171,7 @@ write_smrr(relo_params); } -static void fill_in_relocation_params(struct device *dev, - struct smm_relocation_params *params) +static void fill_in_relocation_params(struct smm_relocation_params *params) { void *handler_base; size_t handler_size; @@ -256,11 +255,9 @@ void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { - struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); - printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - fill_in_relocation_params(dev, &smm_reloc_params); + fill_in_relocation_params(&smm_reloc_params); if (smm_reloc_params.ied_size) setup_ied_area(&smm_reloc_params); diff --git a/src/soc/intel/icelake/smmrelocate.c b/src/soc/intel/icelake/smmrelocate.c index 63048eb..9630844 100644 --- a/src/soc/intel/icelake/smmrelocate.c +++ b/src/soc/intel/icelake/smmrelocate.c @@ -170,8 +170,7 @@ write_smrr(relo_params); } -static void fill_in_relocation_params(struct device *dev, - struct smm_relocation_params *params) +static void fill_in_relocation_params(struct smm_relocation_params *params) { void *handler_base; size_t handler_size; @@ -255,11 +254,9 @@ void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { - struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); - printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - fill_in_relocation_params(dev, &smm_reloc_params); + fill_in_relocation_params(&smm_reloc_params); if (smm_reloc_params.ied_size) setup_ied_area(&smm_reloc_params); diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c index 816e1a8..6e2cf98 100644 --- a/src/soc/intel/skylake/smmrelocate.c +++ b/src/soc/intel/skylake/smmrelocate.c @@ -180,8 +180,7 @@ write_smrr(relo_params); } -static void fill_in_relocation_params(struct device *dev, - struct smm_relocation_params *params) +static void fill_in_relocation_params(struct smm_relocation_params *params) { void *handler_base; size_t handler_size; @@ -265,11 +264,9 @@ void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { - struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); - printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - fill_in_relocation_params(dev, &smm_reloc_params); + fill_in_relocation_params(&smm_reloc_params); if (smm_reloc_params.ied_size) setup_ied_area(&smm_reloc_params); -- To view, visit https://review.coreboot.org/c/coreboot/+/34697 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0900c3b893d72063cc8df5d8ac370cf9d54df17a Gerrit-Change-Number: 34697 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit August 2019