coreboot-gerrit August 2019

coreboot-gerrit@coreboot.org

1 participants
1942 discussions

Change in coreboot[master]: dram: Add basic DDR4 SPD parsing
by Martin Roth (Code Review) 07 Aug '19

07 Aug '19

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34680 ) Change subject: dram: Add basic DDR4 SPD parsing ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/34680/3/src/device/dram/ddr4.c File src/device/dram/ddr4.c: https://review.coreboot.org/c/coreboot/+/34680/3/src/device/dram/ddr4.c@54 PS3, Line 54: ((1 << 4) - 1) Maybe put these in the header file? #define LOW_NIBBLE_MASK ((1 << 4) - 1) #define LOW_3_BIT_MASK ((1 << 4) - 1) or #define 4_BIT_MASK ((1 << 4) - 1) #define 3_BIT_MASK ((1 << 3) - 1) -- To view, visit https://review.coreboot.org/c/coreboot/+/34680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3befbc55cf37e1018baa432cb2f03743b929211 Gerrit-Change-Number: 34680 Gerrit-PatchSet: 4 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 07 Aug 2019 20:57:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/fsp_broadwell_de: Populate SMBIOS tables with memory inform...
by build bot (Jenkins) (Code Review) 07 Aug '19

07 Aug '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34681 ) Change subject: soc/intel/fsp_broadwell_de: Populate SMBIOS tables with memory information ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/34681/4/src/soc/intel/fsp_broadwel… File src/soc/intel/fsp_broadwell_de/romstage/memory.c: https://review.coreboot.org/c/coreboot/+/34681/4/src/soc/intel/fsp_broadwel… PS4, Line 40: SPD_SLAVE_ADDR(1, 0), SPD_SLAVE_ADDR(1, 1)}}; space required after that close brace '}' -- To view, visit https://review.coreboot.org/c/coreboot/+/34681 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1162eb4484dab46f1ab9fe3426eecc4d9378e8e2 Gerrit-Change-Number: 34681 Gerrit-PatchSet: 4 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 07 Aug 2019 20:14:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: dram: Add basic DDR4 SPD parsing
by Andrey Petrov (Code Review) 07 Aug '19

07 Aug '19

Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34680 ) Change subject: dram: Add basic DDR4 SPD parsing ...................................................................... Patch Set 4: (4 comments) https://review.coreboot.org/c/coreboot/+/34680/3/src/device/dram/ddr4.c File src/device/dram/ddr4.c: https://review.coreboot.org/c/coreboot/+/34680/3/src/device/dram/ddr4.c@45 PS3, Line 45: > start with spd[0] to get "Bytes Total" and "Bytes used" Ack https://review.coreboot.org/c/coreboot/+/34680/3/src/device/dram/ddr4.c@46 PS3, Line 46: DDR3 > DDR4 Ack https://review.coreboot.org/c/coreboot/+/34680/3/src/device/dram/ddr4.c@80 PS3, Line 80: dimm->manufacturer_id = (spd[351] << 8) | spd[350]; > check if 351 is within "Bytes used" in spd[0] I addressed this in follow up patch that implements crc checks as well: 34781 https://review.coreboot.org/c/coreboot/+/34680/3/src/device/dram/ddr4.c@85 PS3, Line 85: memcpy(dimm->part_number, &spd[329], SPD_DDR4_PART_LEN); > make sure those are properly null terminated but this is already done on next line -- To view, visit https://review.coreboot.org/c/coreboot/+/34680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3befbc55cf37e1018baa432cb2f03743b929211 Gerrit-Change-Number: 34680 Gerrit-PatchSet: 4 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 07 Aug 2019 20:03:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/skylake: Use new power-failure-state API
by Tim Wawrzynczak (Code Review) 07 Aug '19

07 Aug '19

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34725 ) Change subject: soc/intel/skylake: Use new power-failure-state API ...................................................................... Patch Set 3: (2 comments) https://review.coreboot.org/c/coreboot/+/34725/3/src/soc/intel/skylake/pmc.c File src/soc/intel/skylake/pmc.c: https://review.coreboot.org/c/coreboot/+/34725/3/src/soc/intel/skylake/pmc.… PS3, Line 60: 1 A symbolic constant would be nice https://review.coreboot.org/c/coreboot/+/34725/3/src/soc/intel/skylake/pmc.… PS3, Line 62: 1 same -- To view, visit https://review.coreboot.org/c/coreboot/+/34725 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie72753764ecd876e6cb999fa0074d1114ae5efcf Gerrit-Change-Number: 34725 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Wed, 07 Aug 2019 19:03:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common: Implement power-failure-state handling
by Nico Huber (Code Review) 07 Aug '19

07 Aug '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34724 ) Change subject: soc/intel/common: Implement power-failure-state handling ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/34724/4/src/soc/intel/common/block… File src/soc/intel/common/block/pmc/pmclib.c: https://review.coreboot.org/c/coreboot/+/34724/4/src/soc/intel/common/block… PS4, Line 602: state == MAINBOARD_POWER_STATE_ON > So, if the state is MAINBOARD_POWER_STATE_PREVIOUS, always set to false? For the moment, yes. I tried to keep it close to the current behavior and implement PREVIOUS properly later. See CB:34728. I could also squash things or add an interim `return; /* TBD */` here for PREVIOUS. The result after the patch series should be the same, though. -- To view, visit https://review.coreboot.org/c/coreboot/+/34724 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6970a79d9b95373c2855f4c92232d2aa05963bb Gerrit-Change-Number: 34724 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Aug 2019 18:58:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/hatch: Kohaku: Re-setup dual-routing of EMR_GARAGE_DET
by Tim Wawrzynczak (Code Review) 07 Aug '19

07 Aug '19

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34780 ) Change subject: mb/google/hatch: Kohaku: Re-setup dual-routing of EMR_GARAGE_DET ...................................................................... mb/google/hatch: Kohaku: Re-setup dual-routing of EMR_GARAGE_DET The pinctrl driver in the linux kernel automatically turns off SCI routing for all GPIOs exported via ACPI, so this patch sets up dual-routing of the EMR_GARAGE_DET signal so that one can be used for IRQs and one for the SCI wake. Change-Id: Iadeb4502c5a98a72ba651bdcad626609656c196f Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/hatch/variants/baseboard/gpio.c M src/mainboard/google/hatch/variants/kohaku/gpio.c M src/mainboard/google/hatch/variants/kohaku/overridetree.cb 3 files changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/34780/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 5666d1c..38d44f3 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -30,7 +30,7 @@ PAD_CFG_GPI_INT(GPP_A6, NONE, PLTRST, LEVEL), /* A7 : PP3300_SOC_A */ PAD_NC(GPP_A7, NONE), - /* A8 : PEN_GARAGE_DET_L */ + /* A8 : PEN_GARAGE_DET_L (wake) */ PAD_CFG_GPI_GPIO_DRIVER_SCI(GPP_A8, NONE, DEEP, LEVEL, NONE), /* A9 : ESPI_CLK */ /* A10 : FPMCU_PCH_BOOT1 */ diff --git a/src/mainboard/google/hatch/variants/kohaku/gpio.c b/src/mainboard/google/hatch/variants/kohaku/gpio.c index bc9df38..c157178 100644 --- a/src/mainboard/google/hatch/variants/kohaku/gpio.c +++ b/src/mainboard/google/hatch/variants/kohaku/gpio.c @@ -25,6 +25,8 @@ PAD_NC(GPP_A6, NONE), /* A10 : PEN_RESET_ODL */ PAD_CFG_GPO(GPP_A10, 1, DEEP), + /* A16 : EMR_GARAGE_DET (notification) */ + PAD_CFG_GPI_APIC(GPP_A16, NONE, PLTRST, LEVEL, NONE), /* A17 : PIRQA# ==> NC */ PAD_NC(GPP_A17, NONE), /* A18 : ISH_GP0 ==> NC */ diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index 57429ad..13025c8 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -112,7 +112,8 @@ end chip drivers/generic/gpio_keys register "name" = ""PENH"" - register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_A8)" + # GPP_A16 is the IRQ source, and GPP_A8 is the wake source + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_A16)" register "key.wake" = "GPE0_DW0_08" register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" register "key.dev_name" = ""EJCT"" -- To view, visit https://review.coreboot.org/c/coreboot/+/34780 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iadeb4502c5a98a72ba651bdcad626609656c196f Gerrit-Change-Number: 34780 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: NOT_FOR_MERGE: soc/amd/picasso: Remove FSP-S temporarily
by Marshall Dawson (Code Review) 07 Aug '19

07 Aug '19

Hello Martin Roth, Furquan Shaikh, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/34428 to review the following change. Change subject: NOT_FOR_MERGE: soc/amd/picasso: Remove FSP-S temporarily ...................................................................... NOT_FOR_MERGE: soc/amd/picasso: Remove FSP-S temporarily Change-Id: I090fec731bd70afbf0347cbff087586f31d1ad5b Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/picasso/chip.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/34428/1 diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index f34e696..31ed922 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -118,7 +118,7 @@ static void soc_init(void *chip_info) { - fsp_silicon_init(acpi_is_wakeup_s3()); + // fsp_silicon_init(acpi_is_wakeup_s3()); northbridge_init(); southbridge_init(chip_info); -- To view, visit https://review.coreboot.org/c/coreboot/+/34428 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I090fec731bd70afbf0347cbff087586f31d1ad5b Gerrit-Change-Number: 34428 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: mb/google/hatch: Kohaku: Add touchscreen controller to device tree
by Tim Wawrzynczak (Code Review) 07 Aug '19

07 Aug '19

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34763 ) Change subject: mb/google/hatch: Kohaku: Add touchscreen controller to device tree ...................................................................... mb/google/hatch: Kohaku: Add touchscreen controller to device tree The touchscreen controller was never added to the device tree, and the next board rev will have this IC connected. Set it up in the device tree with conservative power resource timings from the datasheet. BUG=b:138869702 BRANCH=none TEST=compiles; current board rev does not have touch IC Change-Id: I759fb32f31c8eee0e6bd664c6a82308354ef5d08 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/hatch/variants/kohaku/overridetree.cb 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/34763/1 diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index b3ae1bc..2bbb72d 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -81,6 +81,19 @@ end end # I2C 0 + device pci 15.1 on + chip drivers/i2c/generic + register "hid" = ""ATML0001"" + register "desc" = ""Atmel Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "reset_delay_ms" = "10" + register "has_power_resource" = "1" + register "disable_gpio_export_in_crs" = "1" + device i2c 4b on end + end + end # I2C #1 + device pci 15.2 on chip drivers/i2c/hid register "generic.hid" = ""WCOM50C1"" -- To view, visit https://review.coreboot.org/c/coreboot/+/34763 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I759fb32f31c8eee0e6bd664c6a82308354ef5d08 Gerrit-Change-Number: 34763 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

4 12

Change in coreboot[master]: soc/intel/common: Implement power-failure-state handling
by Furquan Shaikh (Code Review) 07 Aug '19

07 Aug '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34724 ) Change subject: soc/intel/common: Implement power-failure-state handling ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/34724/4/src/soc/intel/common/block… File src/soc/intel/common/block/pmc/pmclib.c: https://review.coreboot.org/c/coreboot/+/34724/4/src/soc/intel/common/block… PS4, Line 602: state == MAINBOARD_POWER_STATE_ON So, if the state is MAINBOARD_POWER_STATE_PREVIOUS, always set to false? -- To view, visit https://review.coreboot.org/c/coreboot/+/34724 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6970a79d9b95373c2855f4c92232d2aa05963bb Gerrit-Change-Number: 34724 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Aug 2019 17:43:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/hatch: Kohaku: Add digitizer enable GPIO to device tree
by Tim Wawrzynczak (Code Review) 07 Aug '19

07 Aug '19

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34766 ) Change subject: mb/google/hatch: Kohaku: Add digitizer enable GPIO to device tree ...................................................................... mb/google/hatch: Kohaku: Add digitizer enable GPIO to device tree The enable GPIOs for several devices were shuffled around, and this signal should now be used. Change-Id: I9b0bd768cc8d9810fad6fd8a01f2a2635313008e Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/hatch/variants/kohaku/overridetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/34766/1 diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index 31f6af2..fe5cff3 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -103,6 +103,8 @@ register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A10)" register "generic.reset_delay_ms" = "1" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C15)" + register "generic.enable_delay_ms" = "1" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x1" device i2c 0x09 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/34766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b0bd768cc8d9810fad6fd8a01f2a2635313008e Gerrit-Change-Number: 34766 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

4 4

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit August 2019