Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34770 )
Change subject: soc/mediatek: dsi: Unify format to bpp conversion
......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34770/4/src/soc/mediatek/common/ds…
File src/soc/mediatek/common/dsi.c:
https://review.coreboot.org/c/coreboot/+/34770/4/src/soc/mediatek/common/ds…
PS4, Line 128: bytes_per_pixel = mtk_dsi_get_bits_per_pixel(format) / 8;
Is this supposed to be the ceiling of the division?
For MIPI_DSI_FMT_RGB666 the result was 3 but is now 2.
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ibd405220b73859e5592c68f498af07eef8d7edbc
Gerrit-Change-Number: 34770
Gerrit-PatchSet: 4
Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org>
Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: You-Cheng Syu <youcheng(a)google.com>
Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Reviewer: jitao shi <jitao.shi(a)mediatek.com>
Gerrit-Reviewer: yongqiang niu <yongqiang.niu(a)mediatek.com>
Gerrit-Comment-Date: Thu, 08 Aug 2019 01:49:06 +0000
Gerrit-HasComments: Yes
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Gerrit-MessageType: comment
Asami Doi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33387
Change subject: mainboard/emulation/qemu-aarch64: Add new board for ARMv8
......................................................................
mainboard/emulation/qemu-aarch64: Add new board for ARMv8
This CL adds new board, QEMU/AArch64, for ARMv8. The machine supported
is virt which is a QEMU 2.8 ARM virtual machine. The default CPU of
qemu-system-aarch64 is Cortex-a15, so you need to specify a 64-bit cpu
via a flag.
To execute:
$ qemu-system-aarch64 -M virt -cpu cortex-a53 \
-bios build/coreboot.rom -nographic
Change-Id: Id7c0831b1ecf08785b4ec8139d809bad9b3e1eec
Signed-off-by: Asami Doi <doiasami1219(a)gmail.com>
---
M src/cpu/armltd/Kconfig
M src/cpu/armltd/Makefile.inc
A src/cpu/armltd/cortex-a53/Kconfig
A src/mainboard/emulation/qemu-aarch64/Kconfig
A src/mainboard/emulation/qemu-aarch64/Kconfig.name
A src/mainboard/emulation/qemu-aarch64/Makefile.inc
A src/mainboard/emulation/qemu-aarch64/board_info.txt
A src/mainboard/emulation/qemu-aarch64/cbmem.c
A src/mainboard/emulation/qemu-aarch64/devicetree.cb
A src/mainboard/emulation/qemu-aarch64/mainboard.c
A src/mainboard/emulation/qemu-aarch64/mainboard.h
A src/mainboard/emulation/qemu-aarch64/media.c
A src/mainboard/emulation/qemu-aarch64/memlayout.ld
A src/mainboard/emulation/qemu-aarch64/mmio.c
A src/mainboard/emulation/qemu-aarch64/timer.c
15 files changed, 408 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/33387/1
diff --git a/src/cpu/armltd/Kconfig b/src/cpu/armltd/Kconfig
index af0c5c5..fc01735 100644
--- a/src/cpu/armltd/Kconfig
+++ b/src/cpu/armltd/Kconfig
@@ -1 +1,2 @@
source src/cpu/armltd/cortex-a9/Kconfig
+source src/cpu/armltd/cortex-a53/Kconfig
diff --git a/src/cpu/armltd/Makefile.inc b/src/cpu/armltd/Makefile.inc
index 014742f..cd6acf1 100644
--- a/src/cpu/armltd/Makefile.inc
+++ b/src/cpu/armltd/Makefile.inc
@@ -1 +1,2 @@
subdirs-$(CONFIG_CPU_ARMLTD_CORTEX_A9) += cortex-a9
+subdirs-$(CONFIG_CPU_ARMLTD_CORTEX_A53) += cortex-a53
diff --git a/src/cpu/armltd/cortex-a53/Kconfig b/src/cpu/armltd/cortex-a53/Kconfig
new file mode 100644
index 0000000..1cbfc33
--- /dev/null
+++ b/src/cpu/armltd/cortex-a53/Kconfig
@@ -0,0 +1,10 @@
+config CPU_ARMLTD_CORTEX_A53
+ bool
+ select ARCH_BOOTBLOCK_ARMV8_64
+ select ARCH_ROMSTAGE_ARMV8_64
+ select ARCH_RAMSTAGE_ARMV8_64
+ default n
+
+if CPU_ARMLTD_CORTEX_A53
+
+endif
diff --git a/src/mainboard/emulation/qemu-aarch64/Kconfig b/src/mainboard/emulation/qemu-aarch64/Kconfig
new file mode 100644
index 0000000..9fda646
--- /dev/null
+++ b/src/mainboard/emulation/qemu-aarch64/Kconfig
@@ -0,0 +1,56 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 Asami Doi <d0iasm.pub(a)gmail.com>.
+##
+## This software is licensed under the terms of the GNU General Public
+## License version 2, as published by the Free Software Foundation, and
+## may be copied, distributed, and modified under those terms.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+
+# Emulation for QEMU 2.8 ARM Virtual Machine (alias of virt-2.8)
+# https://wiki.qemu.org/Documentation/Platforms/ARM
+
+# To execute, do:
+# export QEMU_AUDIO_DRV = none
+# qemu-system-aarch64 -M virt -m 1024M -cpu cortex-a53 -nographic -bios build/coreboot.rom
+
+if BOARD_EMULATION_QEMU_AARCH64
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select CPU_ARMLTD_CORTEX_A53
+ select DRIVERS_UART_PL011
+ select CONSOLE_SERIAL
+ select MAINBOARD_HAS_NATIVE_VGA_INIT
+ select MAINBOARD_FORCE_NATIVE_VGA_INIT
+ select HAVE_LINEAR_FRAMEBUFFER
+ select ARCH_BOOTBLOCK_ARMV8_64
+ select ARCH_VERSTAGE_ARMV8_64
+ select ARCH_ROMSTAGE_ARMV8_64
+ select ARCH_RAMSTAGE_ARMV8_64
+ select BOARD_ROMSIZE_KB_4096
+ select BOOT_DEVICE_NOT_SPI_FLASH
+ select MISSING_BOARD_RESET
+
+config MAINBOARD_DIR
+ string
+ default emulation/qemu-aarch64
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "QEMU AArch64"
+
+config MAX_CPUS
+ int
+ default 2
+
+config MAINBOARD_VENDOR
+ string
+ default "ARM Ltd."
+
+endif # BOARD_EMULATION_QEMU_AARCH64
diff --git a/src/mainboard/emulation/qemu-aarch64/Kconfig.name b/src/mainboard/emulation/qemu-aarch64/Kconfig.name
new file mode 100644
index 0000000..9789823
--- /dev/null
+++ b/src/mainboard/emulation/qemu-aarch64/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_EMULATION_QEMU_AARCH64
+ bool "QEMU AArch64 (virt)"
diff --git a/src/mainboard/emulation/qemu-aarch64/Makefile.inc b/src/mainboard/emulation/qemu-aarch64/Makefile.inc
new file mode 100644
index 0000000..e120bec
--- /dev/null
+++ b/src/mainboard/emulation/qemu-aarch64/Makefile.inc
@@ -0,0 +1,32 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 Asami Doi <d0iasm.pub(a)gmail.com>
+##
+## This software is licensed under the terms of the GNU General Public
+## License version 2, as published by the Free Software Foundation, and
+## may be copied, distributed, and modified under those terms.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+
+romstage-y += cbmem.c
+ramstage-y += cbmem.c
+
+bootblock-y += media.c
+romstage-y += media.c
+ramstage-y += media.c
+
+bootblock-y += timer.c
+romstage-y += timer.c
+ramstage-y += timer.c
+
+bootblock-y += mmio.c
+romstage-y += mmio.c
+ramstage-y += mmio.c
+
+bootblock-y += memlayout.ld
+romstage-y += memlayout.ld
+ramstage-y += memlayout.ld
diff --git a/src/mainboard/emulation/qemu-aarch64/board_info.txt b/src/mainboard/emulation/qemu-aarch64/board_info.txt
new file mode 100644
index 0000000..e3ecc19
--- /dev/null
+++ b/src/mainboard/emulation/qemu-aarch64/board_info.txt
@@ -0,0 +1,3 @@
+Board name: QEMU AArch64 (virt)
+Category: emulation
+Board URL: https://wiki.qemu.org/Documentation/Platforms/ARM
diff --git a/src/mainboard/emulation/qemu-aarch64/cbmem.c b/src/mainboard/emulation/qemu-aarch64/cbmem.c
new file mode 100644
index 0000000..635fe4b
--- /dev/null
+++ b/src/mainboard/emulation/qemu-aarch64/cbmem.c
@@ -0,0 +1,65 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stddef.h>
+#include <cbmem.h>
+#include <symbols.h>
+#include <device/mmio.h>
+#include "mainboard.h"
+
+#define PATTERN1 0x55
+#define PATTERN2 0xaa
+
+/* Returns 1 if mebibyte mb is present and 0 otherwise. */
+static int probe_mb(int mb)
+{
+ char *ptr = (char *)0x60000000 + (mb << 20) + 0xfffff;
+ char old;
+ if (ptr < (char *)&_eprogram) {
+ /* Don't probe below _end to avoid accidentally clobering
+ oneself. */
+ return 1;
+ }
+
+ old = read8(ptr);
+ write8(ptr, PATTERN1);
+ if (read8(ptr) != PATTERN1)
+ return 0;
+ write8(ptr, PATTERN2);
+ if (read8(ptr) != PATTERN2)
+ return 0;
+ write8(ptr, old);
+ return 1;
+}
+
+int probe_ramsize(void)
+{
+ int i;
+ int discovered = 0;
+ static int saved_result;
+ if (saved_result)
+ return saved_result;
+ /* Compact binary search. */
+ /* 1 GiB is the largest supported RAM by this machine. */
+ for (i = 9; i >= 0; i--)
+ if (probe_mb(discovered | (1 << i)))
+ discovered |= (1 << i);
+ discovered++;
+ saved_result = discovered;
+ return discovered;
+}
+
+void *cbmem_top(void)
+{
+ return _dram + (probe_ramsize() << 20);
+}
diff --git a/src/mainboard/emulation/qemu-aarch64/devicetree.cb b/src/mainboard/emulation/qemu-aarch64/devicetree.cb
new file mode 100644
index 0000000..258d7ba
--- /dev/null
+++ b/src/mainboard/emulation/qemu-aarch64/devicetree.cb
@@ -0,0 +1,19 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 Asami Doi <d0iasm.pub(a)gmail.com>.
+##
+## This software is licensed under the terms of the GNU General Public
+## License version 2, as published by the Free Software Foundation, and
+## may be copied, distributed, and modified under those terms.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+
+chip cpu/armltd/cortex-a53
+ chip drivers/generic/generic # I2C0 controller
+ device i2c 6 on end # Fake component for testing
+ end
+end
diff --git a/src/mainboard/emulation/qemu-aarch64/mainboard.c b/src/mainboard/emulation/qemu-aarch64/mainboard.c
new file mode 100644
index 0000000..f0b90f1
--- /dev/null
+++ b/src/mainboard/emulation/qemu-aarch64/mainboard.c
@@ -0,0 +1,69 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Asami Doi <d0iasm.pub(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 or, at your option, any later
+ * version of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <cbmem.h>
+#include <halt.h>
+#include "mainboard.h"
+#include <edid.h>
+#include <device/mmio.h>
+
+static void init_gfx(void)
+{
+ uint32_t *pl111;
+ struct edid edid;
+ /* width is at most 4096 */
+ /* height is at most 1024 */
+ int width = 800, height = 600;
+ uint32_t framebuffer = 0x4c000000;
+ pl111 = (uint32_t *)0x10020000;
+ write32(pl111, (width / 4) - 4);
+ write32(pl111 + 1, height - 1);
+ /* registers 2, 3 and 5 are ignored by qemu. Set them correctly if
+ we ever go for real hw. */
+ /* framebuffer address offset. Has to be in vram. */
+ write32(pl111 + 4, framebuffer);
+ write32(pl111 + 7, 0);
+ write32(pl111 + 10, 0xff);
+ write32(pl111 + 6, (5 << 1) | 0x801);
+
+ edid.framebuffer_bits_per_pixel = 32;
+ edid.bytes_per_line = width * 4;
+ edid.x_resolution = width;
+ edid.y_resolution = height;
+
+ set_vbe_mode_info_valid(&edid, framebuffer);
+}
+
+static void mainboard_enable(struct device *dev)
+{
+ int discovered;
+ if (!dev) {
+ printk(BIOS_EMERG, "No dev0; die\n");
+ halt();
+ }
+
+ discovered = probe_ramsize();
+ printk(BIOS_DEBUG, "%d MiB of RAM discovered\n", discovered);
+ ram_resource(dev, 0, 0x60000000 >> 10, discovered << 10);
+ cbmem_recovery(0);
+ init_gfx();
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/emulation/qemu-aarch64/mainboard.h b/src/mainboard/emulation/qemu-aarch64/mainboard.h
new file mode 100644
index 0000000..b6927ea
--- /dev/null
+++ b/src/mainboard/emulation/qemu-aarch64/mainboard.h
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Asami Doi <d0iasm.pub(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 or, at your option, any later
+ * version of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef QEMU_AARCH64_MAINBOARD_H
+#define QEMU_AARCH64_MAINBOARD_H
+
+/* Returns RAM size in mebibytes. */
+int probe_ramsize(void);
+
+#endif
diff --git a/src/mainboard/emulation/qemu-aarch64/media.c b/src/mainboard/emulation/qemu-aarch64/media.c
new file mode 100644
index 0000000..c9c3a34
--- /dev/null
+++ b/src/mainboard/emulation/qemu-aarch64/media.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Asami Doi <d0iasm.pub(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <boot_device.h>
+
+/* Maps directly to NOR flash up to ROM size. */
+static const struct mem_region_device boot_dev =
+ MEM_REGION_DEV_RO_INIT((void *)0x0, CONFIG_ROM_SIZE);
+
+const struct region_device *boot_device_ro(void)
+{
+ return &boot_dev.rdev;
+}
diff --git a/src/mainboard/emulation/qemu-aarch64/memlayout.ld b/src/mainboard/emulation/qemu-aarch64/memlayout.ld
new file mode 100644
index 0000000..03db138
--- /dev/null
+++ b/src/mainboard/emulation/qemu-aarch64/memlayout.ld
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Asami Doi <d0iasm.pub(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <memlayout.h>
+
+#include <arch/header.ld>
+
+/*
+ * Memory map for QEMU virt machine since
+ * a578cdfbdd8f9beff5ced52b7826ddb1669abbbf (June 2019):
+ *
+ * 0x0000_0000: Flash memory
+ * 0x0800_0000: I/O map address
+ * 0x6000_0000: RAM
+ */
+
+#define VIRT_FLASH_START 0x00000000
+#define VIRT_IO_START 0x08000000
+#define VIRT_DRAM_START 0x60000000
+
+/*
+ * This map is designed to work with new qemu virt memory layout and
+ * with -bios option which neatly puts coreboot into flash and so payloads
+ * can find CBFS and we don't risk overwriting CBFS.
+ *
+ * Prior to Jul 2014 qemu aliased 0 to begining of RAM instead of flash
+ * and -bios was unusable as $pc pointed to 0 which was zero-filled as a
+ * workaround we suggested using -kernel but this still had all the issues
+ * of having fake-ROM in RAM. In fact it was even worse as fake ROM ends
+ * up exactly at addresses needed to load Linux.
+ */
+SECTIONS
+{
+ BOOTBLOCK(VIRT_FLASH_START, 64K)
+
+ DRAM_START(VIRT_DRAM_START)
+ STACK(VIRT_DRAM_START, 64K)
+ ROMSTAGE(VIRT_DRAM_START + 0x10000, 128K)
+ RAMSTAGE(VIRT_DRAM_START + 0x30000, 16M)
+
+ /* TODO: Implement MMU support and move TTB to a better location. */
+ TTB(0x61030000, 16K)
+}
diff --git a/src/mainboard/emulation/qemu-aarch64/mmio.c b/src/mainboard/emulation/qemu-aarch64/mmio.c
new file mode 100644
index 0000000..1b9a669
--- /dev/null
+++ b/src/mainboard/emulation/qemu-aarch64/mmio.c
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/uart.h>
+
+#define VIRT_UART_IO_ADDRESS (0x09000000)
+
+uintptr_t uart_platform_base(int idx)
+{
+ return VIRT_UART_IO_ADDRESS;
+}
diff --git a/src/mainboard/emulation/qemu-aarch64/timer.c b/src/mainboard/emulation/qemu-aarch64/timer.c
new file mode 100644
index 0000000..599a872
--- /dev/null
+++ b/src/mainboard/emulation/qemu-aarch64/timer.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Asami Doi <d0iasm.pub(a)gmail.com>.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+void udelay(unsigned int n);
+void udelay(unsigned int n)
+{
+ /* TODO provide delay here. */
+}
+
+int init_timer(void);
+int init_timer(void)
+{
+ return 0;
+}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Id7c0831b1ecf08785b4ec8139d809bad9b3e1eec
Gerrit-Change-Number: 33387
Gerrit-PatchSet: 1
Gerrit-Owner: Asami Doi <d0iasm.pub(a)gmail.com>
Gerrit-MessageType: newchange
Hello Yu-Ping Wu, yongqiang niu, Julius Werner, You-Cheng Syu, jitao shi, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34784
to look at the new patch set (#3).
Change subject: soc/mediatek: dsi: Refactor MIPI TX configuration
......................................................................
soc/mediatek: dsi: Refactor MIPI TX configuration
The only platform-specific difference in mtk_dsi_phy_clk_setting is how
to configure MIPI TX because those registers (and logic) are quite
different across different SOCs.
The calculation of data rate is actually the same so we should isolate
it and move to common, and rename mtk_dsi_phy_clk_setting to a better
name as mtk_dsi_configure_mipi_tx.
BUG=b:80501386,b:117254947
TEST=make -j # board = oak and boots
Change-Id: I894dc2c4c053267debf5a58313b2bb489bcf5f3a
Signed-off-by: Hung-Te Lin <hungte(a)chromium.org>
---
M src/soc/mediatek/common/dsi.c
M src/soc/mediatek/common/include/soc/dsi_common.h
M src/soc/mediatek/mt8173/dsi.c
M src/soc/mediatek/mt8173/include/soc/dsi.h
4 files changed, 40 insertions(+), 23 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/34784/3
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I894dc2c4c053267debf5a58313b2bb489bcf5f3a
Gerrit-Change-Number: 34784
Gerrit-PatchSet: 3
Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org>
Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: You-Cheng Syu <youcheng(a)google.com>
Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Reviewer: jitao shi <jitao.shi(a)mediatek.com>
Gerrit-Reviewer: yongqiang niu <yongqiang.niu(a)mediatek.com>
Gerrit-MessageType: newpatchset
Hello Yu-Ping Wu, yongqiang niu, Julius Werner, You-Cheng Syu, jitao shi, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34771
to look at the new patch set (#5).
Change subject: soc/mediatek: dsi: Refactor PHY timing calculation
......................................................................
soc/mediatek: dsi: Refactor PHY timing calculation
The PHY timing should be calculate by data rate (Mbps). However for 8173
some values were hard-coded so we want to introduce a mtk_phy_timing
structure and a weak function mtk_dsi_override_phy_timing that allows
per-SOC customization to fine tune PHY timings.
BUG=b:80501386,b:117254947
TEST=make -j # board = oak and boots
Change-Id: I1176ca06dda026029ff431aca7f9e21479eed670
Signed-off-by: Hung-Te Lin <hungte(a)chromium.org>
---
M src/soc/mediatek/common/dsi.c
M src/soc/mediatek/common/include/soc/dsi_common.h
M src/soc/mediatek/mt8173/dsi.c
3 files changed, 74 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/34771/5
--
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I1176ca06dda026029ff431aca7f9e21479eed670
Gerrit-Change-Number: 34771
Gerrit-PatchSet: 5
Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org>
Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: You-Cheng Syu <youcheng(a)google.com>
Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com>
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Gerrit-Reviewer: jitao shi <jitao.shi(a)mediatek.com>
Gerrit-Reviewer: yongqiang niu <yongqiang.niu(a)mediatek.com>
Gerrit-MessageType: newpatchset
Hello Yu-Ping Wu, yongqiang niu, Julius Werner, You-Cheng Syu, jitao shi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34784
to look at the new patch set (#2).
Change subject: soc/mediatek: dsi: Refactor MIPI TX configuration
......................................................................
soc/mediatek: dsi: Refactor MIPI TX configuration
The only platform-specific difference in mtk_dsi_phy_clk_setting is how
to configure MIPI TX because those registers (and logic) are quite
different across different SOCs.
The calculation of data rate is actually the same so we should isolate
it and move to common, and rename mtk_dsi_phy_clk_setting to a better
name as mtk_dsi_configure_mipi_tx.
BUG=b:80501386,b:117254947
TEST=make -j # board = oak and boots
Change-Id: I894dc2c4c053267debf5a58313b2bb489bcf5f3a
Signed-off-by: Hung-Te Lin <hungte(a)chromium.org>
---
M src/soc/mediatek/common/dsi.c
M src/soc/mediatek/common/include/soc/dsi_common.h
M src/soc/mediatek/mt8173/dsi.c
M src/soc/mediatek/mt8173/include/soc/dsi.h
4 files changed, 40 insertions(+), 23 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/34784/2
--
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Gerrit-Change-Id: I894dc2c4c053267debf5a58313b2bb489bcf5f3a
Gerrit-Change-Number: 34784
Gerrit-PatchSet: 2
Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org>
Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: You-Cheng Syu <youcheng(a)google.com>
Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com>
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Gerrit-Reviewer: yongqiang niu <yongqiang.niu(a)mediatek.com>
Gerrit-MessageType: newpatchset
Hello Yu-Ping Wu, yongqiang niu, Julius Werner, You-Cheng Syu, jitao shi, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34771
to look at the new patch set (#4).
Change subject: soc/mediatek: dsi: Refactor PHY timing calculation
......................................................................
soc/mediatek: dsi: Refactor PHY timing calculation
The PHY timing should be calculate by data rate (Mbps). However for 8173
some values were hard-coded so we want to introduce a mtk_phy_timing
structure and a weak function mtk_dsi_override_phy_timing that allows
per-SOC customization to fine tune PHY timings.
BUG=b:80501386,b:117254947
TEST=make -j # board = oak and boots
Change-Id: I1176ca06dda026029ff431aca7f9e21479eed670
Signed-off-by: Hung-Te Lin <hungte(a)chromium.org>
---
M src/soc/mediatek/common/dsi.c
M src/soc/mediatek/common/include/soc/dsi_common.h
M src/soc/mediatek/mt8173/dsi.c
3 files changed, 74 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/34771/4
--
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Gerrit-Change-Number: 34771
Gerrit-PatchSet: 4
Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org>
Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
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Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com>
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Gerrit-Reviewer: jitao shi <jitao.shi(a)mediatek.com>
Gerrit-Reviewer: yongqiang niu <yongqiang.niu(a)mediatek.com>
Gerrit-MessageType: newpatchset
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34728 )
Change subject: soc/intel/common: Implement MAINBOARD_POWER_STATE_PREVIOUS
......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34728/4/src/soc/intel/common/block…
File src/soc/intel/common/block/include/intelblocks/pmclib.h:
https://review.coreboot.org/c/coreboot/+/34728/4/src/soc/intel/common/block…
PS4, Line 227: void pmc_set_power_failure_state(pci_devfn_t, bool target_on);
function definition argument 'pci_devfn_t' should also have an identifier name
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I22bd71e4f3b67309c1aa0cb6faeb5959521bf656
Gerrit-Change-Number: 34728
Gerrit-PatchSet: 4
Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
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Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Comment-Date: Wed, 07 Aug 2019 22:41:03 +0000
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