coreboot-gerrit August 2019

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Change in coreboot[master]: mb/google/kohaku: Enable stylus pen device
by shkim (Code Review) 07 Aug '19

07 Aug '19

Hello Seunghwan Kim, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/34581 to review the following change. Change subject: mb/google/kohaku: Enable stylus pen device ...................................................................... mb/google/kohaku: Enable stylus pen device Enabling stylus pen device and pen detection event. BUG=b:137326841 BRANCH=none TEST=Verified pen input operation and pen detection event Change-Id: Ic252a1f90c0fc6cb9b1e426d75a8b503824681f3 Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.com> --- M src/mainboard/google/hatch/variants/kohaku/gpio.c M src/mainboard/google/hatch/variants/kohaku/overridetree.cb 2 files changed, 23 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/34581/1 diff --git a/src/mainboard/google/hatch/variants/kohaku/gpio.c b/src/mainboard/google/hatch/variants/kohaku/gpio.c index 88c1d7b..a5ac068 100644 --- a/src/mainboard/google/hatch/variants/kohaku/gpio.c +++ b/src/mainboard/google/hatch/variants/kohaku/gpio.c @@ -24,7 +24,7 @@ /* A6 : SERIRQ ==> NC */ PAD_NC(GPP_A6, NONE), /* A10 : PEN_RESET_ODL */ - PAD_CFG_GPO(GPP_A10, 0, DEEP), + PAD_CFG_GPO(GPP_A10, 1, DEEP), /* A17 : PIRQA# ==> NC */ PAD_NC(GPP_A17, NONE), /* A18 : ISH_GP0 ==> NC */ @@ -39,15 +39,9 @@ PAD_NC(GPP_B8, NONE), /* C1 : SMBDATA: NC */ PAD_NC(GPP_C1, NONE), - /* - * C12 : EMR_GARAGE_INT - * The same signal is routed to both A8 and C12. Currently C12 - * is the interrupt source, and A8 is the wake source. - * Hoping that GPP_A8 can be used for both interrupt (SCI) and wake - * (GPIO). Keeping as GPI for now. - */ - PAD_CFG_GPI_SCI(GPP_C12, NONE, DEEP, EDGE_SINGLE, INVERT), - /* C15 : EN_PP3300_TSP_DIG_DX */ + /* C7 : PEN_IRQ_OD_L */ + PAD_CFG_GPI_APIC(GPP_C7, NONE, PLTRST, LEVEL, NONE), + /* C15 : EN_PP3300_DIG_DX */ PAD_CFG_GPO(GPP_C15, 0, DEEP), /* C23 : UART2_CTS# ==> NC */ PAD_NC(GPP_C23, NONE), @@ -69,6 +63,10 @@ PAD_NC(GPP_G5, NONE), /* G6 : GPP_G6 ==> NC */ PAD_NC(GPP_G6, NONE), + /* H4 : PCH_I2C_PEN_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5 : PCH_I2C_PEN_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), }; const struct pad_config *override_gpio_table(size_t *num) diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index e463b8b..f3055a1 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -77,12 +77,25 @@ register "generic.hid" = ""WCOM50C1"" register "generic.desc" = ""WCOM Digitizer"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" - register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A10)" - register "generic.reset_delay_ms" = "1" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C15)" + # TODO: Check if reset_gpio is needed for power sequence of pen device + #register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A10)" + #register "generic.reset_delay_ms" = "1" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x1" device i2c 0x09 on end end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A8)" + register "key.wake" = "GPE0_DW0_08" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on end + end end # I2C #2 device pci 19.0 on chip drivers/i2c/da7219 -- To view, visit https://review.coreboot.org/c/coreboot/+/34581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic252a1f90c0fc6cb9b1e426d75a8b503824681f3 Gerrit-Change-Number: 34581 Gerrit-PatchSet: 1 Gerrit-Owner: shkim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/lenovo/{t60,z61t}: whitespace
by Peter Lemenkov (Code Review) 07 Aug '19

07 Aug '19

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34122 ) Change subject: mb/lenovo/{t60,z61t}: whitespace ...................................................................... mb/lenovo/{t60,z61t}: whitespace This just makes diff between these two boards smaller. Change-Id: Id2d602b0a6d2bd07202d8a4d81ee42da8388ef7e Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/t60/cmos.layout M src/mainboard/lenovo/t60/hda_verb.c M src/mainboard/lenovo/z61t/romstage.c M src/mainboard/lenovo/z61t/smihandler.c 4 files changed, 11 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/34122/1 diff --git a/src/mainboard/lenovo/t60/cmos.layout b/src/mainboard/lenovo/t60/cmos.layout index d7ff0f2..75ad427 100644 --- a/src/mainboard/lenovo/t60/cmos.layout +++ b/src/mainboard/lenovo/t60/cmos.layout @@ -48,7 +48,6 @@ # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level #399 1 r 0 unused diff --git a/src/mainboard/lenovo/t60/hda_verb.c b/src/mainboard/lenovo/t60/hda_verb.c index 3507776..73eecf6 100644 --- a/src/mainboard/lenovo/t60/hda_verb.c +++ b/src/mainboard/lenovo/t60/hda_verb.c @@ -1,9 +1,12 @@ /* * This file is part of the coreboot project. * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * Copyright (C) 2007-2009 coresystems GmbH + * 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c index 716be16..820cd52 100644 --- a/src/mainboard/lenovo/z61t/romstage.c +++ b/src/mainboard/lenovo/z61t/romstage.c @@ -41,9 +41,9 @@ // decode range pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0210); // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN - | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN - | FDD_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); + pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | MC_LPC_EN + | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN | FDD_LPC_EN + | LPT_LPC_EN | COMA_LPC_EN); /* range 0x1600 - 0x167f */ pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x007c1601); diff --git a/src/mainboard/lenovo/z61t/smihandler.c b/src/mainboard/lenovo/z61t/smihandler.c index eacbd5e..51ced89 100644 --- a/src/mainboard/lenovo/z61t/smihandler.c +++ b/src/mainboard/lenovo/z61t/smihandler.c @@ -39,8 +39,7 @@ { u8 *bar; if ((bar = (u8 *)pci_read_config32(PCI_DEV(1, 0, 0), 0x18))) { - printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, - *(bar+LVTMA_BL_MOD_LEVEL)); + printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, *(bar+LVTMA_BL_MOD_LEVEL)); *(bar+LVTMA_BL_MOD_LEVEL) &= 0xf0; if (*(bar+LVTMA_BL_MOD_LEVEL) > 0x10) *(bar+LVTMA_BL_MOD_LEVEL) -= 0x10; @@ -51,8 +50,7 @@ { u8 *bar; if ((bar = (u8 *)pci_read_config32(PCI_DEV(1, 0, 0), 0x18))) { - printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, - *(bar+LVTMA_BL_MOD_LEVEL)); + printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, *(bar+LVTMA_BL_MOD_LEVEL)); *(bar+LVTMA_BL_MOD_LEVEL) |= 0x0f; if (*(bar+LVTMA_BL_MOD_LEVEL) < 0xf0) *(bar+LVTMA_BL_MOD_LEVEL) += 0x10; -- To view, visit https://review.coreboot.org/c/coreboot/+/34122 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id2d602b0a6d2bd07202d8a4d81ee42da8388ef7e Gerrit-Change-Number: 34122 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF
by Patrick Rudolph (Code Review) 07 Aug '19

07 Aug '19

Patrick Rudolph has uploaded a new patch set (#67) to the change originally created by Christian Walter. ( https://review.coreboot.org/c/coreboot/+/32734 ) Change subject: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF ...................................................................... mb/supermicro/x11ssh: Add Supermicro X11SSH-TF Add support for the X11SSH-TF which is based on Intel KBL. Working: * SeaBios payload * LinuxBoot payload * IPMI of BMC * PCIe, SATA, USB ports * RS232 serial * Native graphics init Not working: * Tianocore doesn't work yet as the Aspeed NGI is text mode only. * Intel SGX, due to random crashes in soc/intel/common For more details have a look at the documentation. Please apply those patches as well for good user experience: I456be647b159f7a2ea7d94986a24424e56dcc8c4 I22c6885eae6fd7c778ac37b18f95b8775e9064e3 Ica0c20255f661dd61edc3a7d15646b7447c4658e Signed-off-by: Christian Walter <christian.walter(a)9elements.com> Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Change-Id: I2edaa4a928de3a065e517c0f20e3302b4b702323 --- M Documentation/mainboard/index.md A Documentation/mainboard/supermicro/x11ssh-tf.md A Documentation/mainboard/supermicro/x11ssh_flash.jpg A src/mainboard/supermicro/x11ssh/Kconfig A src/mainboard/supermicro/x11ssh/Kconfig.name A src/mainboard/supermicro/x11ssh/Makefile.inc A src/mainboard/supermicro/x11ssh/acpi/ec.asl A src/mainboard/supermicro/x11ssh/acpi/mainboard.asl A src/mainboard/supermicro/x11ssh/acpi/superio.asl A src/mainboard/supermicro/x11ssh/acpi_tables.c A src/mainboard/supermicro/x11ssh/board_info.txt A src/mainboard/supermicro/x11ssh/bootblock.c A src/mainboard/supermicro/x11ssh/cmos.layout A src/mainboard/supermicro/x11ssh/dsdt.asl A src/mainboard/supermicro/x11ssh/gpio.h A src/mainboard/supermicro/x11ssh/mainboard.c A src/mainboard/supermicro/x11ssh/ramstage.c A src/mainboard/supermicro/x11ssh/romstage.c A src/mainboard/supermicro/x11ssh/variants/tf/board_info.txt A src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb A src/mainboard/supermicro/x11ssh/vboot-ro-rwab.fmd 21 files changed, 1,020 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/32734/67 -- To view, visit https://review.coreboot.org/c/coreboot/+/32734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2edaa4a928de3a065e517c0f20e3302b4b702323 Gerrit-Change-Number: 32734 Gerrit-PatchSet: 67 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Keno Fischer <keno(a)alumni.harvard.edu> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Name of user not set #1002358 Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: T. Hudson <trammell.hudson(a)gmail.com> Gerrit-Reviewer: Trammell Hudson <hudson(a)trmm.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Set controller state to active in GSPI init
by Meera Ravindranath (Code Review) 07 Aug '19

07 Aug '19

Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34449 ) Change subject: soc/intel/common: Set controller state to active in GSPI init ...................................................................... soc/intel/common: Set controller state to active in GSPI init Set the controller state to D0 during the GSPI sequence, this ensures the controller is up and active. Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Change-Id: I2f95059453ca5565a38650b147590ece4d8bf5ed --- M src/soc/intel/common/block/gspi/gspi.c 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/34449/1 diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c index 17532bf..8bcefe2 100644 --- a/src/soc/intel/common/block/gspi/gspi.c +++ b/src/soc/intel/common/block/gspi/gspi.c @@ -24,6 +24,7 @@ #include <intelblocks/chip.h> #include <intelblocks/gspi.h> #include <intelblocks/spi.h> +#include <intelblocks/lpss.h> #include <soc/iomap.h> #include <soc/pci_devs.h> #include <string.h> @@ -151,6 +152,7 @@ const struct gspi_cfg *cfg = gspi_get_cfg(); int devfn; uintptr_t gspi_base_addr; + const struct device *tree_dev; assert(gspi_max != 0); if (!cfg) { @@ -172,6 +174,9 @@ devfn = gspi_soc_bus_to_devfn(gspi_bus); gspi_set_base_addr(devfn, NULL, GSPI_BUS_BASE(gspi_base_addr, gspi_bus)); + tree_dev = pcidev_path_on_root(devfn); + /* Ensure controller is in D0 state */ + lpss_set_power_state(tree_dev, STATE_D0); } } @@ -449,6 +454,9 @@ uint32_t cs_ctrl, sscr0, sscr1, clocks, sitf, sirf, pol; struct gspi_ctrlr_params params, *p = &params; + /* Ensure controller is in D0 state */ + lpss_set_power_state((struct device*) dev, STATE_D0); + /* Only chip select 0 is supported. */ if (dev->cs != 0) { printk(BIOS_ERR, "%s: Invalid CS value: cs=%u.\n", __func__, -- To view, visit https://review.coreboot.org/c/coreboot/+/34449 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f95059453ca5565a38650b147590ece4d8bf5ed Gerrit-Change-Number: 34449 Gerrit-PatchSet: 1 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF
by Patrick Rudolph (Code Review) 07 Aug '19

07 Aug '19

Patrick Rudolph has uploaded a new patch set (#66) to the change originally created by Christian Walter. ( https://review.coreboot.org/c/coreboot/+/32734 ) Change subject: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF ...................................................................... mb/supermicro/x11ssh: Add Supermicro X11SSH-TF Add support for the X11SSH-TF which is based on Intel KBL. Working: * SeaBios payload * LinuxBoot payload * IPMI of BMC * PCIe, SATA, USB ports * RS232 serial * Native graphics init Not working: * Tianocore doesn't work yet as the Aspeed NGI is text mode only. * Intel SGX, due to random crashes in soc/intel/common For more details have a look at the documentation. Please apply those patches as well for good user experience: I456be647b159f7a2ea7d94986a24424e56dcc8c4 I22c6885eae6fd7c778ac37b18f95b8775e9064e3 Ica0c20255f661dd61edc3a7d15646b7447c4658e Signed-off-by: Christian Walter <christian.walter(a)9elements.com> Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Change-Id: I2edaa4a928de3a065e517c0f20e3302b4b702323 --- M Documentation/mainboard/index.md A Documentation/mainboard/supermicro/x11ssh-tf.md A Documentation/mainboard/supermicro/x11ssh_flash.jpg A src/mainboard/supermicro/x11ssh/Kconfig A src/mainboard/supermicro/x11ssh/Kconfig.name A src/mainboard/supermicro/x11ssh/Makefile.inc A src/mainboard/supermicro/x11ssh/acpi/ec.asl A src/mainboard/supermicro/x11ssh/acpi/mainboard.asl A src/mainboard/supermicro/x11ssh/acpi/superio.asl A src/mainboard/supermicro/x11ssh/acpi_tables.c A src/mainboard/supermicro/x11ssh/board_info.txt A src/mainboard/supermicro/x11ssh/bootblock.c A src/mainboard/supermicro/x11ssh/cmos.layout A src/mainboard/supermicro/x11ssh/dsdt.asl A src/mainboard/supermicro/x11ssh/gpio.h A src/mainboard/supermicro/x11ssh/mainboard.c A src/mainboard/supermicro/x11ssh/ramstage.c A src/mainboard/supermicro/x11ssh/romstage.c A src/mainboard/supermicro/x11ssh/variants/tf/board_info.txt A src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb A src/mainboard/supermicro/x11ssh/vboot-ro-rwab.fmd 21 files changed, 1,020 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/32734/66 -- To view, visit https://review.coreboot.org/c/coreboot/+/32734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2edaa4a928de3a065e517c0f20e3302b4b702323 Gerrit-Change-Number: 32734 Gerrit-PatchSet: 66 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Keno Fischer <keno(a)alumni.harvard.edu> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Name of user not set #1002358 Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: T. Hudson <trammell.hudson(a)gmail.com> Gerrit-Reviewer: Trammell Hudson <hudson(a)trmm.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF
by build bot (Jenkins) (Code Review) 07 Aug '19

07 Aug '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32734 ) Change subject: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF ...................................................................... Patch Set 65: (14 comments) https://review.coreboot.org/c/coreboot/+/32734/65/src/mainboard/supermicro/… File src/mainboard/supermicro/x11ssh/romstage.c: https://review.coreboot.org/c/coreboot/+/32734/65/src/mainboard/supermicro/… PS65, Line 20: FSP_M_CONFIG *mem_cfg; please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/32734/65/src/mainboard/supermicro/… PS65, Line 23: struct spd_block blk = { please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/32734/65/src/mainboard/supermicro/… PS65, Line 24: .addr_map = { 0x50, 0x51, 0x52, 0x53, }, code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/32734/65/src/mainboard/supermicro/… PS65, Line 24: .addr_map = { 0x50, 0x51, 0x52, 0x53, }, please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/32734/65/src/mainboard/supermicro/… PS65, Line 25: }; please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/32734/65/src/mainboard/supermicro/… PS65, Line 27: mem_cfg->DqPinsInterleaved = 1; please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/32734/65/src/mainboard/supermicro/… PS65, Line 28: get_spd_smbus(&blk); please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/32734/65/src/mainboard/supermicro/… PS65, Line 29: mem_cfg->MemorySpdDataLen = blk.len; please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/32734/65/src/mainboard/supermicro/… PS65, Line 30: mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/32734/65/src/mainboard/supermicro/… PS65, Line 31: mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[2]; please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/32734/65/src/mainboard/supermicro/… PS65, Line 32: mem_cfg->MemorySpdPtr01 = (uintptr_t)blk.spd_array[1]; please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/32734/65/src/mainboard/supermicro/… PS65, Line 33: mem_cfg->MemorySpdPtr11 = (uintptr_t)blk.spd_array[3]; please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/32734/65/src/mainboard/supermicro/… PS65, Line 34: mem_cfg->UserBd = BOARD_TYPE_SERVER; please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/32734/65/src/mainboard/supermicro/… PS65, Line 36: mupd->FspmTestConfig.DmiVc1 = 1; please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/32734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2edaa4a928de3a065e517c0f20e3302b4b702323 Gerrit-Change-Number: 32734 Gerrit-PatchSet: 65 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Keno Fischer <keno(a)alumni.harvard.edu> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Name of user not set #1002358 Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: T. Hudson <trammell.hudson(a)gmail.com> Gerrit-Reviewer: Trammell Hudson <hudson(a)trmm.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Aug 2019 13:40:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP]nb/intel/sandybridge/raminit: Add ECC support
by Christoph Pomaska (Code Review) 07 Aug '19

07 Aug '19

Christoph Pomaska has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/22215 ) Change subject: [WIP]nb/intel/sandybridge/raminit: Add ECC support ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/22215 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1206746332c9939a78b67e7b48d3098bdef8a2ed Gerrit-Change-Number: 22215 Gerrit-PatchSet: 6 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Aug 2019 13:32:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF
by Patrick Rudolph (Code Review) 07 Aug '19

07 Aug '19

Patrick Rudolph has uploaded a new patch set (#65) to the change originally created by Christian Walter. ( https://review.coreboot.org/c/coreboot/+/32734 ) Change subject: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF ...................................................................... mb/supermicro/x11ssh: Add Supermicro X11SSH-TF Add support for the X11SSH-TF which is based on Intel KBL. Working: * SeaBios payload * LinuxBoot payload * IPMI of BMC * PCIe, SATA, USB ports * RS232 serial * Native graphics init Not working: * Tianocore doesn't work yet as the Aspeed NGI is text mode only. * Intel SGX, due to random crashes in soc/intel/common For more details have a look at the documentation. Please apply those patches as well for good user experience: I456be647b159f7a2ea7d94986a24424e56dcc8c4 I22c6885eae6fd7c778ac37b18f95b8775e9064e3 Ica0c20255f661dd61edc3a7d15646b7447c4658e Signed-off-by: Christian Walter <christian.walter(a)9elements.com> Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Change-Id: I2edaa4a928de3a065e517c0f20e3302b4b702323 --- M Documentation/mainboard/index.md A Documentation/mainboard/supermicro/x11ssh-tf.md A Documentation/mainboard/supermicro/x11ssh_flash.jpg A src/mainboard/supermicro/x11ssh/Kconfig A src/mainboard/supermicro/x11ssh/Kconfig.name A src/mainboard/supermicro/x11ssh/Makefile.inc A src/mainboard/supermicro/x11ssh/acpi/ec.asl A src/mainboard/supermicro/x11ssh/acpi/mainboard.asl A src/mainboard/supermicro/x11ssh/acpi/superio.asl A src/mainboard/supermicro/x11ssh/acpi_tables.c A src/mainboard/supermicro/x11ssh/board_info.txt A src/mainboard/supermicro/x11ssh/bootblock.c A src/mainboard/supermicro/x11ssh/cmos.layout A src/mainboard/supermicro/x11ssh/dsdt.asl A src/mainboard/supermicro/x11ssh/gpio.h A src/mainboard/supermicro/x11ssh/mainboard.c A src/mainboard/supermicro/x11ssh/ramstage.c A src/mainboard/supermicro/x11ssh/romstage.c A src/mainboard/supermicro/x11ssh/variants/tf/board_info.txt A src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb A src/mainboard/supermicro/x11ssh/vboot-ro-rwab.fmd 21 files changed, 1,020 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/32734/65 -- To view, visit https://review.coreboot.org/c/coreboot/+/32734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2edaa4a928de3a065e517c0f20e3302b4b702323 Gerrit-Change-Number: 32734 Gerrit-PatchSet: 65 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Keno Fischer <keno(a)alumni.harvard.edu> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Name of user not set #1002358 Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: T. Hudson <trammell.hudson(a)gmail.com> Gerrit-Reviewer: Trammell Hudson <hudson(a)trmm.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/x86/smm: Define single smm_subregion()
by Kyösti Mälkki (Code Review) 07 Aug '19

07 Aug '19

Hello Patrick Rudolph, Vanny E, build bot (Jenkins), David Guckian, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/34776 to look at the new patch set (#2). Change subject: cpu/x86/smm: Define single smm_subregion() ...................................................................... cpu/x86/smm: Define single smm_subregion() At the moment we only have two splitting of TSEG, one with and one without IED. They can all use same implementation. Rename file from stage_cache.c to tseg_region.c to reflect it's purpose. Change-Id: I9daf0dec8fbaaa1f4e6004ea034869f43412d7d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/x86/smm/Makefile.inc D src/cpu/x86/smm/stage_cache.c A src/cpu/x86/smm/tseg_region.c M src/soc/amd/picasso/ramtop.c M src/soc/amd/stoneyridge/ramtop.c M src/soc/intel/apollolake/memmap.c M src/soc/intel/braswell/memmap.c M src/soc/intel/cannonlake/memmap.c M src/soc/intel/denverton_ns/memmap.c M src/soc/intel/icelake/memmap.c M src/soc/intel/skylake/memmap.c 11 files changed, 90 insertions(+), 339 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/34776/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/34776 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9daf0dec8fbaaa1f4e6004ea034869f43412d7d5 Gerrit-Change-Number: 34776 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: dram: Add basic DDR4 SPD parsing
by Patrick Rudolph (Code Review) 07 Aug '19

07 Aug '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34680 ) Change subject: dram: Add basic DDR4 SPD parsing ...................................................................... Patch Set 3: (5 comments) https://review.coreboot.org/c/coreboot/+/34680/3/src/device/dram/ddr4.c File src/device/dram/ddr4.c: https://review.coreboot.org/c/coreboot/+/34680/3/src/device/dram/ddr4.c@45 PS3, Line 45: start with spd[0] to get "Bytes Total" and "Bytes used" https://review.coreboot.org/c/coreboot/+/34680/3/src/device/dram/ddr4.c@56 PS3, Line 56: reg8 = spd[13] & ((1 << 4) - 1); I personally find hex values easier to read. https://review.coreboot.org/c/coreboot/+/34680/3/src/device/dram/ddr4.c@80 PS3, Line 80: dimm->manufacturer_id = (spd[351] << 8) | spd[350]; check if 351 is within "Bytes used" in spd[0] https://review.coreboot.org/c/coreboot/+/34680/3/src/device/dram/ddr4.c@85 PS3, Line 85: memcpy(dimm->part_number, &spd[329], SPD_DDR4_PART_LEN); make sure those are properly null terminated https://review.coreboot.org/c/coreboot/+/34680/3/src/device/dram/ddr4.c@120 PS3, Line 120: dimm->ddr_frequency = selected_freq; besides "configured memory speed" there's also a field for "maximum memory speed". It would be great if you could parse tCK, MTB and FTB, too. -- To view, visit https://review.coreboot.org/c/coreboot/+/34680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3befbc55cf37e1018baa432cb2f03743b929211 Gerrit-Change-Number: 34680 Gerrit-PatchSet: 3 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 07 Aug 2019 09:16:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit August 2019