Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34698 )
Change subject: intel/fsp_rangeley: Rename raminit.c to memmap.c ......................................................................
intel/fsp_rangeley: Rename raminit.c to memmap.c
Use a name consistent with the more recent soc/intel.
Change-Id: I704d7cb637e4e12039ade99f57e10af794c8be97 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/34698 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz Reviewed-by: David Guckian --- M src/northbridge/intel/fsp_rangeley/Makefile.inc R src/northbridge/intel/fsp_rangeley/memmap.c 2 files changed, 2 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved David Guckian: Looks good to me, but someone else must approve
diff --git a/src/northbridge/intel/fsp_rangeley/Makefile.inc b/src/northbridge/intel/fsp_rangeley/Makefile.inc index f9bf050..a2f8054 100644 --- a/src/northbridge/intel/fsp_rangeley/Makefile.inc +++ b/src/northbridge/intel/fsp_rangeley/Makefile.inc @@ -18,12 +18,12 @@
subdirs-y += fsp ramstage-y += northbridge.c -ramstage-y += raminit.c +ramstage-y += memmap.c
ramstage-y += acpi.c ramstage-y += port_access.c
-romstage-y += raminit.c +romstage-y += memmap.c romstage-y += ../../../arch/x86/walkcbfs.S romstage-y += port_access.c
diff --git a/src/northbridge/intel/fsp_rangeley/raminit.c b/src/northbridge/intel/fsp_rangeley/memmap.c similarity index 100% rename from src/northbridge/intel/fsp_rangeley/raminit.c rename to src/northbridge/intel/fsp_rangeley/memmap.c