Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34690 )
Change subject: Documentation: Advertise support for OpenSBI ......................................................................
Documentation: Advertise support for OpenSBI
Change-Id: Ie990bb95fcdcfab0246e8c694704022d9b8b5195 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M Documentation/arch/riscv/index.md M Documentation/mainboard/sifive/hifive-unleashed.md 2 files changed, 16 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/34690/1
diff --git a/Documentation/arch/riscv/index.md b/Documentation/arch/riscv/index.md index 9a5de34..528b691 100644 --- a/Documentation/arch/riscv/index.md +++ b/Documentation/arch/riscv/index.md @@ -23,8 +23,20 @@ ## Additional payload handoff requirements The location of cbmem should be placed in a node in the FDT.
+## OpenSBI +In case the payload doesn't install it's own SBI, like the [RISCV-PK] does, +[OpenSBI] can be used instead. +It's loaded into RAM after coreboot has finished loading the payload. +coreboot then will jump to OpenSBI providing a pointer to the real payload, +which OpenSBI will jump to once the SBI is installed. + +Besides providing SBI it also sets protected memory regions and provides +a platform independend console. + +The OpenSBI code is always run in M mode. + ## Trap delegation -Traps are delegated in the ramstage. +Traps are delegated to the payload.
## SMP within a stage At the beginning of each stage, all harts save 0 are spinning in a loop on @@ -44,3 +56,6 @@ will panic if possible, but behavior is largely undefined.
Only hart 0 runs through most of the code in each stage. + +[RISCV-PK]: https://github.com/riscv/riscv-pk +[OpenSBI]: https://github.com/riscv/opensbi diff --git a/Documentation/mainboard/sifive/hifive-unleashed.md b/Documentation/mainboard/sifive/hifive-unleashed.md index 495dade..4dbbf0e 100644 --- a/Documentation/mainboard/sifive/hifive-unleashed.md +++ b/Documentation/mainboard/sifive/hifive-unleashed.md @@ -17,7 +17,6 @@ - Provide serial number to payload (e.g. in device tree) - Implement instruction emulation - Support for booting Linux on RISC-V -- Add support to run OpenSBI payload in m-mode - SMP support in trap handler
## Configuration
Jonathan Neuschäfer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34690 )
Change subject: Documentation: Advertise support for OpenSBI ......................................................................
Patch Set 1:
(1 comment)
Looks good except for the typo. Thanks!
https://review.coreboot.org/c/coreboot/+/34690/1/Documentation/arch/riscv/in... File Documentation/arch/riscv/index.md:
https://review.coreboot.org/c/coreboot/+/34690/1/Documentation/arch/riscv/in... PS1, Line 34: independend 'independent' with 't'
Hello Jonathan Neuschäfer, Philipp Deppenwiese, build bot (Jenkins), Philipp Hug, Xiang Wang,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34690
to look at the new patch set (#2).
Change subject: Documentation: Advertise support for OpenSBI ......................................................................
Documentation: Advertise support for OpenSBI
Change-Id: Ie990bb95fcdcfab0246e8c694704022d9b8b5195 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M Documentation/arch/riscv/index.md M Documentation/mainboard/sifive/hifive-unleashed.md 2 files changed, 16 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/34690/2
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34690 )
Change subject: Documentation: Advertise support for OpenSBI ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34690/1/Documentation/arch/riscv/in... File Documentation/arch/riscv/index.md:
https://review.coreboot.org/c/coreboot/+/34690/1/Documentation/arch/riscv/in... PS1, Line 34: independend
'independent' with 't'
Done
Jonathan Neuschäfer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34690 )
Change subject: Documentation: Advertise support for OpenSBI ......................................................................
Patch Set 2: Code-Review+1
Philipp Hug has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34690 )
Change subject: Documentation: Advertise support for OpenSBI ......................................................................
Patch Set 2: Code-Review+1
Xiang Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34690 )
Change subject: Documentation: Advertise support for OpenSBI ......................................................................
Patch Set 2: Code-Review+2
Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34690 )
Change subject: Documentation: Advertise support for OpenSBI ......................................................................
Documentation: Advertise support for OpenSBI
Change-Id: Ie990bb95fcdcfab0246e8c694704022d9b8b5195 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/34690 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Jonathan Neuschäfer j.neuschaefer@gmx.net Reviewed-by: Philipp Hug philipp@hug.cx Reviewed-by: Xiang Wang merle@hardenedlinux.org --- M Documentation/arch/riscv/index.md M Documentation/mainboard/sifive/hifive-unleashed.md 2 files changed, 16 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Jonathan Neuschäfer: Looks good to me, but someone else must approve Xiang Wang: Looks good to me, approved Philipp Hug: Looks good to me, but someone else must approve
diff --git a/Documentation/arch/riscv/index.md b/Documentation/arch/riscv/index.md index 9a5de34..ea6a5cd 100644 --- a/Documentation/arch/riscv/index.md +++ b/Documentation/arch/riscv/index.md @@ -23,8 +23,20 @@ ## Additional payload handoff requirements The location of cbmem should be placed in a node in the FDT.
+## OpenSBI +In case the payload doesn't install it's own SBI, like the [RISCV-PK] does, +[OpenSBI] can be used instead. +It's loaded into RAM after coreboot has finished loading the payload. +coreboot then will jump to OpenSBI providing a pointer to the real payload, +which OpenSBI will jump to once the SBI is installed. + +Besides providing SBI it also sets protected memory regions and provides +a platform independent console. + +The OpenSBI code is always run in M mode. + ## Trap delegation -Traps are delegated in the ramstage. +Traps are delegated to the payload.
## SMP within a stage At the beginning of each stage, all harts save 0 are spinning in a loop on @@ -44,3 +56,6 @@ will panic if possible, but behavior is largely undefined.
Only hart 0 runs through most of the code in each stage. + +[RISCV-PK]: https://github.com/riscv/riscv-pk +[OpenSBI]: https://github.com/riscv/opensbi diff --git a/Documentation/mainboard/sifive/hifive-unleashed.md b/Documentation/mainboard/sifive/hifive-unleashed.md index 495dade..4dbbf0e 100644 --- a/Documentation/mainboard/sifive/hifive-unleashed.md +++ b/Documentation/mainboard/sifive/hifive-unleashed.md @@ -17,7 +17,6 @@ - Provide serial number to payload (e.g. in device tree) - Implement instruction emulation - Support for booting Linux on RISC-V -- Add support to run OpenSBI payload in m-mode - SMP support in trap handler
## Configuration