coreboot-gerrit October 2019

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Change in coreboot[master]: Update chromeec submodule to upstream master
by Patrick Georgi (Code Review) 03 Oct '19

03 Oct '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35624 ) Change subject: Update chromeec submodule to upstream master ...................................................................... Update chromeec submodule to upstream master Updating from commit id 860fe2962: 2018-12-29 05:45:29 -0800 - (mt_scp/ipi: Support host command.) to commit id 1906434c4: 2019-09-26 10:32:54 +0000 - (tcpci: add missing CPRINTS argument) This brings in 1681 new commits. Change-Id: Ieb4f00b21a4354bb634c3427c73260123b54ac2a Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M 3rdparty/chromeec 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/35624/1 diff --git a/3rdparty/chromeec b/3rdparty/chromeec index 860fe29..1906434 160000 --- a/3rdparty/chromeec +++ b/3rdparty/chromeec @@ -1 +1 @@ -Subproject commit 860fe2962d40ee901369d1dc67f4aa7a7a42ba4d +Subproject commit 1906434c4e62fac6792b6b81874810495be49b2e -- To view, visit https://review.coreboot.org/c/coreboot/+/35624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb4f00b21a4354bb634c3427c73260123b54ac2a Gerrit-Change-Number: 35624 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/skl/vr_config: fix KBL-U GT3 detection bug
by Patrick Rudolph (Code Review) 03 Oct '19

03 Oct '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35782 ) Change subject: soc/skl/vr_config: fix KBL-U GT3 detection bug ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/35782 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33527d90550a1de78c9375d3d3b0e046787a559b Gerrit-Change-Number: 35782 Gerrit-PatchSet: 2 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 03 Oct 2019 16:31:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/skl/vr_config: fix KBL-U GT3 detection bug
by Maxim Polyakov (Code Review) 03 Oct '19

03 Oct '19

Hello Patrick Rudolph, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35782 to look at the new patch set (#2). Change subject: soc/skl/vr_config: fix KBL-U GT3 detection bug ...................................................................... soc/skl/vr_config: fix KBL-U GT3 detection bug Some VR parameter values for KBL-U with GT3 graphics are different from values for other CPUs in this series [1]. However, GT3 iGPU will never be detected, since the igd_id variable is compared with the LPC device PCI ID. The patch fixes this bug. [1] page 109, 7th Generation Intel(R) Processor Families for U/Y Platforms and 8th Generation Intel(R) Processor Family for U Quad Core and Y Dual Core Platforms. Datasheet, Volume 1. January 2019. Document Number: 334661-006 Change-Id: I33527d90550a1de78c9375d3d3b0e046787a559b Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/soc/intel/skylake/vr_config.c 1 file changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/35782/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/35782 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33527d90550a1de78c9375d3d3b0e046787a559b Gerrit-Change-Number: 35782 Gerrit-PatchSet: 2 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in libgfxinit[master]: gma: Give GM45 its own designation (separate from G45)
by Patrick Georgi (Code Review) 03 Oct '19

03 Oct '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/35711 ) Change subject: gma: Give GM45 its own designation (separate from G45) ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/libgfxinit/+/35711 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I99bbd0582a03a9e2806ef2ebf63e466ec40133b3 Gerrit-Change-Number: 35711 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 03 Oct 2019 16:16:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: cpu/intel/: Fix regression with smmrelocate
by Kyösti Mälkki (Code Review) 03 Oct '19

03 Oct '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35780 ) Change subject: cpu/intel/: Fix regression with smmrelocate ...................................................................... cpu/intel/: Fix regression with smmrelocate Fix regression with commit d53fd70 intel/smm/gen1: Use smm_subregion(). The bitmask on SMRR register parameter was inverted for selected models. Change-Id: Ia572ca3bdd4da371985691b5d249f998382fbe48 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/smm/gen1/smmrelocate.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/35780/1 diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index 4ecd7db..3eb869a 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -121,7 +121,7 @@ /* On model_6fx and model_1067x bits [0:11] on smrr_base are reserved */ if (cpu_has_alternative_smrr()) - params->smrr_base.lo &= ~rmask; + params->smrr_base.lo &= rmask; smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size); } -- To view, visit https://review.coreboot.org/c/coreboot/+/35780 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia572ca3bdd4da371985691b5d249f998382fbe48 Gerrit-Change-Number: 35780 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: ec/google/chromec: Default EC_GOOGLE_CHROMEEC_LPC to disabled
by Martin Roth (Code Review) 03 Oct '19

03 Oct '19

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35154 ) Change subject: ec/google/chromec: Default EC_GOOGLE_CHROMEEC_LPC to disabled ...................................................................... ec/google/chromec: Default EC_GOOGLE_CHROMEEC_LPC to disabled Don't set a default bus type for the Chrome EC on x86. The platform must select the bus, typically LPC or ESPI. BUG=b:140055300 TEST=Build tested only Change-Id: I736cb9e43292a1b228cd083ca81a8e5db383e878 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/ec/google/chromeec/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/35154/1 diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig index 2242653..2eb3b95 100644 --- a/src/ec/google/chromeec/Kconfig +++ b/src/ec/google/chromeec/Kconfig @@ -60,7 +60,7 @@ config EC_GOOGLE_CHROMEEC_LPC depends on EC_GOOGLE_CHROMEEC && ARCH_X86 # Needs Plug-and-play. - def_bool y + def_bool n help Google Chrome EC via LPC bus. -- To view, visit https://review.coreboot.org/c/coreboot/+/35154 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I736cb9e43292a1b228cd083ca81a8e5db383e878 Gerrit-Change-Number: 35154 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: mb/[google/intel]/*: Specify Chrome EC bus - LPC or ESPI
by Martin Roth (Code Review) 03 Oct '19

03 Oct '19

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35153 ) Change subject: mb/[google/intel]/*: Specify Chrome EC bus - LPC or ESPI ...................................................................... mb/[google/intel]/*: Specify Chrome EC bus - LPC or ESPI Previously all boards using eSPI for the Chrome EC just called it LPC as the code for the chrome EC is the same between the two busses. I'm adding a new Kconfig symbol to specify eSPI, so switch the boards that actually use eSPI to that symbol and add the LPC symbol to all the others. The EC_GOOGLE_CHROMEEC_LPC symbol will no longer default to enabled for x86 platforms, so one symbol or the other needs to be specified for each platform. BUG=b:140055300 TEST=Build tested only. Change-Id: Icf242ca2b7d8b1470feda4e44b47a2cdc20680f2 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/mainboard/google/auron/Kconfig M src/mainboard/google/cyan/Kconfig M src/mainboard/google/dragonegg/Kconfig M src/mainboard/google/eve/Kconfig M src/mainboard/google/glados/Kconfig M src/mainboard/google/hatch/Kconfig M src/mainboard/google/link/Kconfig M src/mainboard/google/octopus/Kconfig M src/mainboard/google/poppy/Kconfig M src/mainboard/google/rambi/Kconfig M src/mainboard/google/slippy/Kconfig M src/mainboard/intel/glkrvp/Kconfig M src/mainboard/intel/strago/Kconfig 13 files changed, 13 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/35153/1 diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig index 69b086f..91abc6f 100644 --- a/src/mainboard/google/auron/Kconfig +++ b/src/mainboard/google/auron/Kconfig @@ -4,6 +4,7 @@ select SOC_INTEL_BROADWELL select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_LPC select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig index bf0cd09..1929723 100644 --- a/src/mainboard/google/cyan/Kconfig +++ b/src/mainboard/google/cyan/Kconfig @@ -3,6 +3,7 @@ select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID + select EC_GOOGLE_CHROMEEC_LPC select EC_GOOGLE_CHROMEEC_MEC select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP select ENABLE_BUILTIN_COM1 diff --git a/src/mainboard/google/dragonegg/Kconfig b/src/mainboard/google/dragonegg/Kconfig index 39228f4..854330c 100644 --- a/src/mainboard/google/dragonegg/Kconfig +++ b/src/mainboard/google/dragonegg/Kconfig @@ -5,7 +5,7 @@ select DRIVERS_I2C_HID select DRIVERS_SPI_ACPI select EC_GOOGLE_CHROMEEC - select EC_GOOGLE_CHROMEEC_LPC + select EC_GOOGLE_CHROMEEC_ESPI select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_LPSS_UART_FOR_CONSOLE diff --git a/src/mainboard/google/eve/Kconfig b/src/mainboard/google/eve/Kconfig index 022493c..6f38436 100644 --- a/src/mainboard/google/eve/Kconfig +++ b/src/mainboard/google/eve/Kconfig @@ -11,7 +11,7 @@ select DRIVERS_USB_ACPI select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID - select EC_GOOGLE_CHROMEEC_LPC + select EC_GOOGLE_CHROMEEC_ESPI select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_GMA_HAVE_VBT diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig index b75b726..f571dba 100644 --- a/src/mainboard/google/glados/Kconfig +++ b/src/mainboard/google/glados/Kconfig @@ -6,7 +6,7 @@ select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP select EC_GOOGLE_CHROMEEC_BOARDID - select EC_GOOGLE_CHROMEEC_LPC + select EC_GOOGLE_CHROMEEC_ESPI select EC_GOOGLE_CHROMEEC_MEC select EC_GOOGLE_CHROMEEC_PD select HAVE_ACPI_RESUME diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 5c7c267..72590c4 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -11,7 +11,7 @@ select DRIVERS_USB_ACPI select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID - select EC_GOOGLE_CHROMEEC_LPC + select EC_GOOGLE_CHROMEEC_ESPI select GOOGLE_SMBIOS_MAINBOARD_VERSION select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig index 6d62f64..a785eee 100644 --- a/src/mainboard/google/link/Kconfig +++ b/src/mainboard/google/link/Kconfig @@ -7,6 +7,7 @@ select SOUTHBRIDGE_INTEL_C216 select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_LPC select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index 8ca9251..6abf68d 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -12,7 +12,7 @@ select DRIVERS_USB_ACPI select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID - select EC_GOOGLE_CHROMEEC_LPC + select EC_GOOGLE_CHROMEEC_ESPI select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_LPSS_UART_FOR_CONSOLE diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index fda8c9e..6970221 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -7,7 +7,7 @@ select DRIVERS_I2C_HID select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID - select EC_GOOGLE_CHROMEEC_LPC + select EC_GOOGLE_CHROMEEC_ESPI select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_GMA_HAVE_VBT if BOARD_GOOGLE_NAMI diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index 56d44bc..e5eb509 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -3,6 +3,7 @@ def_bool n select SOC_INTEL_BAYTRAIL select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_LPC select ENABLE_BUILTIN_COM1 select BOARD_ROMSIZE_KB_8192 select HAVE_ACPI_TABLES diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index 35fced0..0bd6ff5 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -7,6 +7,7 @@ select INTEL_LYNXPOINT_LP select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_LPC select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME diff --git a/src/mainboard/intel/glkrvp/Kconfig b/src/mainboard/intel/glkrvp/Kconfig index 920b446..74679a4b 100644 --- a/src/mainboard/intel/glkrvp/Kconfig +++ b/src/mainboard/intel/glkrvp/Kconfig @@ -30,7 +30,7 @@ config GLK_CHROME_EC bool "Chrome EC" select EC_GOOGLE_CHROMEEC - select EC_GOOGLE_CHROMEEC_LPC + select EC_GOOGLE_CHROMEEC_ESPI config GLK_INTEL_EC bool "Intel EC" diff --git a/src/mainboard/intel/strago/Kconfig b/src/mainboard/intel/strago/Kconfig index da04d78..6f610a4 100644 --- a/src/mainboard/intel/strago/Kconfig +++ b/src/mainboard/intel/strago/Kconfig @@ -5,6 +5,7 @@ select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID + select EC_GOOGLE_CHROMEEC_LPC select EC_GOOGLE_CHROMEEC_MEC select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP select ENABLE_BUILTIN_COM1 -- To view, visit https://review.coreboot.org/c/coreboot/+/35153 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf242ca2b7d8b1470feda4e44b47a2cdc20680f2 Gerrit-Change-Number: 35153 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: southbridge/intel: Add config option to validate firmware descriptor
by Mathew King (Code Review) 03 Oct '19

03 Oct '19

Mathew King has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34816 ) Change subject: southbridge/intel: Add config option to validate firmware descriptor ...................................................................... southbridge/intel: Add config option to validate firmware descriptor Add new config option to validate the Intel firmware descriptor against the fmap layout. This will prevent a firmware descriptor from being used that could corrupt regions of the bootimage in certian circumstances. BUG=chromium:992215 TEST=Coming Change-Id: I9e8bb20485e96026cd594cf4e9d6b11b2bf20e1f Signed-off-by: Mathew King <mathewk(a)chromium.org> --- M src/southbridge/intel/common/Kconfig M src/southbridge/intel/common/firmware/Makefile.inc 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/34816/1 diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index c3bd90d..6b7b5e6 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -54,6 +54,13 @@ This config states descriptor mode is *required* for the platform to function properly, or to function at all. +config VALIDATE_INTEL_DESCRIPTOR + def_bool n if INTEL_DESCRIPTOR_MODE_CAPABLE + help + This config enables validating the Intel firmware descriptor against the + fmap layout. If the firmware descriptor layout does not match the fmap + then the bootimage cannot be built. + config INTEL_CHIPSET_LOCKDOWN depends on HAVE_INTEL_CHIPSET_LOCKDOWN && HAVE_SMI_HANDLER && !CHROMEOS #ChromeOS's payload seems to handle finalization on its on. diff --git a/src/southbridge/intel/common/firmware/Makefile.inc b/src/southbridge/intel/common/firmware/Makefile.inc index 898ab60..3b14f75 100644 --- a/src/southbridge/intel/common/firmware/Makefile.inc +++ b/src/southbridge/intel/common/firmware/Makefile.inc @@ -35,6 +35,11 @@ printf " DD Adding Intel Firmware Descriptor\n" dd if=$(IFD_BIN_PATH) \ of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1 +ifeq ($(CONFIG_VALIDATE_INTEL_DESCRIPTOR),y) + $(objutil)/ifdtool/ifdtool \ + $(IFDTOOL_USE_CHIPSET) \ + -t $(obj)/coreboot.pre +endif ifeq ($(CONFIG_HAVE_ME_BIN),y) printf " IFDTOOL me.bin -> coreboot.pre\n" $(objutil)/ifdtool/ifdtool \ -- To view, visit https://review.coreboot.org/c/coreboot/+/34816 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e8bb20485e96026cd594cf4e9d6b11b2bf20e1f Gerrit-Change-Number: 34816 Gerrit-PatchSet: 1 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: ifdtool: Add validate option to ifdtool
by Mathew King (Code Review) 03 Oct '19

03 Oct '19

Mathew King has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34802 ) Change subject: ifdtool: Add validate option to ifdtool ...................................................................... ifdtool: Add validate option to ifdtool Add an option to ifdtool which validates that the flash regions defined in the descriptor match the coresponding areas in the FMAP. BUG=chromium:992215 TEST=Ran 'ifdtool -t' with a good bios image and verify no issues run 'ifdtool -t' with a bad bios image and verify expected issues Change-Id: Idebf105dee1b8f829d54bd65c82867af7aa4aded --- M util/ifdtool/Makefile M util/ifdtool/ifdtool.c M util/ifdtool/ifdtool.h 3 files changed, 79 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/34802/1 diff --git a/util/ifdtool/Makefile b/util/ifdtool/Makefile index cc52b1e..a4f0af6 100644 --- a/util/ifdtool/Makefile +++ b/util/ifdtool/Makefile @@ -18,10 +18,16 @@ CC = gcc INSTALL = /usr/bin/env install PREFIX = /usr/local -CFLAGS = -O2 -g -Wall -Wextra -Wmissing-prototypes -Werror -I../../src/commonlib/include +CFLAGS = -O2 -g -Wall -Wextra -Wmissing-prototypes -Werror +CFLAGS += -I../../src/commonlib/include +CFLAGS += -I../cbfstool/flashmap +CFLAGS += -include ../../src/commonlib/include/commonlib/compiler.h LDFLAGS = OBJS = ifdtool.o +OBJS += fmap.o +OBJS += kv_pair.o +OBJS += valstr.o all: dep $(PROGRAM) @@ -38,6 +44,9 @@ %.o: %.c $(CC) $(CFLAGS) -c -o $@ $< +%.o: ../cbfstool/flashmap/%.c + $(CC) $(CFLAGS) -c -o $@ $< + install: $(PROGRAM) mkdir -p $(DESTDIR)$(PREFIX)/bin $(INSTALL) $(PROGRAM) $(DESTDIR)$(PREFIX)/bin diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 83caa69..eb9b420 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -22,6 +22,7 @@ #include <sys/types.h> #include <sys/stat.h> #include <commonlib/helpers.h> +#include <fmap.h> #include "ifdtool.h" #ifndef O_BINARY @@ -46,15 +47,15 @@ static int platform = -1; static const struct region_name region_names[MAX_REGIONS] = { - { "Flash Descriptor", "fd", "flashregion_0_flashdescriptor.bin" }, - { "BIOS", "bios", "flashregion_1_bios.bin" }, - { "Intel ME", "me", "flashregion_2_intel_me.bin" }, - { "GbE", "gbe", "flashregion_3_gbe.bin" }, - { "Platform Data", "pd", "flashregion_4_platform_data.bin" }, - { "Reserved", "res1", "flashregion_5_reserved.bin" }, - { "Reserved", "res2", "flashregion_6_reserved.bin" }, - { "Reserved", "res3", "flashregion_7_reserved.bin" }, - { "EC", "ec", "flashregion_8_ec.bin" }, + { "Flash Descriptor", "fd", "flashregion_0_flashdescriptor.bin", "SI_DESC" }, + { "BIOS", "bios", "flashregion_1_bios.bin", "SI_BIOS" }, + { "Intel ME", "me", "flashregion_2_intel_me.bin", "SI_ME" }, + { "GbE", "gbe", "flashregion_3_gbe.bin", "SI_GBE" }, + { "Platform Data", "pd", "flashregion_4_platform_data.bin", "SI_PDR" }, + { "Reserved", "res1", "flashregion_5_reserved.bin", NULL }, + { "Reserved", "res2", "flashregion_6_reserved.bin", NULL }, + { "Reserved", "res3", "flashregion_7_reserved.bin", NULL }, + { "EC", "ec", "flashregion_8_ec.bin", "SI_EC" }, }; /* port from flashrom */ @@ -804,6 +805,51 @@ } } +static void validate_layout(char *image, int size) +{ + uint i, errors = 0; + struct fmap* fmap; + long int fmap_loc = fmap_find((uint8_t *)image, size); + const frba_t *frba = find_frba(image, size); + + if (fmap_loc < 0 || !frba) + exit(EXIT_FAILURE); + + fmap = (struct fmap *)(image + fmap_loc); + + for (i = 0; i < max_regions; i++) { + if (region_names[i].fmapname == NULL) + continue; + + region_t region = get_region(frba, i); + + if (region.size == 0) + continue; + + const struct fmap_area *area = + fmap_find_area(fmap, region_names[i].fmapname); + + if (!area) + continue; + + if ((uint)region.base != area->offset || + (uint)region.size != area->size) { + printf("Region mismatch between %s and %s\n", + region_names[i].terse, area->name); + printf(" Descriptor region %s:\n", region_names[i].terse); + printf(" offset: 0x%08x\n", region.base); + printf(" length: 0x%08x\n", region.size); + printf(" FMAP area %s:\n", area->name); + printf(" offset: 0x%08x\n", area->offset); + printf(" length: 0x%08x\n", area->size); + errors++; + } + } + + if (errors > 0) + exit(EXIT_FAILURE); +} + static void write_image(const char *filename, char *image, int size) { char new_filename[FILENAME_MAX]; // allow long file names @@ -1359,6 +1405,7 @@ printf("\n" " -d | --dump: dump intel firmware descriptor\n" " -f | --layout <filename> dump regions into a flashrom layout file\n" + " -t | --validate Validate that the firmware descriptor layout matches the fmap layout\n" " -x | --extract: extract intel fd modules\n" " -i | --inject <region>:<module> inject file <module> into region <region>\n" " -n | --newlayout <filename> update regions using a flashrom layout file\n" @@ -1388,7 +1435,7 @@ { int opt, option_index = 0; int mode_dump = 0, mode_extract = 0, mode_inject = 0, mode_spifreq = 0; - int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0; + int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0; int mode_layout = 0, mode_newlayout = 0, mode_density = 0; int mode_altmedisable = 0, altmedisable = 0; char *region_type_string = NULL, *region_fname = NULL; @@ -1413,10 +1460,11 @@ {"version", 0, NULL, 'v'}, {"help", 0, NULL, 'h'}, {"platform", 0, NULL, 'p'}, + {"validate", 0, NULL, 't'}, {0, 0, 0, 0} }; - while ((opt = getopt_long(argc, argv, "df:D:C:M:xi:n:s:p:eluvh?", + while ((opt = getopt_long(argc, argv, "df:D:C:M:xi:n:s:p:eluvth?", long_options, &option_index)) != EOF) { switch (opt) { case 'd': @@ -1593,6 +1641,9 @@ } fprintf(stderr, "Platform is: %s\n", optarg); break; + case 't': + mode_validate = 1; + break; case 'v': print_version(); exit(EXIT_SUCCESS); @@ -1608,7 +1659,7 @@ if ((mode_dump + mode_layout + mode_extract + mode_inject + mode_newlayout + (mode_spifreq | mode_em100 | mode_unlocked | - mode_locked) + mode_altmedisable) > 1) { + mode_locked) + mode_altmedisable + mode_layout) > 1) { fprintf(stderr, "You may not specify more than one mode.\n\n"); print_usage(argv[0]); exit(EXIT_FAILURE); @@ -1616,7 +1667,8 @@ if ((mode_dump + mode_layout + mode_extract + mode_inject + mode_newlayout + mode_spifreq + mode_em100 + mode_locked + - mode_unlocked + mode_density + mode_altmedisable) == 0) { + mode_unlocked + mode_density + mode_altmedisable + + mode_validate) == 0) { fprintf(stderr, "You need to specify a mode.\n\n"); print_usage(argv[0]); exit(EXIT_FAILURE); @@ -1667,6 +1719,9 @@ if (mode_extract) write_regions(image, size); + if (mode_validate) + validate_layout(image, size); + if (mode_inject) inject_region(filename, image, size, region_type, region_fname); diff --git a/util/ifdtool/ifdtool.h b/util/ifdtool/ifdtool.h index f3b9a53..195a09c 100644 --- a/util/ifdtool/ifdtool.h +++ b/util/ifdtool/ifdtool.h @@ -165,4 +165,5 @@ const char *pretty; const char *terse; const char *filename; + const char *fmapname; }; -- To view, visit https://review.coreboot.org/c/coreboot/+/34802 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idebf105dee1b8f829d54bd65c82867af7aa4aded Gerrit-Change-Number: 34802 Gerrit-PatchSet: 1 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: libpayload: refactor fetching cbmem pointers
by Patrick Georgi (Code Review) 03 Oct '19

03 Oct '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35756 ) Change subject: libpayload: refactor fetching cbmem pointers ...................................................................... libpayload: refactor fetching cbmem pointers There's a recurring pattern of reading cbtable entries that point into cbmem entries. Move that pattern into its own function. Coccinelle patch used for this: @@ identifier T, T2; expression TARGET; @@ -struct cb_cbmem_tab *const T2 = (struct cb_cbmem_tab *)T; -TARGET = phys_to_virt(T2->cbmem_tab); +TARGET = get_cbmem_ptr(T); Change-Id: I7bd4a7ad8baeeaebf0fa7d4b4de6dbc719bc781f Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M payloads/libpayload/arch/x86/coreboot.c M payloads/libpayload/include/coreboot_tables.h M payloads/libpayload/libc/coreboot.c 3 files changed, 15 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/35756/1 diff --git a/payloads/libpayload/arch/x86/coreboot.c b/payloads/libpayload/arch/x86/coreboot.c index 3a9eb1a..07adee8 100644 --- a/payloads/libpayload/arch/x86/coreboot.c +++ b/payloads/libpayload/arch/x86/coreboot.c @@ -50,8 +50,7 @@ static void cb_parse_mrc_cache(void *ptr, struct sysinfo_t *info) { - struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr; - info->mrc_cache = phys_to_virt(cbmem->cbmem_tab); + info->mrc_cache = get_cbmem_ptr(ptr); } int cb_parse_arch_specific(struct cb_record *rec, struct sysinfo_t *info) diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index c24d6ac..188f426 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -395,4 +395,6 @@ (void *)(((u8 *) (_rec)) + sizeof(*(_rec)) \ + (sizeof((_rec)->map[0]) * (_idx))) +/* Helper functions */ +void *get_cbmem_ptr(unsigned char *ptr); #endif diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c index e14b144..2ff2090 100644 --- a/payloads/libpayload/libc/coreboot.c +++ b/payloads/libpayload/libc/coreboot.c @@ -42,6 +42,12 @@ /* === Parsing code === */ /* This is the generic parsing code. */ +void *get_cbmem_ptr(unsigned char *ptr) +{ + struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr; + return phys_to_virt(cbmem->cbmem_tab); +} + static void cb_parse_memory(void *ptr, struct sysinfo_t *info) { struct cb_memory *mem = ptr; @@ -128,20 +134,17 @@ static void cb_parse_tstamp(unsigned char *ptr, struct sysinfo_t *info) { - struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr; - info->tstamp_table = phys_to_virt(cbmem->cbmem_tab); + info->tstamp_table = get_cbmem_ptr(ptr); } static void cb_parse_cbmem_cons(unsigned char *ptr, struct sysinfo_t *info) { - struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr; - info->cbmem_cons = phys_to_virt(cbmem->cbmem_tab); + info->cbmem_cons = get_cbmem_ptr(ptr); } static void cb_parse_acpi_gnvs(unsigned char *ptr, struct sysinfo_t *info) { - struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr; - info->acpi_gnvs = phys_to_virt(cbmem->cbmem_tab); + info->acpi_gnvs = get_cbmem_ptr(ptr); } static void cb_parse_board_id(unsigned char *ptr, struct sysinfo_t *info) @@ -193,8 +196,7 @@ static void cb_parse_wifi_calibration(void *ptr, struct sysinfo_t *info) { - struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr; - info->wifi_calibration = phys_to_virt(cbmem->cbmem_tab); + info->wifi_calibration = get_cbmem_ptr(ptr); } static void cb_parse_ramoops(void *ptr, struct sysinfo_t *info) @@ -235,14 +237,12 @@ static void cb_parse_vpd(void *ptr, struct sysinfo_t *info) { - struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr; - info->chromeos_vpd = phys_to_virt(cbmem->cbmem_tab); + info->chromeos_vpd = get_cbmem_ptr(ptr); } static void cb_parse_fmap_cache(void *ptr, struct sysinfo_t *info) { - struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr; - info->fmap_cache = phys_to_virt(cbmem->cbmem_tab); + info->fmap_cache = get_cbmem_ptr(ptr); } #if CONFIG(LP_TIMER_RDTSC) -- To view, visit https://review.coreboot.org/c/coreboot/+/35756 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7bd4a7ad8baeeaebf0fa7d4b4de6dbc719bc781f Gerrit-Change-Number: 35756 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit October 2019