coreboot-gerrit October 2019

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Change in coreboot[master]: superio/ite: Add IT8786E-I
by Felix Held (Code Review) 03 Oct '19

03 Oct '19

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30335 ) Change subject: superio/ite: Add IT8786E-I ...................................................................... Patch Set 8: Since there's no board in tree that is using this SIO code, the SIO cleanup patch 35428 would remove this; since you're working on a board using this chip, please comment on the patch I mentioned that it doesn't get removed -- To view, visit https://review.coreboot.org/c/coreboot/+/30335 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7317da6a72db64f95f9a790ef96ed7a5f93b3aea Gerrit-Change-Number: 30335 Gerrit-PatchSet: 8 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Thu, 03 Oct 2019 14:03:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: superio/ite/it8613e: add support for ITE IT8613E
by Krystian Hebel (Code Review) 03 Oct '19

03 Oct '19

Krystian Hebel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31617 Change subject: superio/ite/it8613e: add support for ITE IT8613E ...................................................................... superio/ite/it8613e: add support for ITE IT8613E This change adds support for the SuperIO chip IT8613E. This chip uses FANs 2-5 and have SmartGuardian always enabled (no ON/OFF control) so it relies on support in common ITE code. LDNs were taken from datasheet. Change-Id: I73c083b7019163c1203a5aabbef7d9d8f5ccb16a Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> --- A src/superio/ite/it8613e/Kconfig A src/superio/ite/it8613e/Makefile.inc A src/superio/ite/it8613e/chip.h A src/superio/ite/it8613e/it8613e.h A src/superio/ite/it8613e/superio.c 5 files changed, 189 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/31617/1 diff --git a/src/superio/ite/it8613e/Kconfig b/src/superio/ite/it8613e/Kconfig new file mode 100644 index 0000000..f09cac2 --- /dev/null +++ b/src/superio/ite/it8613e/Kconfig @@ -0,0 +1,27 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> +## Copyright (C) 2017 Gergely Kiss <mail.gery(a)gmail.com> +## Copyright (C) 2018 Kevin Cody-Little <kcodyjr(a)gmail.com> +## Copyright (C) 2019 Protectli +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SUPERIO_ITE_IT8613E + bool + select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_ENV_CTRL + select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 + select SUPERIO_ITE_ENV_CTRL_8BIT_PWM + select SUPERIO_ITE_ENV_CTRL_5FANS + select SUPERIO_ITE_ENV_CTRL_NO_ONOFF diff --git a/src/superio/ite/it8613e/Makefile.inc b/src/superio/ite/it8613e/Makefile.inc new file mode 100644 index 0000000..75ab26b --- /dev/null +++ b/src/superio/ite/it8613e/Makefile.inc @@ -0,0 +1,19 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> +## Copyright (C) 2017 Gergely Kiss <mail.gery(a)gmail.com> +## Copyright (C) 2019 Protectli +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_SUPERIO_ITE_IT8613E) += superio.c diff --git a/src/superio/ite/it8613e/chip.h b/src/superio/ite/it8613e/chip.h new file mode 100644 index 0000000..65875c8 --- /dev/null +++ b/src/superio/ite/it8613e/chip.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * Copyright (C) 2019 Protectli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_ITE_IT8613E_CHIP_H +#define SUPERIO_ITE_IT8613E_CHIP_H + +#include <superio/ite/common/env_ctrl_chip.h> + +struct superio_ite_it8613e_config { + struct ite_ec_config ec; +}; + +#endif /* SUPERIO_ITE_IT8613E_CHIP_H */ diff --git a/src/superio/ite/it8613e/it8613e.h b/src/superio/ite/it8613e/it8613e.h new file mode 100644 index 0000000..dace936 --- /dev/null +++ b/src/superio/ite/it8613e/it8613e.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2017 Gergely Kiss <mail.gery(a)gmail.com> + * Copyright (C) 2019 Protectli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_ITE_IT8613E_H +#define SUPERIO_ITE_IT8613E_H + +#define IT8613E_SP1 0x01 /* Com1 */ +#define IT8613E_EC 0x04 /* Environment controller */ +#define IT8613E_KBCK 0x05 /* PS/2 keyboard */ +#define IT8613E_KBCM 0x06 /* PS/2 mouse */ +#define IT8613E_GPIO 0x07 /* GPIO */ +#define IT8613E_CIR 0x0a /* Consumer Infrared */ + +#endif /* SUPERIO_ITE_IT8613E_H */ diff --git a/src/superio/ite/it8613e/superio.c b/src/superio/ite/it8613e/superio.c new file mode 100644 index 0000000..6bffc16 --- /dev/null +++ b/src/superio/ite/it8613e/superio.c @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2007 Philipp Degler <pdegler(a)rumms.uni-mannheim.de> + * Copyright (C) 2017 Gergely Kiss <mail.gery(a)gmail.com> + * Copyright (C) 2019 Protectli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <device/pnp.h> +#include <pc80/keyboard.h> +#include <arch/io.h> +#include <stdlib.h> +#include <superio/conf_mode.h> +#include <superio/ite/common/env_ctrl.h> + +#include "chip.h" +#include "it8613e.h" + +static void it8613e_init(struct device *dev) +{ + const struct superio_ite_it8613e_config *conf = dev->chip_info; + const struct resource *res; + + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + case IT8613E_EC: + res = find_resource(dev, PNP_IDX_IO0); + if (!conf || !res) + break; + ite_ec_init(res->base, &conf->ec); + break; + case IT8613E_KBCK: + pc_keyboard_init(NO_AUX_DEVICE); + break; + case IT8613E_KBCM: + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = it8613e_init, + .ops_pnp_mode = &pnp_conf_mode_870155_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + /* Serial Port 1 */ + { NULL, IT8613E_SP1, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0x0ff8, }, + /* Environmental Controller */ + { NULL, IT8613E_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x0ff8, 0x0ffc, }, + /* KBC Keyboard */ + { NULL, IT8613E_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0, + 0x0fff, 0x0fff, }, + /* KBC Mouse */ + { NULL, IT8613E_KBCM, PNP_IRQ0 | PNP_MSC0, }, + /* GPIO */ + { NULL, IT8613E_GPIO, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x0ffc, 0x0fff, }, + /* Consumer Infrared */ + { NULL, IT8613E_CIR, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0x0ff8, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_ite_it8613e_ops = { + CHIP_NAME("ITE IT8613E Super I/O") + .enable_dev = enable_dev, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/31617 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73c083b7019163c1203a5aabbef7d9d8f5ccb16a Gerrit-Change-Number: 31617 Gerrit-PatchSet: 1 Gerrit-Owner: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/nehalem: Don't run graphic init on S3 resume
by Arthur Heymans (Code Review) 03 Oct '19

03 Oct '19

Hello Patrick Rudolph, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35773 to look at the new patch set (#8). Change subject: nb/intel/nehalem: Don't run graphic init on S3 resume ...................................................................... nb/intel/nehalem: Don't run graphic init on S3 resume The assumption is made that an ACPI aware an OS does not rely on firmware to initialize the display. TESTED on a Lenovo Thinkpad X201 with Linux 5.2, display still works after S3, more than 200ms in time saved (dropped from 411ms to 182ms in total in one test). Change-Id: I36219e6d04db561d4f2ddb6e962166c598d5bc4f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/nehalem/gma.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/35773/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/35773 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36219e6d04db561d4f2ddb6e962166c598d5bc4f Gerrit-Change-Number: 35773 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: nb/intel/nehalem: Don't run graphic init on S3 resume
by Patrick Rudolph (Code Review) 03 Oct '19

03 Oct '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35773 ) Change subject: nb/intel/nehalem: Don't run graphic init on S3 resume ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/35773 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36219e6d04db561d4f2ddb6e962166c598d5bc4f Gerrit-Change-Number: 35773 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 03 Oct 2019 08:44:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/*/{ms2290,x201}: Complete devicetree
by Arthur Heymans (Code Review) 03 Oct '19

03 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35752 ) Change subject: mb/*/{ms2290,x201}: Complete devicetree ...................................................................... mb/*/{ms2290,x201}: Complete devicetree This will add the southbridge_intel_ibexpeak chip operations to those PCI devices, making it easier to disable them based on the devicetree content. Change-Id: Ia6ba4022b0fe4cab70964fbc08d4e9c3b4fde311 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/x201/devicetree.cb M src/mainboard/packardbell/ms2290/devicetree.cb 2 files changed, 30 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/35752/1 diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index de6d568..d7d4a91 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -74,9 +74,10 @@ register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" - device pci 16.2 on # IDE/SATA - subsystemid 0x17aa 0x2161 - end + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R, only management boot + device pci 16.3 off end # Management Engine KT device pci 19.0 on # Ethernet subsystemid 0x17aa 0x2153 @@ -92,14 +93,19 @@ device pci 1c.0 on end # PCIe Port #1 device pci 1c.1 on end # PCIe Port #2 (wwan) + device pci 1c.2 off end device pci 1c.3 on smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end # PCIe Port #4 (Expresscard) device pci 1c.4 on end # PCIe Port #5 (wlan) + device pci 1c.5 off end + device pci 1c.6 off end + device pci 1c.7 off end device pci 1d.0 on # USB2 EHCI subsystemid 0x17aa 0x2163 end + device pci 1e.0 on end # P2P bridge device pci 1f.0 on # PCI-LPC bridge subsystemid 0x17aa 0x2166 chip superio/nsc/pc87382 @@ -179,6 +185,9 @@ device i2c 5f on end end end + device pci 1f.4 off end + device pci 1f.5 off end + device pci 1f.6 on end end end end diff --git a/src/mainboard/packardbell/ms2290/devicetree.cb b/src/mainboard/packardbell/ms2290/devicetree.cb index c98f9a3..3c912aa 100644 --- a/src/mainboard/packardbell/ms2290/devicetree.cb +++ b/src/mainboard/packardbell/ms2290/devicetree.cb @@ -66,6 +66,13 @@ register "alt_gp_smi_en" = "0x0000" register "gen1_dec" = "0x040069" + device pci 16.0 off end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R, only management boot + device pci 16.3 off end # Management Engine KT + + device pci 19.0 off end # Ethernet + device pci 1a.0 on # USB2 EHCI subsystemid 0x1025 0x0379 end @@ -75,11 +82,18 @@ end device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2 + device pci 1c.2 off end + device pci 1c.3 off end + device pci 1c.4 off end + device pci 1c.5 off end + device pci 1c.6 off end + device pci 1c.7 off end device pci 1d.0 on # USB2 EHCI subsystemid 0x1025 0x0379 end + device pci 1e.0 on end device pci 1f.0 on # PCI-LPC bridge subsystemid 0x1025 0x0379 end @@ -89,6 +103,9 @@ device pci 1f.3 on # SMBUS subsystemid 0x1025 0x0379 end + device pci 1f.4 off end + device pci 1f.5 off end + device pci 1f.6 off end end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/35752 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6ba4022b0fe4cab70964fbc08d4e9c3b4fde311 Gerrit-Change-Number: 35752 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/nehalem: Don't run graphic init on S3 resume
by Arthur Heymans (Code Review) 03 Oct '19

03 Oct '19

Hello Patrick Rudolph, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35773 to look at the new patch set (#4). Change subject: nb/intel/nehalem: Don't run graphic init on S3 resume ...................................................................... nb/intel/nehalem: Don't run graphic init on S3 resume The assumption is made that an ACPI aware an OS does not rely on firmware to initialize the display. TESTED on a Lenovo Thinkpad X201 with Linux 5.2, display still works after S3, more than 200ms in time saved (dropped from 411ms to 182ms in total in one test). Change-Id: I36219e6d04db561d4f2ddb6e962166c598d5bc4f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/nehalem/gma.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/35773/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/35773 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36219e6d04db561d4f2ddb6e962166c598d5bc4f Gerrit-Change-Number: 35773 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: nvramtool: Change binary install directory from sbin to bin
by Paul Menzel (Code Review) 03 Oct '19

03 Oct '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/17573 ) Change subject: nvramtool: Change binary install directory from sbin to bin ...................................................................... Patch Set 3: Jerome, unfortunately you have been unresponsive. I could address the comments, if you do not mind. -- To view, visit https://review.coreboot.org/c/coreboot/+/17573 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5febccf07c0313ed2f1f60142fc76e9c9a4dc27 Gerrit-Change-Number: 17573 Gerrit-PatchSet: 3 Gerrit-Owner: Paul Kocialkowski <contact(a)paulk.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Kocialkowski <contact(a)paulk.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Denis 'GNUtoo' Carikli <GNUtoo(a)cyberdimension.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Comment-Date: Thu, 03 Oct 2019 08:26:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: nvramtool: Change binary install directory from sbin to bin
by Paul Menzel (Code Review) 03 Oct '19

03 Oct '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/17573 ) Change subject: nvramtool: Change binary install directory from sbin to bin ...................................................................... Patch Set 3: > Patch Set 3: > > I think we pretty much expect $(INSTALL) to be gnu, so maybe use -D instead of mkdir? I can do that in a follow-up commit. -- To view, visit https://review.coreboot.org/c/coreboot/+/17573 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5febccf07c0313ed2f1f60142fc76e9c9a4dc27 Gerrit-Change-Number: 17573 Gerrit-PatchSet: 3 Gerrit-Owner: Paul Kocialkowski <contact(a)paulk.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Kocialkowski <contact(a)paulk.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Denis 'GNUtoo' Carikli <GNUtoo(a)cyberdimension.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Comment-Date: Thu, 03 Oct 2019 08:26:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: nvramtool: Change binary install directory from sbin to bin
by Paul Menzel (Code Review) 03 Oct '19

03 Oct '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/17573 ) Change subject: nvramtool: Change binary install directory from sbin to bin ...................................................................... Patch Set 3: > Patch Set 1: > > This is not related to "recent systems" but instead to some GNU/Linux and unix distributions that chose to move the binaries to /usr/bin > > Here's some more background on the decision: > https://www.freedesktop.org/wiki/Software/systemd/TheCaseForTheUsrMerge/ > > Fedora also chose to do it: > https://lists.fedoraproject.org/pipermail/devel/2012-January/161761.html That is something else. /bin → /usr/bin /sbin → /usr/sbin /lib → /usr/lib /lib64 → /usr/lib64 -- To view, visit https://review.coreboot.org/c/coreboot/+/17573 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5febccf07c0313ed2f1f60142fc76e9c9a4dc27 Gerrit-Change-Number: 17573 Gerrit-PatchSet: 3 Gerrit-Owner: Paul Kocialkowski <contact(a)paulk.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Kocialkowski <contact(a)paulk.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Denis 'GNUtoo' Carikli <GNUtoo(a)cyberdimension.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Comment-Date: Thu, 03 Oct 2019 08:25:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/nehalem: Don't run graphic init on S3 resume
by Arthur Heymans (Code Review) 03 Oct '19

03 Oct '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35773 ) Change subject: nb/intel/nehalem: Don't run graphic init on S3 resume ...................................................................... Patch Set 3: (3 comments) https://review.coreboot.org/c/coreboot/+/35773/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/35773/1//COMMIT_MSG@9 PS1, Line 9: ACPI aware an OS > an ACPI aware OS Done https://review.coreboot.org/c/coreboot/+/35773/1//COMMIT_MSG@12 PS1, Line 12: Thinkpda > Thinkpad Done https://review.coreboot.org/c/coreboot/+/35773/1//COMMIT_MSG@13 PS1, Line 13: more than 200ms in time saved. > Woot! What is the current resume time of coreboot? from 411ms to 182ms. So that's indeed pretty fast :-) -- To view, visit https://review.coreboot.org/c/coreboot/+/35773 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36219e6d04db561d4f2ddb6e962166c598d5bc4f Gerrit-Change-Number: 35773 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 03 Oct 2019 08:23:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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coreboot-gerrit October 2019