Krystian Hebel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31617
Change subject: superio/ite/it8613e: add support for ITE IT8613E ......................................................................
superio/ite/it8613e: add support for ITE IT8613E
This change adds support for the SuperIO chip IT8613E. This chip uses FANs 2-5 and have SmartGuardian always enabled (no ON/OFF control) so it relies on support in common ITE code. LDNs were taken from datasheet.
Change-Id: I73c083b7019163c1203a5aabbef7d9d8f5ccb16a Signed-off-by: Krystian Hebel krystian.hebel@3mdeb.com --- A src/superio/ite/it8613e/Kconfig A src/superio/ite/it8613e/Makefile.inc A src/superio/ite/it8613e/chip.h A src/superio/ite/it8613e/it8613e.h A src/superio/ite/it8613e/superio.c 5 files changed, 189 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/31617/1
diff --git a/src/superio/ite/it8613e/Kconfig b/src/superio/ite/it8613e/Kconfig new file mode 100644 index 0000000..f09cac2 --- /dev/null +++ b/src/superio/ite/it8613e/Kconfig @@ -0,0 +1,27 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2014 Edward O'Callaghan eocallaghan@alterapraxis.com +## Copyright (C) 2017 Gergely Kiss mail.gery@gmail.com +## Copyright (C) 2018 Kevin Cody-Little kcodyjr@gmail.com +## Copyright (C) 2019 Protectli +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SUPERIO_ITE_IT8613E + bool + select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_ENV_CTRL + select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 + select SUPERIO_ITE_ENV_CTRL_8BIT_PWM + select SUPERIO_ITE_ENV_CTRL_5FANS + select SUPERIO_ITE_ENV_CTRL_NO_ONOFF diff --git a/src/superio/ite/it8613e/Makefile.inc b/src/superio/ite/it8613e/Makefile.inc new file mode 100644 index 0000000..75ab26b --- /dev/null +++ b/src/superio/ite/it8613e/Makefile.inc @@ -0,0 +1,19 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2006 Uwe Hermann uwe@hermann-uwe.de +## Copyright (C) 2017 Gergely Kiss mail.gery@gmail.com +## Copyright (C) 2019 Protectli +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_SUPERIO_ITE_IT8613E) += superio.c diff --git a/src/superio/ite/it8613e/chip.h b/src/superio/ite/it8613e/chip.h new file mode 100644 index 0000000..65875c8 --- /dev/null +++ b/src/superio/ite/it8613e/chip.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan eocallaghan@alterapraxis.com + * Copyright (C) 2019 Protectli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_ITE_IT8613E_CHIP_H +#define SUPERIO_ITE_IT8613E_CHIP_H + +#include <superio/ite/common/env_ctrl_chip.h> + +struct superio_ite_it8613e_config { + struct ite_ec_config ec; +}; + +#endif /* SUPERIO_ITE_IT8613E_CHIP_H */ diff --git a/src/superio/ite/it8613e/it8613e.h b/src/superio/ite/it8613e/it8613e.h new file mode 100644 index 0000000..dace936 --- /dev/null +++ b/src/superio/ite/it8613e/it8613e.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Uwe Hermann uwe@hermann-uwe.de + * Copyright (C) 2017 Gergely Kiss mail.gery@gmail.com + * Copyright (C) 2019 Protectli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_ITE_IT8613E_H +#define SUPERIO_ITE_IT8613E_H + +#define IT8613E_SP1 0x01 /* Com1 */ +#define IT8613E_EC 0x04 /* Environment controller */ +#define IT8613E_KBCK 0x05 /* PS/2 keyboard */ +#define IT8613E_KBCM 0x06 /* PS/2 mouse */ +#define IT8613E_GPIO 0x07 /* GPIO */ +#define IT8613E_CIR 0x0a /* Consumer Infrared */ + +#endif /* SUPERIO_ITE_IT8613E_H */ diff --git a/src/superio/ite/it8613e/superio.c b/src/superio/ite/it8613e/superio.c new file mode 100644 index 0000000..6bffc16 --- /dev/null +++ b/src/superio/ite/it8613e/superio.c @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Uwe Hermann uwe@hermann-uwe.de + * Copyright (C) 2007 Philipp Degler pdegler@rumms.uni-mannheim.de + * Copyright (C) 2017 Gergely Kiss mail.gery@gmail.com + * Copyright (C) 2019 Protectli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <device/pnp.h> +#include <pc80/keyboard.h> +#include <arch/io.h> +#include <stdlib.h> +#include <superio/conf_mode.h> +#include <superio/ite/common/env_ctrl.h> + +#include "chip.h" +#include "it8613e.h" + +static void it8613e_init(struct device *dev) +{ + const struct superio_ite_it8613e_config *conf = dev->chip_info; + const struct resource *res; + + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + case IT8613E_EC: + res = find_resource(dev, PNP_IDX_IO0); + if (!conf || !res) + break; + ite_ec_init(res->base, &conf->ec); + break; + case IT8613E_KBCK: + pc_keyboard_init(NO_AUX_DEVICE); + break; + case IT8613E_KBCM: + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = it8613e_init, + .ops_pnp_mode = &pnp_conf_mode_870155_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + /* Serial Port 1 */ + { NULL, IT8613E_SP1, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0x0ff8, }, + /* Environmental Controller */ + { NULL, IT8613E_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x0ff8, 0x0ffc, }, + /* KBC Keyboard */ + { NULL, IT8613E_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0, + 0x0fff, 0x0fff, }, + /* KBC Mouse */ + { NULL, IT8613E_KBCM, PNP_IRQ0 | PNP_MSC0, }, + /* GPIO */ + { NULL, IT8613E_GPIO, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x0ffc, 0x0fff, }, + /* Consumer Infrared */ + { NULL, IT8613E_CIR, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0x0ff8, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_ite_it8613e_ops = { + CHIP_NAME("ITE IT8613E Super I/O") + .enable_dev = enable_dev, +};
Hello Felix Held, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31617
to look at the new patch set (#2).
Change subject: superio/ite/it8613e: add support for ITE IT8613E ......................................................................
superio/ite/it8613e: add support for ITE IT8613E
This change adds support for the SuperIO chip IT8613E. This chip uses FANs 2-5 and have SmartGuardian always enabled (no ON/OFF control) so it relies on support in common ITE code. LDNs were taken from datasheet.
Change-Id: I73c083b7019163c1203a5aabbef7d9d8f5ccb16a Signed-off-by: Krystian Hebel krystian.hebel@3mdeb.com --- A src/superio/ite/it8613e/Kconfig A src/superio/ite/it8613e/Makefile.inc A src/superio/ite/it8613e/chip.h A src/superio/ite/it8613e/it8613e.h A src/superio/ite/it8613e/superio.c 5 files changed, 208 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/31617/2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31617 )
Change subject: superio/ite/it8613e: add support for ITE IT8613E ......................................................................
Patch Set 2: Code-Review+1
(3 comments)
https://review.coreboot.org/#/c/31617/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31617/1//COMMIT_MSG@10 PS1, Line 10: have has
https://review.coreboot.org/#/c/31617/1//COMMIT_MSG@11 PS1, Line 11: datasheet What revision?
https://review.coreboot.org/#/c/31617/1/src/superio/ite/it8613e/superio.c File src/superio/ite/it8613e/superio.c:
https://review.coreboot.org/#/c/31617/1/src/superio/ite/it8613e/superio.c@55 PS1, Line 55: .read_resources = pnp_read_resources, Use tabs?
Hello Felix Held, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31617
to look at the new patch set (#3).
Change subject: superio/ite/it8613e: add support for ITE IT8613E ......................................................................
superio/ite/it8613e: add support for ITE IT8613E
This change adds support for the SuperIO chip IT8613E. This chip uses FANs 2-5 and has SmartGuardian always enabled (no ON/OFF control) so it relies on support in common ITE code. LDNs were taken from IT8613E Preliminary Specification V0.3.
Change-Id: I73c083b7019163c1203a5aabbef7d9d8f5ccb16a Signed-off-by: Krystian Hebel krystian.hebel@3mdeb.com --- A src/superio/ite/it8613e/Kconfig A src/superio/ite/it8613e/Makefile.inc A src/superio/ite/it8613e/chip.h A src/superio/ite/it8613e/it8613e.h A src/superio/ite/it8613e/superio.c 5 files changed, 208 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/31617/3
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31617 )
Change subject: superio/ite/it8613e: add support for ITE IT8613E ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/#/c/31617/4/src/superio/ite/it8613e/superio.c File src/superio/ite/it8613e/superio.c:
https://review.coreboot.org/#/c/31617/4/src/superio/ite/it8613e/superio.c@74 PS4, Line 74: 0x0fff is this mask correct? I don't have the datasheet, but this seems a bit unusual to me; guessing from other ITE SIO datasheets, I'd expect 0x0ff8 here (if this is the simple I/O BAR)
Krystian Hebel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31617 )
Change subject: superio/ite/it8613e: add support for ITE IT8613E ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/#/c/31617/4/src/superio/ite/it8613e/superio.c File src/superio/ite/it8613e/superio.c:
https://review.coreboot.org/#/c/31617/4/src/superio/ite/it8613e/superio.c@74 PS4, Line 74: 0x0fff
is this mask correct? I don't have the datasheet, but this seems a bit unusual to me; guessing from […]
I've rechecked it, those are correct according to specification. Some of others ITE chips have identical simple I/O BARs, e.g. IT8783.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31617 )
Change subject: superio/ite/it8613e: add support for ITE IT8613E ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/#/c/31617/4/src/superio/ite/it8613e/superio.c File src/superio/ite/it8613e/superio.c:
https://review.coreboot.org/#/c/31617/4/src/superio/ite/it8613e/superio.c@74 PS4, Line 74: 0x0fff
I've rechecked it, those are correct according to specification. […]
I checked the IT8772E datasheet and there the simple I/O BAR is 8 bytes long: "The accessed I/O ports are programmable and are eight consecutive I/O ports (Base Address+0, Base Address+1, Base Address+2, Base Address+3, Base Address+4, Base Address+5). Base Address is programmed on the registers of GPIO Simple I/O Base Address LSB and MSB registers (LDN=07h, Index=62h and 63h)." This is however not mentioned in the table with the sizes of the different I/O BARs of the SIO.
Krystian Hebel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31617 )
Change subject: superio/ite/it8613e: add support for ITE IT8613E ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/#/c/31617/4/src/superio/ite/it8613e/superio.c File src/superio/ite/it8613e/superio.c:
https://review.coreboot.org/#/c/31617/4/src/superio/ite/it8613e/superio.c@74 PS4, Line 74: 0x0fff
I checked the IT8772E datasheet and there the simple I/O BAR is 8 bytes long: […]
OK, I think I misunderstood how these values are used in coreboot. I was looking at IT8783 code and specification [1]. Does it mean that there is error in code for IT8783?
1: http://www.ite.com.tw/uploads/product_download/IT8783_A_V0.5_062510.pdf
Hello Felix Held, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31617
to look at the new patch set (#9).
Change subject: superio/ite/it8613e: add support for ITE IT8613E ......................................................................
superio/ite/it8613e: add support for ITE IT8613E
This change adds support for the SuperIO chip IT8613E. This chip uses FANs 2-5 and has SmartGuardian always enabled (no ON/OFF control) so it relies on support in common ITE code. LDNs were taken from IT8613E Preliminary Specification V0.3.
Change-Id: I73c083b7019163c1203a5aabbef7d9d8f5ccb16a Signed-off-by: Krystian Hebel krystian.hebel@3mdeb.com --- A src/superio/ite/it8613e/Kconfig A src/superio/ite/it8613e/Makefile.inc A src/superio/ite/it8613e/chip.h A src/superio/ite/it8613e/it8613e.h A src/superio/ite/it8613e/superio.c 5 files changed, 208 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/31617/9
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31617 )
Change subject: superio/ite/it8613e: add support for ITE IT8613E ......................................................................
Patch Set 9: Code-Review+2
(1 comment)
https://review.coreboot.org/#/c/31617/4/src/superio/ite/it8613e/superio.c File src/superio/ite/it8613e/superio.c:
https://review.coreboot.org/#/c/31617/4/src/superio/ite/it8613e/superio.c@74 PS4, Line 74: 0x0fff
OK, I think I misunderstood how these values are used in coreboot. […]
yes, the simple io io range of IT8783 is also 8 bytes long, so 0x0ff8 should also be the correct mask there
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31617 )
Change subject: superio/ite/it8613e: add support for ITE IT8613E ......................................................................
Patch Set 9:
(2 comments)
https://review.coreboot.org/#/c/31617/9/src/superio/ite/it8613e/superio.c File src/superio/ite/it8613e/superio.c:
https://review.coreboot.org/#/c/31617/9/src/superio/ite/it8613e/superio.c@23 PS9, Line 23: #include <arch/io.h> remove
https://review.coreboot.org/#/c/31617/9/src/superio/ite/it8613e/superio.c@24 PS9, Line 24: #include <stdlib.h> why? ARRAY_SIZE() is commonlib/helpers.h
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31617 )
Change subject: superio/ite/it8613e: add support for ITE IT8613E ......................................................................
Patch Set 9: Code-Review+1
oh, didn't check if things needed to be changed after the arch/io patches
Hello Felix Held, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31617
to look at the new patch set (#10).
Change subject: superio/ite/it8613e: add support for ITE IT8613E ......................................................................
superio/ite/it8613e: add support for ITE IT8613E
This change adds support for the SuperIO chip IT8613E. This chip uses FANs 2-5 and has SmartGuardian always enabled (no ON/OFF control) so it relies on support in common ITE code. LDNs were taken from IT8613E Preliminary Specification V0.3.
Change-Id: I73c083b7019163c1203a5aabbef7d9d8f5ccb16a Signed-off-by: Krystian Hebel krystian.hebel@3mdeb.com --- A src/superio/ite/it8613e/Kconfig A src/superio/ite/it8613e/Makefile.inc A src/superio/ite/it8613e/chip.h A src/superio/ite/it8613e/it8613e.h A src/superio/ite/it8613e/superio.c 5 files changed, 206 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/31617/10
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31617 )
Change subject: superio/ite/it8613e: add support for ITE IT8613E ......................................................................
Patch Set 10: Code-Review+2
Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31617 )
Change subject: superio/ite/it8613e: add support for ITE IT8613E ......................................................................
superio/ite/it8613e: add support for ITE IT8613E
This change adds support for the SuperIO chip IT8613E. This chip uses FANs 2-5 and has SmartGuardian always enabled (no ON/OFF control) so it relies on support in common ITE code. LDNs were taken from IT8613E Preliminary Specification V0.3.
Change-Id: I73c083b7019163c1203a5aabbef7d9d8f5ccb16a Signed-off-by: Krystian Hebel krystian.hebel@3mdeb.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/31617 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Felix Held felix-coreboot@felixheld.de --- A src/superio/ite/it8613e/Kconfig A src/superio/ite/it8613e/Makefile.inc A src/superio/ite/it8613e/chip.h A src/superio/ite/it8613e/it8613e.h A src/superio/ite/it8613e/superio.c 5 files changed, 206 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved
diff --git a/src/superio/ite/it8613e/Kconfig b/src/superio/ite/it8613e/Kconfig new file mode 100644 index 0000000..f09cac2 --- /dev/null +++ b/src/superio/ite/it8613e/Kconfig @@ -0,0 +1,27 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2014 Edward O'Callaghan eocallaghan@alterapraxis.com +## Copyright (C) 2017 Gergely Kiss mail.gery@gmail.com +## Copyright (C) 2018 Kevin Cody-Little kcodyjr@gmail.com +## Copyright (C) 2019 Protectli +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SUPERIO_ITE_IT8613E + bool + select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_ENV_CTRL + select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 + select SUPERIO_ITE_ENV_CTRL_8BIT_PWM + select SUPERIO_ITE_ENV_CTRL_5FANS + select SUPERIO_ITE_ENV_CTRL_NO_ONOFF diff --git a/src/superio/ite/it8613e/Makefile.inc b/src/superio/ite/it8613e/Makefile.inc new file mode 100644 index 0000000..75ab26b --- /dev/null +++ b/src/superio/ite/it8613e/Makefile.inc @@ -0,0 +1,19 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2006 Uwe Hermann uwe@hermann-uwe.de +## Copyright (C) 2017 Gergely Kiss mail.gery@gmail.com +## Copyright (C) 2019 Protectli +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_SUPERIO_ITE_IT8613E) += superio.c diff --git a/src/superio/ite/it8613e/chip.h b/src/superio/ite/it8613e/chip.h new file mode 100644 index 0000000..65875c8 --- /dev/null +++ b/src/superio/ite/it8613e/chip.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan eocallaghan@alterapraxis.com + * Copyright (C) 2019 Protectli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_ITE_IT8613E_CHIP_H +#define SUPERIO_ITE_IT8613E_CHIP_H + +#include <superio/ite/common/env_ctrl_chip.h> + +struct superio_ite_it8613e_config { + struct ite_ec_config ec; +}; + +#endif /* SUPERIO_ITE_IT8613E_CHIP_H */ diff --git a/src/superio/ite/it8613e/it8613e.h b/src/superio/ite/it8613e/it8613e.h new file mode 100644 index 0000000..890c249 --- /dev/null +++ b/src/superio/ite/it8613e/it8613e.h @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Uwe Hermann uwe@hermann-uwe.de + * Copyright (C) 2017 Gergely Kiss mail.gery@gmail.com + * Copyright (C) 2019 Protectli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_ITE_IT8613E_H +#define SUPERIO_ITE_IT8613E_H + +/* + * IT8613 supports 2 clock inputs: PCICLK and CLKIN. Multiple registers need + * to be set to choose proper source. PCICLK is required for LPC. + * + * In the table below PD means pull-down, X - don't care. + * + * |-------------------------------------------------------------------| + * | CLKIN | PCICLK | LDN7\ | GBL\ | LDN7\ | LDN7\ | GBL\ | + * | | | 71h[3] | 23h[3] | 2Dh[2] | 2Dh[1] | 23h[0] | + * |--------+--------+---------+---------+---------+---------+---------| + * | PD | 33 MHz | X | 0 | 0 | 0 | 0 | + * | PD | 24 MHz | 1 | 1 | X | 0 | 1 | + * | PD | 25 MHz | X | 0 | 1 | 0 | 0 | + * | 24 MHz | X | 0 | 1 | X | 0 | 1 | + * | 48 MHz | X | 0 | 1 | X | 0 | 0 | + * |-------------------------------------------------------------------| + * + */ + +#define IT8613E_SP1 0x01 /* Com1 */ +#define IT8613E_EC 0x04 /* Environment controller */ +#define IT8613E_KBCK 0x05 /* PS/2 keyboard */ +#define IT8613E_KBCM 0x06 /* PS/2 mouse */ +#define IT8613E_GPIO 0x07 /* GPIO */ +#define IT8613E_CIR 0x0a /* Consumer Infrared */ + +#endif /* SUPERIO_ITE_IT8613E_H */ diff --git a/src/superio/ite/it8613e/superio.c b/src/superio/ite/it8613e/superio.c new file mode 100644 index 0000000..7a4e336 --- /dev/null +++ b/src/superio/ite/it8613e/superio.c @@ -0,0 +1,85 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Uwe Hermann uwe@hermann-uwe.de + * Copyright (C) 2007 Philipp Degler pdegler@rumms.uni-mannheim.de + * Copyright (C) 2017 Gergely Kiss mail.gery@gmail.com + * Copyright (C) 2019 Protectli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <device/pnp.h> +#include <pc80/keyboard.h> +#include <superio/conf_mode.h> +#include <superio/ite/common/env_ctrl.h> + +#include "chip.h" +#include "it8613e.h" + +static void it8613e_init(struct device *dev) +{ + const struct superio_ite_it8613e_config *conf = dev->chip_info; + const struct resource *res; + + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + case IT8613E_EC: + res = find_resource(dev, PNP_IDX_IO0); + if (!conf || !res) + break; + ite_ec_init(res->base, &conf->ec); + break; + case IT8613E_KBCK: + pc_keyboard_init(NO_AUX_DEVICE); + break; + case IT8613E_KBCM: + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = it8613e_init, + .ops_pnp_mode = &pnp_conf_mode_870155_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + /* Serial Port 1 */ + { NULL, IT8613E_SP1, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0x0ff8, }, + /* Environmental Controller */ + { NULL, IT8613E_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x0ff8, 0x0ff8, }, + /* KBC Keyboard */ + { NULL, IT8613E_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0, + 0x0fff, 0x0fff, }, + /* KBC Mouse */ + { NULL, IT8613E_KBCM, PNP_IRQ0 | PNP_MSC0, }, + /* GPIO */ + { NULL, IT8613E_GPIO, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x0ffc, 0x0ff8, }, + /* Consumer Infrared */ + { NULL, IT8613E_CIR, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0x0ff8, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_ite_it8613e_ops = { + CHIP_NAME("ITE IT8613E Super I/O") + .enable_dev = enable_dev, +};
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31617 )
Change subject: superio/ite/it8613e: add support for ITE IT8613E ......................................................................
Patch Set 11:
Since there's no board in tree that is using this SIO code, the SIO cleanup patch 35428 would remove this; since I'm assuming that you're working on a board using this chip, please comment on the patch I mentioned that it doesn't get removed
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Felix Held (Code Review) -
Krystian Hebel (Code Review)
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Kyösti Mälkki (Code Review)
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Nico Huber (Code Review)
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Paul Menzel (Code Review)