coreboot-gerrit October 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: util/crossgcc: Update fls function name for binutils nds32 patch
by Stefan Reinauer (Code Review) 03 Oct '19

03 Oct '19

Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28363 ) Change subject: util/crossgcc: Update fls function name for binutils nds32 patch ...................................................................... Patch Set 1: -Code-Review Is this still needed for the current binutils 2.32 or can we abandon? -- To view, visit https://review.coreboot.org/c/coreboot/+/28363 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff2019bf4fce2e07e4f78605411bb3fc4f324de7 Gerrit-Change-Number: 28363 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 03 Oct 2019 02:15:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: util/release: add gerrit stats script
by Stefan Reinauer (Code Review) 03 Oct '19

03 Oct '19

Stefan Reinauer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/14225 ) Change subject: util/release: add gerrit stats script ...................................................................... util/release: add gerrit stats script This tool downloads, caches and analyzes commits pushed to gerrit for a specified range of commits. Currently it only works over SSH. Data that is printed about the range of commits: CSV Data about each individual commit: - Commit ID - Commit Date - Author - Commiter - Submitter - Lines added - Lines removed - Title - Reviewers It then prints the analysis it did on the data: - Total Commits - Total lines added - Total lines removed - Total difference - Authors - Number of commits - Total Authors - Authors - Lines added - Authors - Lines removed - Reviewers - Number of patches reviewed - Submitters - Number of patches submitted The script relies on a number of perl modules which must be installed separately. Change-Id: I74896a97b5fe370c0b08562ac85d29435e438a31 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/14225 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- A util/release/gerrit_stats.pl 1 file changed, 470 insertions(+), 0 deletions(-) Approvals: Stefan Reinauer: Verified; Looks good to me, approved diff --git a/util/release/gerrit_stats.pl b/util/release/gerrit_stats.pl new file mode 100755 index 0000000..acd5622 --- /dev/null +++ b/util/release/gerrit_stats.pl @@ -0,0 +1,470 @@ +#!/usr/bin/perl + +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015 Google, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +package gerrit_stats; + +# To install any needed modules install the cpanm app, and use it to install the required modules: +# sudo cpan App::cpanminus +# sudo /usr/local/bin/cpanm JSON::Util Net::OpenSSH DateTime Devel::Size + +use strict; +use warnings; +use English qw( -no_match_vars ); +use File::Find; +use File::Path; +use Getopt::Long; +use Getopt::Std; +use JSON::Util; +use Net::OpenSSH; +use Data::Dumper qw(Dumper); +use DateTime; +use Devel::Size qw(size total_size); + +my $old_version; +my $new_version; +my $infodir="$ENV{'HOME'}/.commit_info/" . `git config -l | grep remote.origin.url | sed 's|.*@||' | sed 's|:.*||'`; +chomp($infodir); +my $URL_WITH_USER; +my $SKIP_GERRIT_CHECK; +my $print_commit_list = 1; + +#disable print buffering +$OUTPUT_AUTOFLUSH = 1; +binmode STDOUT, ":utf8"; + +Main(); + +#------------------------------------------------------------------------------- +# Main +#------------------------------------------------------------------------------- +sub Main { + check_arguments(); + + my %submitters = (); + my %authors = (); + my %owners = (); + my %reviewers = (); + my %author_added = (); + my %author_removed = (); + my $total_added = 0; + my $total_removed = 0; + my $number_of_commits = 0; + my $number_of_submitters = 0; + my $submit_epoch = ""; + my $first_submit_epoch = ""; + if (!$URL_WITH_USER) { + get_user() + } + + # make sure the versions exist + check_versions(); + + #fetch patches if needed. Get ids of first and last commits + my @commits = `git log --pretty=%h "$old_version..$new_version" 2>/dev/null`; + get_commits(@commits); + my $last_commit_id = $commits[0]; + my $first_commit_id = $commits[@commits - 1]; + chomp $last_commit_id; + chomp $first_commit_id; + + print "Statistics from commit $first_commit_id to commit $last_commit_id\n"; + print "Patch, Date, Owner, Author, Submitter, Inserted lines, Deleted lines, Subject, Reviewers\n"; + + #loop through all commits + for my $commit_id (@commits) { + $commit_id =~ s/^\s+|\s+$//g; + + my $submitter = ""; + my %patch_reviewers = (); + my $info; + my $owner; + my $author; + my $author_email; + my $inserted_lines = 0; + my $deleted_lines = 0; + my $subject; + + $number_of_commits++; + print "\"$commit_id\", "; + + #read the data file for the current commit + if (-f "$infodir/$commit_id" && -s "$infodir/$commit_id" > 20) { + open( my $HANDLE, "<", "$infodir/$commit_id" ) or die "Error: could not open file '$infodir/$commit_id'\n"; + $info = <$HANDLE>; + close $HANDLE; + + my $commit_info = JSON::Util->decode($info); + + #get the easy data + $owner = $commit_info->{'owner'}{'name'}; + if (! $owner) { + $owner = $commit_info->{'owner'}{'username'}; + } + if (! $owner) { + $owner = ""; + } + $author = $commit_info->{'currentPatchSet'}{'author'}{'name'}; + $author_email = $commit_info->{'currentPatchSet'}{'author'}{'email'}; + if (! $author) { + $author = $commit_info->{'currentPatchSet'}{'author'}{'username'}; + } + + $inserted_lines = $commit_info->{'currentPatchSet'}{'sizeInsertions'}; + $deleted_lines = $commit_info->{'currentPatchSet'}{'sizeDeletions'}; + $subject = $commit_info->{'subject'}; + + #get the patch's submitter + my $approvals = $commit_info->{'currentPatchSet'}{'approvals'}; + for my $approval (@$approvals) { + if ($approval->{'type'} eq "SUBM") { + $submit_epoch = $approval->{'grantedOn'}; + $submitter = $approval->{'by'}{'name'}; + } + } + + #get all the reviewers for all patch revisions + my $patchsets = $commit_info->{'patchSets'}; + for my $patch (@$patchsets) { + if (! $author) { + $author = $patch->{'author'}{'name'}; + } + my $approvals = $patch->{'approvals'}; + for my $approval (@$approvals) { + + if ( (! $submitter) && ($approval->{'type'} eq "SUBM")) { + $submit_epoch = $approval->{'grantedOn'}; + $submitter = $approval->{'by'}{'name'}; + } + + if ($approval->{'type'} eq "Code-Review") { + my $patch_reviewer = $approval->{'by'}{'name'}; + if ($patch_reviewer) { + if (exists $patch_reviewers{$patch_reviewer}) { + $patch_reviewers{$patch_reviewer}++; + } else { + $patch_reviewers{$patch_reviewer} = 1; + } + } + } + } + } + + } else { + # get the info from git + my $logline = `git log --pretty="%ct@@@%s@@@%an@@@%aE@@@%cn" $commit_id^..$commit_id --`; + $logline =~ m/^(.*)@@@(.*)@@@(.*)@@@(.*)@@@(.*)\n/; + ($submit_epoch, $subject, $author, $author_email, $submitter) = ($1, $2, $3, $4, $5); + $owner = $author; + $logline = `git log --pretty= --shortstat $commit_id^..$commit_id --`; + if ($logline =~ m/\s+(\d+)\s+insertion/) { + $inserted_lines = $1; + } + if ($logline =~ m/\s+(\d+)\s+deletion/) { + $deleted_lines = $1 * -1; + } + my @loglines = `git log $commit_id^..$commit_id -- | grep '\\sReviewed-by:'`; + for my $line (@loglines){ + if ($line =~ m/.*:\s+(.*)\s</) { + my $patch_reviewer = $1; + if ($patch_reviewer) { + if (exists $patch_reviewers{$patch_reviewer}) { + $patch_reviewers{$patch_reviewer}++; + } else { + $patch_reviewers{$patch_reviewer} = 1; + } + } + } + } + + } + + # Not entirely certain why this is needed, but for a number of patches have been submitted + # the submit time in gerrit is set to April 9, 2015. + if ($submit_epoch == 1428586219){ + my $logline = `git log --pretty="%ct" $commit_id^..$commit_id --`; + $logline =~ m/^(.*)\n/; + $submit_epoch = $1; + } + + #add the count and owner to the submitter hash + if (exists $submitters{$submitter}) { + $submitters{$submitter}++; + } else { + $submitters{$submitter} = 1; + $number_of_submitters++; + } + + #create a readable date + my $dt = DateTime->from_epoch(epoch => $submit_epoch); + $dt->set_time_zone( 'Europe/Paris' ); + my $submit_time = $dt->strftime('%Y/%m/%d %H:%M:%S'); + if (!$first_submit_epoch) { + $first_submit_epoch = $submit_epoch; + } + + #create the list of reviewers to print + my $reviewerlist = ""; + foreach my $reviewer (keys %patch_reviewers) { + if ($reviewerlist eq "") { + $reviewerlist = $reviewer; + } else { + $reviewerlist .= ", $reviewer"; + } + + if (exists $reviewers{$reviewer}) { + $reviewers{$reviewer}++; + } else { + $reviewers{$reviewer} = 1; + } + } + if (! $reviewerlist) { + $reviewerlist = "-" + } + + if ($print_commit_list) { + print "$submit_time, $owner, $author, $submitter, $inserted_lines, $deleted_lines, \"$subject\", \"$reviewerlist\"\n"; + } else { + print "$number_of_commits\n"; + } + $total_added += $inserted_lines; + $total_removed += $deleted_lines; + if (exists $owners{$owner}) { + $owners{$owner}++; + } else { + $owners{$owner} = 1; + } + + if (exists $authors{$author}{"num"}) { + $authors{$author}{"num"}++; + $author_added{$author} += $inserted_lines; + $author_removed{$author} += $deleted_lines; + $authors{$author}{"earliest_commit"}=$submit_time; + } else { + $authors{$author}{"num"} = 1; + $authors{$author}{"latest_commit"}=$submit_time; + $authors{$author}{"earliest_commit"}=$submit_time; + $author_added{$author} = $inserted_lines; + $author_removed{$author} = $deleted_lines; + } + if (! exists $authors{$author}{email} && $author_email) { + $authors{$author}{email} = "$author_email"; + } + } + my $Days = ($first_submit_epoch - $submit_epoch) / 86400; + if (($first_submit_epoch - $submit_epoch) % 86400) { + $Days += 1; + } + + print "- Total Commits: $number_of_commits\n"; + printf "- Average Commits per day: %.2f\n", $number_of_commits / $Days; + print "- Total lines added: $total_added\n"; + print "- Total lines removed: $total_removed\n"; + print "- Total difference: " . ($total_added + $total_removed) . "\n\n"; + + print "=== Authors - Number of commits ===\n"; + my $number_of_authors = 0; + foreach my $author (sort { $authors{$b}{num} <=> $authors{$a}{num} } (keys %authors) ) { + if (! exists $authors{$author}{"email"}) { + $authors{$author}{"email"} = "-"; + } + printf "%-25s %5d %-40s (%2.2f%%) {%s / %s}\n",$author, $authors{$author}{"num"}, $authors{$author}{"email"}, $authors{$author}{"num"} / $number_of_commits * 100, $authors{$author}{"latest_commit"}, $authors{$author}{"earliest_commit"}; + $number_of_authors++; + } + print "Total Authors: $number_of_authors\n\n"; + + print "=== Authors - Lines added ===\n"; + foreach my $author (sort { $author_added{$b} <=> $author_added{$a} } (keys %author_added) ) { + if ($author_added{$author}) { + printf "%-25s %5d (%2.3f%%)\n",$author, $author_added{$author}, $author_added{$author} / $total_added * 100; + } + } + print "\n"; + + print "=== Authors - Lines removed ===\n"; + foreach my $author (sort { $author_removed{$a} <=> $author_removed{$b} } (keys %author_removed) ) { + if ($author_removed{$author}) { + printf "%-25s %5d (%2.3f%%)\n",$author,$author_removed{$author} * -1, $author_removed{$author} / $total_removed * 100; + } + } + print "\n"; + + print "=== Reviewers - Number of patches reviewed ===\n"; + my $number_of_reviewers = 0; + foreach my $reviewer (sort { $reviewers{$b} <=> $reviewers{$a} } (keys %reviewers) ) { + printf "%-25s %5d (%2.3f%%)\n",$reviewer, $reviewers{$reviewer}, $reviewers{$reviewer} / $number_of_commits * 100; + $number_of_reviewers++; + } + print "Total Reviewers: $number_of_reviewers\n\n"; + + print "=== Submitters - Number of patches submitted ===\n"; + foreach my $submitter (sort { $submitters{$b} <=> $submitters{$a} } (keys %submitters) ) { + printf "%-25s %5d (%2.3f%%)\n",$submitter, $submitters{$submitter}, $submitters{$submitter} / $number_of_commits * 100; + } + print "Total Submitters: $number_of_submitters\n\n"; + + print "Commits, Ave, Added, Removed, Diff, Authors, Reviewers, Submitters\n"; + printf "$number_of_commits, %.2f, $total_added, $total_removed, " . ($total_added + $total_removed) . ", $number_of_authors, $number_of_reviewers, $number_of_submitters\n", $number_of_commits / $Days; +} + +#------------------------------------------------------------------------------- +#------------------------------------------------------------------------------- +sub check_versions { + `git cat-file -e $old_version^{commit} 2>/dev/null`; + if (${^CHILD_ERROR_NATIVE}){ + print "Error: Old version ($old_version) does not exist.\n"; + exit 1; + } + + `git cat-file -e $new_version^{commit} 2>/dev/null`; + if (${^CHILD_ERROR_NATIVE}){ + print "Error: New version ($new_version) does not exist.\n"; + exit 1; + } +} + +#------------------------------------------------------------------------------- +#------------------------------------------------------------------------------- +sub get_user { + my $url=`git config -l | grep remote.origin.url`; + + if ($url =~ /.*url=ssh:\/\/(\w+@[a-zA-Z][a-zA-Z0-9\.]+:\d+)/) + { + $URL_WITH_USER = $1; + } else { + print "Error: Could not get a ssh url with a username from gitconfig.\n"; + print " use the -u option to set a url.\n"; + exit 1; + } +} + +#------------------------------------------------------------------------------- +#------------------------------------------------------------------------------- +sub get_commits { + my @commits = @_; + my $submit_time = ""; + if (defined $SKIP_GERRIT_CHECK) { + return; + } + my $ssh = Net::OpenSSH->new("$URL_WITH_USER", ); + $ssh->error and die "Couldn't establish SSH connection to $URL_WITH_USER:". $ssh->error; + + print "Using URL: ssh://$URL_WITH_USER\n"; + + if (! -d $infodir) { + mkpath($infodir) + } + + for my $commit_id (@commits) { + $commit_id =~ s/^\s+|\s+$//g; + $submit_time = ""; + my $gerrit_review; + + # Quit if we've reeached the last coreboot commit supporting these queries + if ($commit_id =~ /^7309709/) { + last; + } + + if (-f "$infodir/$commit_id") { + $gerrit_review = 1; + } else { + $gerrit_review = `git log $commit_id^..$commit_id | grep '\\sReviewed-on:\\s'`; + } + + if ($gerrit_review && $commit_id && (! -f "$infodir/$commit_id") ) { + print "Downloading $commit_id"; + my @info = $ssh->capture("gerrit query --format=JSON --comments --files --current-patch-set --all-approvals --submit-records --dependencies commit:$commit_id"); + $ssh->error and die "remote ls command failed: " . $ssh->error; + + my $commit_info = JSON::Util->decode($info[0]); + my $rowcount = $commit_info->{'rowCount'}; + if (defined $rowcount && ($rowcount eq "0")) { + print " - no gerrit commit for that id.\n"; + open( my $HANDLE, ">", "$infodir/$commit_id" ) or die "Error: could not open file '$infodir/$commit_id'\n"; + print $HANDLE "No gerrit commit"; + close $HANDLE; + next; + } + my $approvals = $commit_info->{'currentPatchSet'}{'approvals'}; + + for my $approval (@$approvals) { + if ($approval->{'type'} eq "SUBM") { + $submit_time = $approval->{'grantedOn'} + } + } + my $dt=""; + if ($submit_time) { + $dt = DateTime->from_epoch(epoch => $submit_time); + } else { + print " - no submit time for that id.\n"; + open( my $HANDLE, ">", "$infodir/$commit_id" ) or die "Error: could not open file '$infodir/$commit_id'\n"; + print $HANDLE "No submit time"; + close $HANDLE; + + next; + } + + open( my $HANDLE, ">", "$infodir/$commit_id" ) or die "Error: could not open file '$infodir/$commit_id'\n"; + print $HANDLE $info[0]; + close $HANDLE; + + $dt->set_time_zone( 'Europe/Paris' ); + print " - submit time: " . $dt->strftime('%Y/%m/%d %H:%M:%S') . "\n"; + } elsif ($commit_id && (! -f "$infodir/$commit_id")) { + print "No gerrit commit for $commit_id\n"; + open( my $HANDLE, ">", "$infodir/$commit_id" ) or die "Error: could not open file '$infodir/$commit_id'\n"; + print $HANDLE "No gerrit commit"; + close $HANDLE; + } + } + print "\n"; +} + +#------------------------------------------------------------------------------- +# check_arguments parse the command line arguments +#------------------------------------------------------------------------------- +sub check_arguments { + my $show_usage = 0; + GetOptions( + 'help|?' => sub { usage() }, + 'url|u=s' => \$URL_WITH_USER, + 'skip|s' => \$SKIP_GERRIT_CHECK, + ); + # strip ssh:// from url if passed in. + if (defined $URL_WITH_USER) { + $URL_WITH_USER =~ s|ssh://||; + } + if (@ARGV) { + ($old_version, $new_version) = @ARGV; + } else { + usage(); + } +} + +#------------------------------------------------------------------------------- +# usage - Print the arguments for the user +#------------------------------------------------------------------------------- +sub usage { + print "gerrit_stats <options> [Old version] [New version]\n"; + print "Old version should be a tag (4.1), a branch (origin/4.1), or a commit id\n"; + print "New version can be 'HEAD' a branch (origin/master) a tag (4.2), or a commit id\n"; + print " Options:\n"; + print " u | url [url] url with username.\n"; + print "Example: \"$0 -u Gaumless\@review.coreboot.org:29418 origin/4.1 4.2\"\n"; + exit(0); +} + +1; -- To view, visit https://review.coreboot.org/c/coreboot/+/14225 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74896a97b5fe370c0b08562ac85d29435e438a31 Gerrit-Change-Number: 14225 Gerrit-PatchSet: 4 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Assignee: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-MessageType: merged

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Change in coreboot[master]: util/release: add gerrit stats script
by Stefan Reinauer (Code Review) 03 Oct '19

03 Oct '19

Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/14225 ) Change subject: util/release: add gerrit stats script ...................................................................... Patch Set 3: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/14225 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74896a97b5fe370c0b08562ac85d29435e438a31 Gerrit-Change-Number: 14225 Gerrit-PatchSet: 3 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Assignee: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Comment-Date: Thu, 03 Oct 2019 02:12:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: nvramtool: Change binary install directory from sbin to bin
by Stefan Reinauer (Code Review) 03 Oct '19

03 Oct '19

Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/17573 ) Change subject: nvramtool: Change binary install directory from sbin to bin ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/17573 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5febccf07c0313ed2f1f60142fc76e9c9a4dc27 Gerrit-Change-Number: 17573 Gerrit-PatchSet: 3 Gerrit-Owner: Paul Kocialkowski <contact(a)paulk.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Kocialkowski <contact(a)paulk.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Denis 'GNUtoo' Carikli <GNUtoo(a)cyberdimension.org> Gerrit-Comment-Date: Thu, 03 Oct 2019 02:10:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: buildgcc: Run aclocal before configure
by Stefan Reinauer (Code Review) 03 Oct '19

03 Oct '19

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35522 ) Change subject: buildgcc: Run aclocal before configure ...................................................................... buildgcc: Run aclocal before configure Ubuntu 19.04 will fail looking for aclocal-1.15 if the scripts are not regenerated because 19.04 ships with 1.16. There are not enough eyes to roll when working with GNU autotools. Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: I4aa9f520499930ffc984ab0b0144c9c6b2e544a0 --- M util/crossgcc/buildgcc 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/35522/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 9c10c7d..a16d670 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -893,6 +893,7 @@ } build_MAKE() { + ( cd ../${MAKE_DIR}/ && aclocal && autoconf ) CC="$(hostcc host)" CXX="$(hostcxx host)" CFLAGS="$HOSTCFLAGS" \ ../${MAKE_DIR}/configure --prefix="$TARGETDIR" --disable-nls \ || touch .failed -- To view, visit https://review.coreboot.org/c/coreboot/+/35522 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4aa9f520499930ffc984ab0b0144c9c6b2e544a0 Gerrit-Change-Number: 35522 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: util/crossgcc: Add patch for __alloca missing on ubuntu 18.04
by Martin Roth (Code Review) 03 Oct '19

03 Oct '19

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35724 ) Change subject: util/crossgcc: Add patch for __alloca missing on ubuntu 18.04 ...................................................................... util/crossgcc: Add patch for __alloca missing on ubuntu 18.04 Bring this over from the HEADS repo. Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I36dc9860f4c4a2675fd3fa24fa3e534215ceb43e --- A util/crossgcc/patches/make-4.2.1_alloca.patch 1 file changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/35724/1 diff --git a/util/crossgcc/patches/make-4.2.1_alloca.patch b/util/crossgcc/patches/make-4.2.1_alloca.patch new file mode 100644 index 0000000..61a3581 --- /dev/null +++ b/util/crossgcc/patches/make-4.2.1_alloca.patch @@ -0,0 +1,11 @@ +--- clean/make-4.2/glob/glob.c 2013-10-20 17:14:38.000000000 +0000 ++++ make-4.2/glob/glob.c 2018-09-18 10:16:03.860886356 +0000 +@@ -208,7 +208,7 @@ + #endif /* __GNU_LIBRARY__ || __DJGPP__ */ + + +-#if !defined __alloca && !defined __GNU_LIBRARY__ ++#if !defined __alloca && defined __GNU_LIBRARY__ + + # ifdef __GNUC__ + # undef alloca -- To view, visit https://review.coreboot.org/c/coreboot/+/35724 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36dc9860f4c4a2675fd3fa24fa3e534215ceb43e Gerrit-Change-Number: 35724 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: intel/quark: Drop xx_DEV_FUNC
by Kyösti Mälkki (Code Review) 02 Oct '19

02 Oct '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35728 ) Change subject: intel/quark: Drop xx_DEV_FUNC ...................................................................... intel/quark: Drop xx_DEV_FUNC Change-Id: Ice1062d10b793dcbeb5b2ce9e2788fd3b6b6250b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/quark/include/soc/pci_devs.h 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/35728/1 diff --git a/src/soc/intel/quark/include/soc/pci_devs.h b/src/soc/intel/quark/include/soc/pci_devs.h index 1e17402..a24f28f 100644 --- a/src/soc/intel/quark/include/soc/pci_devs.h +++ b/src/soc/intel/quark/include/soc/pci_devs.h @@ -50,25 +50,21 @@ #define SIO2_DEV 0x15 #define I2CGPIO_DEV SIO2_DEV #define I2CGPIO_FUNC 2 -#define I2CGPIO_DEV_FUNC PCI_DEVFN(I2CGPIO_DEV, I2CGPIO_FUNC) #define I2CGPIO_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, I2CGPIO_DEV, I2CGPIO_FUNC) /* PCIe Ports */ #define PCIE_DEV 0x17 #define PCIE_PORT0_DEV PCIE_DEV #define PCIE_PORT0_FUNC 0 -#define PCIE_PORT0_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT0_FUNC) #define PCIE_PORT0_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, PCIE_DEV, PCIE_PORT0_FUNC) #define PCIE_PORT1_DEV PCIE_DEV #define PCIE_PORT1_FUNC 1 -#define PCIE_PORT1_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT1_FUNC) #define PCIE_PORT1_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, PCIE_DEV, PCIE_PORT1_FUNC) /* Platform Controller Unit */ #define LPC_DEV PCI_DEVICE_NUMBER_QNC_LPC #define LPC_FUNC PCI_FUNCTION_NUMBER_QNC_LPC -#define LPC_DEV_FUNC PCI_DEVFN(LPC_DEV, LPC_FUNC) #define LPC_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, LPC_DEV, LPC_FUNC) #endif /* _QUARK_PCI_DEVS_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35728 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice1062d10b793dcbeb5b2ce9e2788fd3b6b6250b Gerrit-Change-Number: 35728 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] intel/skylake: Refactor IRQ assignments
by Kyösti Mälkki (Code Review) 02 Oct '19

02 Oct '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35735 ) Change subject: [WIP] intel/skylake: Refactor IRQ assignments ...................................................................... [WIP] intel/skylake: Refactor IRQ assignments Change-Id: Ifc4795245187f8d70650242a56e6ce771ef2167a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/skylake/include/soc/interrupt.h M src/soc/intel/skylake/irq.c 2 files changed, 44 insertions(+), 86 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/35735/1 diff --git a/src/soc/intel/skylake/include/soc/interrupt.h b/src/soc/intel/skylake/include/soc/interrupt.h index 015ea76..3bf3ca8 100644 --- a/src/soc/intel/skylake/include/soc/interrupt.h +++ b/src/soc/intel/skylake/include/soc/interrupt.h @@ -31,9 +31,9 @@ #define PCH_PHRC 7 #define PCH_MAX_IRQ_CONFIG 8 -#define DEVICE_INT_CONFIG(dev, func, line, irqno) {\ - .Device = dev, \ - .Function = func, \ +#define DEVICE_INT_CONFIG(devfn, line, irqno) {\ + .Device = PCI_SLOT(devfn), \ + .Function = PCI_FUNC(devfn), \ .IntX = line, \ .Irq = irqno } diff --git a/src/soc/intel/skylake/irq.c b/src/soc/intel/skylake/irq.c index ddaffda..6e6d655 100644 --- a/src/soc/intel/skylake/irq.c +++ b/src/soc/intel/skylake/irq.c @@ -28,194 +28,152 @@ * cAVS(Audio, Voice, Speech), INTA is default, programmed in * PciCfgSpace 3Dh */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, - PCI_FUNC(PCH_DEVFN_HDA), int_A, cAVS_INTA_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_HDA, int_A, cAVS_INTA_IRQ), /* * SMBus Controller, no default value, programmed in * PciCfgSpace 3Dh */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, - PCI_FUNC(PCH_DEVFN_SMBUS), int_A, SMBUS_INTA_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_SMBUS, int_A, SMBUS_INTA_IRQ), /* GbE Controller, INTA is default, programmed in PciCfgSpace 3Dh */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, - PCI_FUNC(PCH_DEVFN_GBE), int_A, GbE_INTA_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_GBE, int_A, GbE_INTA_IRQ), /* TraceHub, INTA is default, RO register */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, - PCI_FUNC(PCH_DEVFN_TRACEHUB), int_A, - TRACE_HUB_INTA_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_TRACEHUB, int_A, TRACE_HUB_INTA_IRQ), /* * SerialIo: UART #0, INTA is default, * programmed in PCR[SERIALIO] + PCICFGCTRL[7] */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, - PCI_FUNC(PCH_DEVFN_UART0), int_A, LPSS_UART0_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_UART0, int_A, LPSS_UART0_IRQ), /* * SerialIo: UART #1, INTA is default, * programmed in PCR[SERIALIO] + PCICFGCTRL[8] */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, - PCI_FUNC(PCH_DEVFN_UART1), int_B, LPSS_UART1_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_UART1, int_B, LPSS_UART1_IRQ), /* * SerialIo: SPI #0, INTA is default, * programmed in PCR[SERIALIO] + PCICFGCTRL[10] */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, - PCI_FUNC(PCH_DEVFN_GSPI0), int_C, LPSS_SPI0_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_GSPI0, int_C, LPSS_SPI0_IRQ), /* * SerialIo: SPI #1, INTA is default, * programmed in PCR[SERIALIO] + PCICFGCTRL[11] */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, - PCI_FUNC(PCH_DEVFN_GSPI1), int_D, LPSS_SPI1_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_GSPI1, int_D, LPSS_SPI1_IRQ), /* SCS: eMMC (SKL PCH-LP Only) */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, - PCI_FUNC(PCH_DEVFN_EMMC), int_B, eMMC_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_EMMC, int_B, eMMC_IRQ), /* SCS: SDIO (SKL PCH-LP Only) */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, - PCI_FUNC(PCH_DEVFN_SDIO), int_C, SDIO_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_SDIO, int_C, SDIO_IRQ), /* SCS: SDCard (SKL PCH-LP Only) */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, - PCI_FUNC(PCH_DEVFN_SDCARD), int_D, SD_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_SDCARD, int_D, SD_IRQ), /* PCI Express Port, INT is default, * programmed in PciCfgSpace + FCh */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, - PCI_FUNC(PCH_DEVFN_PCIE9), int_A, PCIE_9_IRQ), - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, - PCI_FUNC(PCH_DEVFN_PCIE10), int_B, PCIE_10_IRQ), - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, - PCI_FUNC(PCH_DEVFN_PCIE11), int_C, PCIE_11_IRQ), - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, - PCI_FUNC(PCH_DEVFN_PCIE12), int_D, PCIE_12_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_PCIE9, int_A, PCIE_9_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_PCIE10, int_B, PCIE_10_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_PCIE11, int_C, PCIE_11_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_PCIE12, int_D, PCIE_12_IRQ), /* * PCI Express Port 1, INT is default, * programmed in PciCfgSpace + FCh */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, - PCI_FUNC(PCH_DEVFN_PCIE1), int_A, PCIE_1_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_PCIE1, int_A, PCIE_1_IRQ), /* * PCI Express Port 2, INT is default, * programmed in PciCfgSpace + FCh */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, - PCI_FUNC(PCH_DEVFN_PCIE2), int_B, PCIE_2_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_PCIE2, int_B, PCIE_2_IRQ), /* * PCI Express Port 3, INT is default, * programmed in PciCfgSpace + FCh */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, - PCI_FUNC(PCH_DEVFN_PCIE3), int_C, PCIE_3_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_PCIE3, int_C, PCIE_3_IRQ), /* * PCI Express Port 4, INT is default, * programmed in PciCfgSpace + FCh */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, - PCI_FUNC(PCH_DEVFN_PCIE4), int_D, PCIE_4_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_PCIE4, int_D, PCIE_4_IRQ), /* * PCI Express Port 5, INT is default, * programmed in PciCfgSpace + FCh */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, - PCI_FUNC(PCH_DEVFN_PCIE5), int_A, PCIE_5_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_PCIE5, int_A, PCIE_5_IRQ), /* * PCI Express Port 6, INT is default, * programmed in PciCfgSpace + FCh */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, - PCI_FUNC(PCH_DEVFN_PCIE6), int_B, PCIE_6_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_PCIE6, int_B, PCIE_6_IRQ), /* * PCI Express Port 7, INT is default, * programmed in PciCfgSpace + FCh */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, - PCI_FUNC(PCH_DEVFN_PCIE7), int_C, PCIE_7_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_PCIE7, int_C, PCIE_7_IRQ), /* * PCI Express Port 8, INT is default, * programmed in PciCfgSpace + FCh */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, - PCI_FUNC(PCH_DEVFN_PCIE8), int_D, PCIE_8_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_PCIE8, int_D, PCIE_8_IRQ), /* * SerialIo UART Controller #2, INTA is default, * programmed in PCR[SERIALIO] + PCICFGCTRL[9] */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2, - PCI_FUNC(PCH_DEVFN_UART2), int_A, LPSS_UART2_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_UART2, int_A, LPSS_UART2_IRQ), /* * SerialIo UART Controller #5, INTA is default, * programmed in PCR[SERIALIO] + PCICFGCTRL[6] */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2, - PCI_FUNC(PCH_DEVFN_I2C5), int_B, LPSS_I2C5_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_I2C5, int_B, LPSS_I2C5_IRQ), /* * SerialIo UART Controller #4, INTA is default, * programmed in PCR[SERIALIO] + PCICFGCTRL[5] */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2, - PCI_FUNC(PCH_DEVFN_I2C4), int_C, LPSS_I2C4_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_I2C4, int_C, LPSS_I2C4_IRQ), /* * SATA Controller, INTA is default, * programmed in PciCfgSpace + 3Dh */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_SATA, - PCI_FUNC(PCH_DEVFN_SATA), int_A, SATA_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_SATA, int_A, SATA_IRQ), /* CSME: HECI #1 */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, - PCI_FUNC(PCH_DEVFN_CSE), int_A, HECI_1_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_CSE, int_A, HECI_1_IRQ), /* CSME: HECI #2 */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, - PCI_FUNC(PCH_DEVFN_CSE_2), int_B, HECI_2_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_CSE_2, int_B, HECI_2_IRQ), /* CSME: IDE-Redirection (IDE-R) */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, - PCI_FUNC(PCH_DEVFN_CSE_IDER), int_C, IDER_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_CSE_IDER, int_C, IDER_IRQ), /* CSME: Keyboard and Text (KT) Redirection */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, - PCI_FUNC(PCH_DEVFN_CSE_KT), int_D, KT_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_CSE_KT, int_D, KT_IRQ), /* CSME: HECI #3 */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, - PCI_FUNC(PCH_DEVFN_CSE_3), int_A, HECI_3_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_CSE_3, int_A, HECI_3_IRQ), /* * SerialIo I2C Controller #0, INTA is default, * programmed in PCR[SERIALIO] + PCICFGCTRL[1] */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, - PCI_FUNC(PCH_DEVFN_I2C0), int_A, LPSS_I2C0_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_I2C0, int_A, LPSS_I2C0_IRQ), /* * SerialIo I2C Controller #1, INTA is default, * programmed in PCR[SERIALIO] + PCICFGCTRL[2] */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, - PCI_FUNC(PCH_DEVFN_I2C1), int_B, LPSS_I2C1_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_I2C1, int_B, LPSS_I2C1_IRQ), /* * SerialIo I2C Controller #2, INTA is default, * programmed in PCR[SERIALIO] + PCICFGCTRL[3] */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, - PCI_FUNC(PCH_DEVFN_I2C2), int_C, LPSS_I2C2_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_I2C2, int_C, LPSS_I2C2_IRQ), /* * SerialIo I2C Controller #3, INTA is default, * programmed in PCR[SERIALIO] + PCICFGCTRL[4] */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, - PCI_FUNC(PCH_DEVFN_I2C3), int_D, LPSS_I2C3_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_I2C3, int_D, LPSS_I2C3_IRQ), /* * USB 3.0 xHCI Controller, no default value, * programmed in PciCfgSpace 3Dh */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, - PCI_FUNC(PCH_DEVFN_XHCI), int_A, XHCI_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_XHCI, int_A, XHCI_IRQ), /* USB Device Controller (OTG) */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, - PCI_FUNC(PCH_DEVFN_USBOTG), int_B, OTG_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_USBOTG, int_B, OTG_IRQ), /* Thermal Subsystem */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, - PCI_FUNC(PCH_DEVFN_THERMAL), int_C, THERMAL_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_THERMAL, int_C, THERMAL_IRQ), /* Camera IO Host Controller */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, - PCI_FUNC(PCH_DEVFN_CIO), int_A, CIO_INTA_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_CIO, int_A, CIO_INTA_IRQ), /* Integrated Sensor Hub */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_ISH, - PCI_FUNC(PCH_DEVFN_ISH), int_A, ISH_IRQ) + DEVICE_INT_CONFIG(PCH_DEVFN_ISH, int_A, ISH_IRQ) }; void soc_irq_settings(FSP_SIL_UPD *params) -- To view, visit https://review.coreboot.org/c/coreboot/+/35735 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc4795245187f8d70650242a56e6ce771ef2167a Gerrit-Change-Number: 35735 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: intel/pci_devs: Regroup PCI xx_DEVID entries
by Kyösti Mälkki (Code Review) 02 Oct '19

02 Oct '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35727 ) Change subject: intel/pci_devs: Regroup PCI xx_DEVID entries ...................................................................... intel/pci_devs: Regroup PCI xx_DEVID entries Change-Id: I953e9a7746232b4c40deca55eb6cb3bd7af91496 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/baytrail/include/soc/pci_devs.h M src/soc/intel/braswell/include/soc/pci_devs.h M src/soc/intel/denverton_ns/include/soc/pci_devs.h M src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h M src/southbridge/intel/fsp_rangeley/pci_devs.h 5 files changed, 152 insertions(+), 145 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/35727/1 diff --git a/src/soc/intel/baytrail/include/soc/pci_devs.h b/src/soc/intel/baytrail/include/soc/pci_devs.h index 4b344f8..c999a1a 100644 --- a/src/soc/intel/baytrail/include/soc/pci_devs.h +++ b/src/soc/intel/baytrail/include/soc/pci_devs.h @@ -21,131 +21,132 @@ /* SoC transaction router */ #define SOC_DEV 0x0 #define SOC_FUNC 0 -# define SOC_DEVID 0x0f00 /* Graphics and Display */ #define GFX_DEV 0x2 #define GFX_FUNC 0 -# define GFX_DEVID 0x0f31 /* SDIO Port */ #define SDIO_DEV 0x11 #define SDIO_FUNC 0 -# define SDIO_DEVID 0x0f15 /* SD Port */ #define SD_DEV 0x12 #define SD_FUNC 0 -# define SD_DEVID 0x0f16 /* SATA */ #define SATA_DEV 0x13 #define SATA_FUNC 0 -#define IDE1_DEVID 0x0f20 -#define IDE2_DEVID 0x0f21 -#define AHCI1_DEVID 0x0f22 -#define AHCI2_DEVID 0x0f23 /* xHCI */ #define XHCI_DEV 0x14 #define XHCI_FUNC 0 -# define XHCI_DEVID 0x0f35 /* LPE Audio */ #define LPE_DEV 0x15 #define LPE_FUNC 0 -# define LPE_DEVID 0x0f28 /* MMC Port */ #define MMC_DEV 0x17 #define MMC_FUNC 0 -# define MMC_DEVID 0x0f50 /* Serial IO 1 */ #define SIO1_DEV 0x18 # define SIO_DMA1_DEV SIO1_DEV # define SIO_DMA1_FUNC 0 -# define SIO_DMA1_DEVID 0x0f40 # define I2C1_DEV SIO1_DEV # define I2C1_FUNC 1 -# define I2C1_DEVID 0x0f41 # define I2C2_DEV SIO1_DEV # define I2C2_FUNC 2 -# define I2C2_DEVID 0x0f42 # define I2C3_DEV SIO1_DEV # define I2C3_FUNC 3 -# define I2C3_DEVID 0x0f43 # define I2C4_DEV SIO1_DEV # define I2C4_FUNC 4 -# define I2C4_DEVID 0x0f44 # define I2C5_DEV SIO1_DEV # define I2C5_FUNC 5 -# define I2C5_DEVID 0x0f45 # define I2C6_DEV SIO1_DEV # define I2C6_FUNC 6 -# define I2C6_DEVID 0x0f46 # define I2C7_DEV SIO1_DEV # define I2C7_FUNC 7 -# define I2C7_DEVID 0x0f47 /* Trusted Execution Engine */ #define TXE_DEV 0x1a #define TXE_FUNC 0 -# define TXE_DEVID 0x0f18 /* HD Audio */ #define HDA_DEV 0x1b #define HDA_FUNC 0 -# define HDA_DEVID 0x0f04 /* PCIe Ports */ #define PCIE_DEV 0x1c # define PCIE_PORT1_DEV PCIE_DEV # define PCIE_PORT1_FUNC 0 -# define PCIE_PORT1_DEVID 0x0f48 # define PCIE_PORT2_DEV PCIE_DEV # define PCIE_PORT2_FUNC 1 -# define PCIE_PORT2_DEVID 0x0f4a # define PCIE_PORT3_DEV PCIE_DEV # define PCIE_PORT3_FUNC 2 -# define PCIE_PORT3_DEVID 0x0f4c # define PCIE_PORT4_DEV PCIE_DEV # define PCIE_PORT4_FUNC 3 -# define PCIE_PORT4_DEVID 0x0f4e /* EHCI */ #define EHCI_DEV 0x1d #define EHCI_FUNC 0 -# define EHCI_DEVID 0x0f34 /* Serial IO 2 */ #define SIO2_DEV 0x1e # define SIO_DMA2_DEV SIO2_DEV # define SIO_DMA2_FUNC 0 -# define SIO_DMA2_DEVID 0x0f06 # define PWM1_DEV SIO2_DEV # define PWM1_FUNC 1 -# define PWM1_DEVID 0x0f08 # define PWM2_DEV SIO2_DEV # define PWM2_FUNC 2 -# define PWM2_DEVID 0x0f09 # define HSUART1_DEV SIO2_DEV # define HSUART1_FUNC 3 -# define HSUART1_DEVID 0x0f0a # define HSUART2_DEV SIO2_DEV # define HSUART2_FUNC 4 -# define HSUART2_DEVID 0x0f0c # define SPI_DEV SIO2_DEV # define SPI_FUNC 5 -# define SPI_DEVID 0xf0e /* Platform Controller Unit */ #define PCU_DEV 0x1f # define LPC_DEV PCU_DEV # define LPC_FUNC 0 -# define LPC_DEVID 0x0f1c # define SMBUS_DEV PCU_DEV # define SMBUS_FUNC 3 + +# define SOC_DEVID 0x0f00 +# define GFX_DEVID 0x0f31 +# define SDIO_DEVID 0x0f15 +# define SD_DEVID 0x0f16 +#define IDE1_DEVID 0x0f20 +#define IDE2_DEVID 0x0f21 +#define AHCI1_DEVID 0x0f22 +#define AHCI2_DEVID 0x0f23 +# define XHCI_DEVID 0x0f35 +# define LPE_DEVID 0x0f28 +# define MMC_DEVID 0x0f50 +# define SIO_DMA1_DEVID 0x0f40 +# define I2C1_DEVID 0x0f41 +# define I2C2_DEVID 0x0f42 +# define I2C3_DEVID 0x0f43 +# define I2C4_DEVID 0x0f44 +# define I2C5_DEVID 0x0f45 +# define I2C6_DEVID 0x0f46 +# define I2C7_DEVID 0x0f47 +# define TXE_DEVID 0x0f18 +# define HDA_DEVID 0x0f04 +# define PCIE_PORT1_DEVID 0x0f48 +# define PCIE_PORT2_DEVID 0x0f4a +# define PCIE_PORT3_DEVID 0x0f4c +# define PCIE_PORT4_DEVID 0x0f4e +# define EHCI_DEVID 0x0f34 +# define SIO_DMA2_DEVID 0x0f06 +# define PWM1_DEVID 0x0f08 +# define PWM2_DEVID 0x0f09 +# define HSUART1_DEVID 0x0f0a +# define HSUART2_DEVID 0x0f0c +# define SPI_DEVID 0xf0e +# define LPC_DEVID 0x0f1c # define SMBUS_DEVID 0x0f12 #endif /* _BAYTRAIL_PCI_DEVS_H_ */ diff --git a/src/soc/intel/braswell/include/soc/pci_devs.h b/src/soc/intel/braswell/include/soc/pci_devs.h index 8b06aff..82ec930 100644 --- a/src/soc/intel/braswell/include/soc/pci_devs.h +++ b/src/soc/intel/braswell/include/soc/pci_devs.h @@ -23,99 +23,76 @@ /* SoC transaction router */ #define SOC_DEV 0x0 #define SOC_FUNC 0 -# define SOC_DEVID 0x2280 /* Graphics and Display */ #define GFX_DEV 0x2 #define GFX_FUNC 0 -# define GFX_DEVID 0x22b1 /* P-Unit DPTF */ #define PUNIT_DEV 0xB #define PUNIT_FUNC 0 -#define PUNIT_DEVID 0x22DC /* MMC Port */ #define MMC_DEV 0x10 #define MMC_FUNC 0 -# define MMC_DEVID 0x2294 /* SDIO Port */ #define SDIO_DEV 0x11 #define SDIO_FUNC 0 -# define SDIO_DEVID 0x2295 /* SD Port */ #define SD_DEV 0x12 #define SD_FUNC 0 -# define SD_DEVID 0x2296 /* SATA */ #define SATA_DEV 0x13 #define SATA_FUNC 0 -#define AHCI1_DEVID 0x22a3 /* xHCI */ #define XHCI_DEV 0x14 #define XHCI_FUNC 0 -#define XHCI_DEVID 0x22b5 /* LPE Audio */ #define LPE_DEV 0x15 #define LPE_FUNC 0 -# define LPE_DEVID 0x22a8 /* Serial IO 1 */ #define SIO1_DEV 0x18 # define SIO_DMA1_DEV SIO1_DEV # define SIO_DMA1_FUNC 0 -# define SIO_DMA1_DEVID 0x22c0 # define I2C1_DEV SIO1_DEV # define I2C1_FUNC 1 -# define I2C1_DEVID 0x22c1 # define I2C2_DEV SIO1_DEV # define I2C2_FUNC 2 -# define I2C2_DEVID 0x22c2 # define I2C3_DEV SIO1_DEV # define I2C3_FUNC 3 -# define I2C3_DEVID 0x22c3 # define I2C4_DEV SIO1_DEV # define I2C4_FUNC 4 -# define I2C4_DEVID 0x22c4 # define I2C5_DEV SIO1_DEV # define I2C5_FUNC 5 -# define I2C5_DEVID 0x22c5 # define I2C6_DEV SIO1_DEV # define I2C6_FUNC 6 -# define I2C6_DEVID 0x22c6 # define I2C7_DEV SIO1_DEV # define I2C7_FUNC 7 -# define I2C7_DEVID 0x22c7 /* Trusted Execution Engine */ #define TXE_DEV 0x1a #define TXE_FUNC 0 -# define TXE_DEVID 0x2298 /* HD Audio */ #define HDA_DEV 0x1b #define HDA_FUNC 0 -# define HDA_DEVID 0x2284 /* PCIe Ports */ #define PCIE_DEV 0x1c # define PCIE_PORT1_DEV PCIE_DEV # define PCIE_PORT1_FUNC 0 -# define PCIE_PORT1_DEVID 0x22c8 # define PCIE_PORT2_DEV PCIE_DEV # define PCIE_PORT2_FUNC 1 -# define PCIE_PORT2_DEVID 0x22ca # define PCIE_PORT3_DEV PCIE_DEV # define PCIE_PORT3_FUNC 2 -# define PCIE_PORT3_DEVID 0x22cc # define PCIE_PORT4_DEV PCIE_DEV # define PCIE_PORT4_FUNC 3 -# define PCIE_PORT4_DEVID 0x22ce /* Total number of ROOT PORTS */ #define MAX_ROOT_PORTS_BSW 4 @@ -123,34 +100,59 @@ #define SIO2_DEV 0x1e # define SIO_DMA2_DEV SIO2_DEV # define SIO_DMA2_FUNC 0 -# define SIO_DMA2_DEVID 0x2286 # define PWM1_DEV SIO2_DEV # define PWM1_FUNC 1 -# define PWM1_DEVID 0x2288 # define PWM2_DEV SIO2_DEV # define PWM2_FUNC 2 -# define PWM2_DEVID 0x2289 # define HSUART1_DEV SIO2_DEV # define HSUART1_FUNC 3 -# define HSUART1_DEVID 0x228a # define HSUART2_DEV SIO2_DEV # define HSUART2_FUNC 4 -# define HSUART2_DEVID 0x228c # define SPI_DEV SIO2_DEV # define SPI_FUNC 5 -# define SPI_DEVID 0x228e /* Platform Controller Unit */ #define PCU_DEV 0x1f # define LPC_DEV PCU_DEV # define LPC_FUNC 0 -# define LPC_DEVID 0x229c # define SMBUS_DEV PCU_DEV # define SMBUS_FUNC 3 -# define SMBUS_DEVID 0x0f12 /* PCH SCC Device Modes */ #define PCH_DISABLED 0 #define PCH_PCI_MODE 1 #define PCH_ACPI_MODE 2 + +# define SOC_DEVID 0x2280 +# define GFX_DEVID 0x22b1 +#define PUNIT_DEVID 0x22DC +# define MMC_DEVID 0x2294 +# define SDIO_DEVID 0x2295 +# define SD_DEVID 0x2296 +#define AHCI1_DEVID 0x22a3 +#define XHCI_DEVID 0x22b5 +# define LPE_DEVID 0x22a8 +# define SIO_DMA1_DEVID 0x22c0 +# define I2C1_DEVID 0x22c1 +# define I2C2_DEVID 0x22c2 +# define I2C3_DEVID 0x22c3 +# define I2C4_DEVID 0x22c4 +# define I2C5_DEVID 0x22c5 +# define I2C6_DEVID 0x22c6 +# define I2C7_DEVID 0x22c7 +# define TXE_DEVID 0x2298 +# define HDA_DEVID 0x2284 +# define PCIE_PORT1_DEVID 0x22c8 +# define PCIE_PORT2_DEVID 0x22ca +# define PCIE_PORT3_DEVID 0x22cc +# define PCIE_PORT4_DEVID 0x22ce +# define SIO_DMA2_DEVID 0x2286 +# define PWM1_DEVID 0x2288 +# define PWM2_DEVID 0x2289 +# define HSUART1_DEVID 0x228a +# define HSUART2_DEVID 0x228c +# define SPI_DEVID 0x228e +# define LPC_DEVID 0x229c +# define SMBUS_DEVID 0x0f12 + #endif /* _SOC_PCI_DEVS_H_ */ diff --git a/src/soc/intel/denverton_ns/include/soc/pci_devs.h b/src/soc/intel/denverton_ns/include/soc/pci_devs.h index a8a6283..faa4d92 100644 --- a/src/soc/intel/denverton_ns/include/soc/pci_devs.h +++ b/src/soc/intel/denverton_ns/include/soc/pci_devs.h @@ -34,157 +34,116 @@ /* SoC transaction router */ #define SA_DEV 0x0 #define SA_FUNC 0 -#define SA_DEVID 0x1980 -#define SA_DEVID_DNVAD 0x1995 #define SOC_DEV SA_DEV #define SOC_FUNC SA_FUNC -#define SOC_DEVID SA_DEVID /* RAS */ #define RAS_DEV 0x4 #define RAS_FUNC 0 -#define RAS_DEVID 0x19a1 /* Root Complex Event Collector */ #define RCEC_DEV 0x5 #define RCEC_FUNC 0 -#define RCEC_DEVID 0x19a2 /* Virtual Root Port 2 */ #define VRP2_DEV 0x6 #define VRP2_FUNC 0 -#define VRP2_DEVID 0x19a3 /* PCIe Root Ports */ #define PCIE_DEV 0x09 #define MAX_PCIE_PORT 0x8 #define PCIE_PORT1_DEV 0x09 #define PCIE_PORT1_FUNC 0 -#define PCIE_PORT1_DEVID 0x19a4 #define PCIE_PORT2_DEV 0x0a #define PCIE_PORT2_FUNC 0 -#define PCIE_PORT2_DEVID 0x19a5 #define PCIE_PORT3_DEV 0x0b #define PCIE_PORT3_FUNC 0 -#define PCIE_PORT3_DEVID 0x19a6 #define PCIE_PORT4_DEV 0x0c #define PCIE_PORT4_FUNC 0 -#define PCIE_PORT4_DEVID 0x19a7 #define PCIE_PORT5_DEV 0x0e #define PCIE_PORT5_FUNC 0 -#define PCIE_PORT5_DEVID 0x19a8 #define PCIE_PORT6_DEV 0x0f #define PCIE_PORT6_FUNC 0 -#define PCIE_PORT6_DEVID 0x19a9 #define PCIE_PORT7_DEV 0x10 #define PCIE_PORT7_FUNC 0 -#define PCIE_PORT7_DEVID 0x19aa #define PCIE_PORT8_DEV 0x11 #define PCIE_PORT8_FUNC 0 -#define PCIE_PORT8_DEVID 0x19ab /* SMBUS 2 */ #define SMBUS2_DEV 0x12 #define SMBUS2_FUNC 0 -#define SMBUS2_DEVID 0x19ac /* SATA */ #define SATA_DEV 0x13 #define SATA_FUNC 0 -#define AHCI_DEVID 0x19b2 #define SATA2_DEV 0x14 #define SATA2_FUNC 0 -#define AHCI2_DEVID 0x19c2 /* xHCI */ #define XHCI_DEV 0x15 #define XHCI_FUNC 0 -#define XHCI_DEVID 0x19d0 /* Virtual Root Port 0 */ #define VRP0_DEV 0x16 #define VRP0_FUNC 0 -#define VRP0_DEVID 0x19d1 /* Virtual Root Port 1 */ #define VRP1_DEV 0x17 #define VRP1_FUNC 0 -#define VRP1_DEVID 0x19d2 /* CSME */ #define ME_HECI_DEV 0x18 #define ME_HECI1_DEV ME_HECI_DEV #define ME_HECI1_FUNC 0 -#define ME_HECI1_DEVID 0x19d3 #define ME_HECI2_DEV ME_HECI_DEV #define ME_HECI2_FUNC 1 -#define ME_HECI2_DEVID 0x19d4 #define ME_IEDR_DEV ME_HECI_DEV #define ME_IEDR_FUNC 2 -#define ME_IEDR_DEVID 0x19ea #define ME_MEKT_DEV ME_HECI_DEV #define ME_MEKT_FUNC 3 -#define ME_MEKT_DEVID 0x19d5 #define ME_HECI3_DEV ME_HECI_DEV #define ME_HECI3_FUNC 4 -#define ME_HECI3_DEVID 0x19d6 /* HSUART */ #define HSUART_DEV 0x1a -#define HSUART_DEVID 0x19d8 #define HSUART1_DEV HSUART_DEV #define HSUART1_FUNC 0 -#define HSUART1_DEVID HSUART_DEVID #define HSUART2_DEV HSUART_DEV #define HSUART2_FUNC 1 -#define HSUART2_DEVID HSUART_DEVID #define HSUART3_DEV HSUART_DEV #define HSUART3_FUNC 2 -#define HSUART3_DEVID HSUART_DEVID /* IE */ #define IE_HECI_DEV 0x1b #define IE_HECI1_DEV IE_HECI_DEV #define IE_HECI1_FUNC 0 -#define IE_HECI1_DEVID 0x19e5 #define IE_HECI2_DEV IE_HECI_DEV #define IE_HECI2_FUNC 1 -#define IE_HECI2_DEVID 0x19e6 #define IE_IEDR_DEV IE_HECI_DEV #define IE_IEDR_FUNC 2 -#define IE_IEDR_DEVID 0x19e7 #define IE_MEKT_DEV IE_HECI_DEV #define IE_MEKT_FUNC 3 -#define IE_MEKT_DEVID 0x19e8 #define IE_HECI3_DEV IE_HECI_DEV #define IE_HECI3_FUNC 4 -#define IE_HECI3_DEVID 0x19e9 /* MMC Port */ #define MMC_DEV 0x1c #define MMC_FUNC 0 -#define MMC_DEVID 0x19db /* Platform Controller Unit */ #define PCU_DEV 0x1f #define LPC_DEV PCU_DEV #define LPC_FUNC 0 -#define LPC_DEVID 0x19dc #define P2SB_DEV PCU_DEV #define P2SB_FUNC 1 -#define P2SB_DEVID 0x19dd #define PMC_DEV PCU_DEV #define PMC_FUNC 2 -#define PMC_DEVID 0x19de #define SMBUS_DEV PCU_DEV #define SMBUS_FUNC 4 -#define SMBUS_DEVID 0x19df #define SPI_DEV PCU_DEV #define SPI_FUNC 5 -#define SPI_DEVID 0x19e0 #define NPK_DEV PCU_DEV #define NPK_FUNC 7 -#define NPK_DEVID 0x19e1 /* TODO - New added */ #define SA_DEV_SLOT_ROOT 0x00 @@ -199,4 +158,46 @@ #define PCH_DEV_LPC _PCH_DEV(LPC, 0) #define PCH_DEV_SPI _PCH_DEV(LPC, 5) +#define SA_DEVID 0x1980 +#define SA_DEVID_DNVAD 0x1995 +#define SOC_DEVID SA_DEVID +#define RAS_DEVID 0x19a1 +#define RCEC_DEVID 0x19a2 +#define VRP2_DEVID 0x19a3 +#define PCIE_PORT1_DEVID 0x19a4 +#define PCIE_PORT2_DEVID 0x19a5 +#define PCIE_PORT3_DEVID 0x19a6 +#define PCIE_PORT4_DEVID 0x19a7 +#define PCIE_PORT5_DEVID 0x19a8 +#define PCIE_PORT6_DEVID 0x19a9 +#define PCIE_PORT7_DEVID 0x19aa +#define PCIE_PORT8_DEVID 0x19ab +#define SMBUS2_DEVID 0x19ac +#define AHCI_DEVID 0x19b2 +#define AHCI2_DEVID 0x19c2 +#define XHCI_DEVID 0x19d0 +#define VRP0_DEVID 0x19d1 +#define VRP1_DEVID 0x19d2 +#define ME_HECI1_DEVID 0x19d3 +#define ME_HECI2_DEVID 0x19d4 +#define ME_IEDR_DEVID 0x19ea +#define ME_MEKT_DEVID 0x19d5 +#define ME_HECI3_DEVID 0x19d6 +#define HSUART_DEVID 0x19d8 +#define HSUART1_DEVID HSUART_DEVID +#define HSUART2_DEVID HSUART_DEVID +#define HSUART3_DEVID HSUART_DEVID +#define IE_HECI1_DEVID 0x19e5 +#define IE_HECI2_DEVID 0x19e6 +#define IE_IEDR_DEVID 0x19e7 +#define IE_MEKT_DEVID 0x19e8 +#define IE_HECI3_DEVID 0x19e9 +#define MMC_DEVID 0x19db +#define LPC_DEVID 0x19dc +#define P2SB_DEVID 0x19dd +#define PMC_DEVID 0x19de +#define SMBUS_DEVID 0x19df +#define SPI_DEVID 0x19e0 +#define NPK_DEVID 0x19e1 + #endif /* _DENVERTON_NS_PCI_DEVS_H_ */ diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h b/src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h index ad8d80a..8de4d19 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h @@ -24,8 +24,6 @@ #define SOC_DEV 0 #define SOC_FUNC 0 -#define SOC_DEVID 0x2F00 -#define SOC_DEVID_ES2 0x6F00 #define SOC_DEV_FUNC PCI_DEVFN(SOC_DEV, SOC_FUNC) /* DMI2/PCIe link to PCH */ @@ -53,24 +51,19 @@ #define VTD_DEV 5 #define VTD_FUNC 0 -#define VTD_DEVID 0x6f28 #define VTD_DEV_FUNC PCI_DEVFN(VTD_DEV, VTD_FUNC) #define VTD_PCI_DEV PCI_DEV(BUS0, VTD_DEV, VTD_FUNC) #define LPC_DEV 31 #define LPC_FUNC 0 -#define LPC_DEVID 0x8C42 -#define LPC_DEVID_ES2 0x8C54 #define LPC_DEV_FUNC PCI_DEVFN(LPC_DEV, LPC_FUNC) #define SATA_DEV 31 #define SATA_FUNC 2 -#define AHCI_DEVID 0x8C02 #define SATA_DEV_FUNC PCI_DEVFN(SATA_DEV, SATA_FUNC) #define SMBUS_DEV 31 #define SMBUS_FUNC 3 -#define SMBUS_DEVID 0x8C22 #define SMBUS_DEV_FUNC PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC) #define SATA2_DEV 31 @@ -79,17 +72,14 @@ #define EHCI1_DEV 29 #define EHCI1_FUNC 0 -#define EHCI1_DEVID 0x8C26 #define EHCI1_DEV_FUNC PCI_DEVFN(EHCI_DEV1, EHCI_FUNC1) #define EHCI2_DEV 26 #define EHCI2_FUNC 0 -#define EHCI2_DEVID 0x8C2D #define EHCI2_DEV_FUNC PCI_DEVFN(EHCI_DEV2, EHCI_FUNC2) #define XHCI_DEV 20 #define XHCI_FUNC 0 -#define XHCI_DEVID 0x8C31 #define XHCI_FUS_REG 0xE0 #define XHCI_FUNC_DISABLE (1 << 0) #define XHCI_USB2PR_REG 0xD0 @@ -97,45 +87,34 @@ #define GBE_DEV 25 #define GBE_FUNC 0 -#define GBE_DEVID 0x8C33 #define GBE_DEV_FUNC PCI_DEVFN(GBE_DEV, GBE_FUNC) #define ME_DEV 22 #define ME_FUNC 0 -#define ME_DEVID 0x8C3A #define ME_DEV_FUNC PCI_DEVFN(ME_DEV, ME_FUNC) #define HDA_DEV 27 #define HDA_FUNC 0 -#define HDA_DEVID 0x8C20 #define HDA_DEV_FUNC PCI_DEVFN(HDA_DEV, HDA_FUNC) /* Ports from PCH block with adjustable burification settings */ #define PCIE_DEV 28 #define PCIE_PORT1_DEV PCIE_DEV #define PCIE_PORT1_FUNC 0 -#define PCIE_PORT1_DEVID 0x8C10 #define PCIE_PORT2_DEV PCIE_DEV #define PCIE_PORT2_FUNC 1 -#define PCIE_PORT2_DEVID 0x8C12 #define PCIE_PORT3_DEV PCIE_DEV #define PCIE_PORT3_FUNC 2 -#define PCIE_PORT3_DEVID 0x8C14 #define PCIE_PORT4_DEV PCIE_DEV #define PCIE_PORT4_FUNC 3 -#define PCIE_PORT4_DEVID 0x8C16 #define PCIE_PORT5_DEV PCIE_DEV #define PCIE_PORT5_FUNC 4 -#define PCIE_PORT5_DEVID 0x8C18 #define PCIE_PORT6_DEV PCIE_DEV #define PCIE_PORT6_FUNC 5 -#define PCIE_PORT6_DEVID 0x8C1A #define PCIE_PORT7_DEV PCIE_DEV #define PCIE_PORT7_FUNC 6 -#define PCIE_PORT7_DEVID 0x8C1C #define PCIE_PORT8_DEV PCIE_DEV #define PCIE_PORT8_FUNC 7 -#define PCIE_PORT8_DEVID 0x8C1E #define PCIE_PORT1_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT1_FUNC) #define PCIE_PORT2_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT2_FUNC) #define PCIE_PORT3_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT3_FUNC) @@ -161,4 +140,27 @@ #define UBOX_DEV 16 #define UBOX_FUNC 7 + +#define SOC_DEVID 0x2F00 +#define SOC_DEVID_ES2 0x6F00 +#define VTD_DEVID 0x6f28 +#define LPC_DEVID 0x8C42 +#define LPC_DEVID_ES2 0x8C54 +#define AHCI_DEVID 0x8C02 +#define SMBUS_DEVID 0x8C22 +#define EHCI1_DEVID 0x8C26 +#define EHCI2_DEVID 0x8C2D +#define XHCI_DEVID 0x8C31 +#define GBE_DEVID 0x8C33 +#define ME_DEVID 0x8C3A +#define HDA_DEVID 0x8C20 +#define PCIE_PORT1_DEVID 0x8C10 +#define PCIE_PORT2_DEVID 0x8C12 +#define PCIE_PORT3_DEVID 0x8C14 +#define PCIE_PORT4_DEVID 0x8C16 +#define PCIE_PORT5_DEVID 0x8C18 +#define PCIE_PORT6_DEVID 0x8C1A +#define PCIE_PORT7_DEVID 0x8C1C +#define PCIE_PORT8_DEVID 0x8C1E + #endif /* _SOC_PCI_DEVS_H_ */ diff --git a/src/southbridge/intel/fsp_rangeley/pci_devs.h b/src/southbridge/intel/fsp_rangeley/pci_devs.h index 29f9085..89f3c5c 100644 --- a/src/southbridge/intel/fsp_rangeley/pci_devs.h +++ b/src/southbridge/intel/fsp_rangeley/pci_devs.h @@ -26,87 +26,71 @@ /* Host Bridge */ #define SOC_DEV 0x0 #define SOC_FUNC 0 -# define SOC_DEVID 0x1f08 # define SOC_DEV_FUNC PCI_DEVFN(SOC_DEV,SOC_FUNC) /* PCIE Port 1 */ #define PCIE_PORT1_DEV 0x1 #define PCIE_PORT1_FUNC 0 -# define PCIE_PORT1_DEVID 0x1f10 # define PCIE_PORT1_DEV_FUNC PCI_DEVFN(PCIE_PORT1_DEV,PCIE_PORT1_FUNC) /* PCIE Port 2 */ #define PCIE_PORT2_DEV 0x2 #define PCIE_PORT2_FUNC 0 -# define PCIE_PORT2_DEVID 0x1f11 # define PCIE_PORT2_DEV_FUNC PCI_DEVFN(PCIE_PORT2_DEV,PCIE_PORT2_FUNC) /* PCIE Port 3 */ #define PCIE_PORT3_DEV 0x3 #define PCIE_PORT3_FUNC 0 -# define PCIE_PORT3_DEVID 0x1f12 # define PCIE_PORT3_DEV_FUNC PCI_DEVFN(PCIE_PORT3_DEV,PCIE_PORT3_FUNC) /* PCIE Port 4 */ #define PCIE_PORT4_DEV 0x4 #define PCIE_PORT4_FUNC 0 -# define PCIE_PORT4_DEVID 0x1f13 # define PCIE_PORT4_DEV_FUNC PCI_DEVFN(PCIE_PORT4_DEV,PCIE_PORT4_FUNC) /* Host Bridge, Fabric, and RAS Registers */ #define HOST_BRIDGE_DEV 0xe #define HOST_BRIDGE_FUNC 0 -# define HOST_BRIDGE_DEVID 0x1f14 # define HOST_BRIDGE_DEV_FUNC PCI_DEVFN(HOST_BRIDGE_DEV,HOST_BRIDGE_FUNC) /* Root Complex Event Collector (RCEC) */ #define RCEC_DEV 0xf #define RCEC_FUNC 0 -# define RCEC_DEVID 0x1f16 # define RCEC_DEV_FUNC PCI_DEVFN(RCEC_DEV,RCEC_FUNC) /* SMBus 2.0 1 */ #define SMBUS1_DEV 0x13 #define SMBUS1_FUNC 0 -# define SMBUS1_DEVID 0x1f15 # define SMBUS1_DEV_FUNC PCI_DEVFN(SMBUS1_DEV,SMBUS1_FUNC) /* Gigabit Ethernet (GbE) */ #define GBE_DEV 0x14 -#define GBE_DEVID 0x1f41 #define GBE1_DEV GBE_DEV #define GBE1_FUNC 0 -# define GBE1_DEVID GBE_DEVID # define GBE1_DEV_FUNC PCI_DEVFN(GBE1_DEV,GBE1_FUNC) #define GBE2_DEV GBE_DEV #define GBE2_FUNC 1 -# define GBE2_DEVID GBE_DEVID # define GBE2_DEV_FUNC PCI_DEVFN(GBE2_DEV,GBE2_FUNC) #define GBE3_DEV GBE_DEV #define GBE3_FUNC 2 -# define GBE3_DEVID GBE_DEVID # define GBE3_DEV_FUNC PCI_DEVFN(GBE3_DEV,GBE3_FUNC) #define GBE4_DEV GBE_DEV #define GBE4_FUNC 3 -# define GBE4_DEVID GBE_DEVID # define GBE4_DEV_FUNC PCI_DEVFN(GBE4_DEV,GBE4_FUNC) /* USB 2.0 */ #define USB2_DEV 0x16 #define USB2_FUNC 0 -# define USB2_DEVID 0x1f2c # define USB2_DEV_FUNC PCI_DEVFN(USB2_DEV,USB2_FUNC) /* SATA Gen 2 */ #define SATA2_DEV 0x17 #define SATA2_FUNC 0 -# define SATA2_DEVID 0x1f22 # define SATA2_DEV_FUNC PCI_DEVFN(SATA2_DEV,SATA2_FUNC) /* SATA Gen 3 */ #define SATA3_DEV 0x18 #define SATA3_FUNC 0 -# define SATA3_DEVID 0x1f32 # define SATA3_DEV_FUNC PCI_DEVFN(SATA3_DEV,SATA3_FUNC) /* Platform Control Unit (PCU) */ @@ -115,20 +99,37 @@ /* Low Pin Count (LPC/ISA) */ #define LPC_DEV PCU_DEV #define LPC_FUNC 0 -# define LPC_DEVID 0x1f38 # define LPC_DEV_FUNC PCI_DEVFN(LPC_DEV,LPC_FUNC) # define LPC_BDF PCI_DEV(BUS0, LPC_DEV, LPC_FUNC) /* SMBus 2.0 0 */ #define SMBUS0_DEV PCU_DEV #define SMBUS0_FUNC 3 -# define SMBUS0_DEVID 0x1f3c # define SMBUS0_DEV_FUNC PCI_DEVFN(SMBUS0_DEV,SMBUS0_FUNC) /* Intel QuickAssist Integrated Accelerator (IQIA) */ #define IQAT_DEV 0xb #define IQAT_FUNC 0 -# define IQAT_DEVID 0x1f18 # define IQAT_DEV_FUNC PCI_DEVFN(IQAT_DEV,IQAT_FUNC) +#define SOC_DEVID 0x1f08 +#define PCIE_PORT1_DEVID 0x1f10 +#define PCIE_PORT2_DEVID 0x1f11 +#define PCIE_PORT3_DEVID 0x1f12 +#define PCIE_PORT4_DEVID 0x1f13 +#define HOST_BRIDGE_DEVID 0x1f14 +#define RCEC_DEVID 0x1f16 +#define SMBUS1_DEVID 0x1f15 +#define GBE_DEVID 0x1f41 +#define GBE1_DEVID GBE_DEVID +#define GBE2_DEVID GBE_DEVID +#define GBE3_DEVID GBE_DEVID +#define GBE4_DEVID GBE_DEVID +#define USB2_DEVID 0x1f2c +#define SATA2_DEVID 0x1f22 +#define SATA3_DEVID 0x1f32 +#define LPC_DEVID 0x1f38 +#define SMBUS0_DEVID 0x1f3c +#define IQAT_DEVID 0x1f18 + #endif /* _RANGELEY_PCI_DEVS_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35727 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I953e9a7746232b4c40deca55eb6cb3bd7af91496 Gerrit-Change-Number: 35727 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skylake: devicetrice: introduce PchHdaVcType parameter for FSP
by Michael Niewöhner (Code Review) 02 Oct '19

02 Oct '19

Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35542 ) Change subject: soc/intel/skylake: devicetrice: introduce PchHdaVcType parameter for FSP ...................................................................... soc/intel/skylake: devicetrice: introduce PchHdaVcType parameter for FSP Set the FSP Parameter PchHdaVcType from devicetree if needed for a variant. Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Change-Id: Ibafc3b6bd2495658f2bd634218042ec413a89f5e --- M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/asrock/h110m/ramstage.c M src/mainboard/intel/kblrvp/ramstage.c M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb M src/mainboard/supermicro/x11-lga1151-series/ramstage.c M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/chip_fsp20.c 8 files changed, 7 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/35542/1 diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 572cd6a..f6a0bcf 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -55,6 +55,7 @@ register "PmTimerDisabled" = "0" register "EnableAzalia" = "1" register "DspEnable" = "0" + register "PchHdaVcType" = "0x01" register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10" diff --git a/src/mainboard/asrock/h110m/ramstage.c b/src/mainboard/asrock/h110m/ramstage.c index c93e84c..a247b72 100644 --- a/src/mainboard/asrock/h110m/ramstage.c +++ b/src/mainboard/asrock/h110m/ramstage.c @@ -24,6 +24,4 @@ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); params->CdClock = 3; - /* Enable Virtual Channel 1 */ - params->PchHdaVcType = 0x1; } diff --git a/src/mainboard/intel/kblrvp/ramstage.c b/src/mainboard/intel/kblrvp/ramstage.c index ad55c26..a19e96e 100644 --- a/src/mainboard/intel/kblrvp/ramstage.c +++ b/src/mainboard/intel/kblrvp/ramstage.c @@ -25,9 +25,6 @@ * dependencies during hardware initialization. */ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); params->CdClock = 3; - - /* Enable Virtual Channel 1 */ - params->PchHdaVcType = 0x1; } static void ioexpander_init(void *unused) diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb index 2a1cb8a..43c16e3 100644 --- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb @@ -30,6 +30,7 @@ register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" register "SaGv" = "SaGv_Enabled" + register "PchHdaVcType" = "0x01" register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10" diff --git a/src/mainboard/supermicro/x11-lga1151-series/ramstage.c b/src/mainboard/supermicro/x11-lga1151-series/ramstage.c index 677a10f..a16678e 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/ramstage.c +++ b/src/mainboard/supermicro/x11-lga1151-series/ramstage.c @@ -20,9 +20,4 @@ /* Configure pads prior to SiliconInit() in case there's any * dependencies during hardware initialization. */ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); - - // TODO: on x11ssm FSP does not crash as in x11ssh; even when explicitly setting to 0x0 - // probably can be removed here - /* This must be one, otherwise FSP crashes ... */ - params->PchHdaVcType = 0x1; } diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb index 1039f7a..02db50c 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb @@ -30,6 +30,9 @@ register "PcieRpEnable[8]" = "1" register "PcieRpClkReqSupport[8]" = "0" + # FIXME: find out why FSP crashes without this + register "PchHdaVcType" = "0x01" + device domain 0 on device pci 01.0 on end # unused device pci 01.1 on # PCIE Slot (JPCIE1) diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index fee14d8..dc263a2 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -207,6 +207,7 @@ /* Audio related */ u8 EnableAzalia; u8 DspEnable; + u8 PchHdaVcType; /* * I/O Buffer Ownership: diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index d1d7d6f..4fa34b0 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -361,6 +361,7 @@ params->PchIshEnable = dev ? dev->enabled : 0; params->PchHdaEnable = config->EnableAzalia; + params->PchHdaVcType = config->PchHdaVcType; params->PchHdaIoBufferOwnership = config->IoBufferOwnership; params->PchHdaDspEnable = config->DspEnable; params->Device4Enable = config->Device4Enable; -- To view, visit https://review.coreboot.org/c/coreboot/+/35542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibafc3b6bd2495658f2bd634218042ec413a89f5e Gerrit-Change-Number: 35542 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-MessageType: newchange

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coreboot-gerrit October 2019