coreboot-gerrit October 2019

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Change in coreboot[master]: sb/intel/i82801gx: Correctly align register offset
by Arthur Heymans (Code Review) 01 Oct '19

01 Oct '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35737 ) Change subject: sb/intel/i82801gx: Correctly align register offset ...................................................................... Patch Set 2: (1 comment) Thx for finding this. https://review.coreboot.org/c/coreboot/+/35737/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/35737/2//COMMIT_MSG@7 PS2, Line 7: Correctly align register offset The register is simply wrong, but include/device/pci_mmio_cfg.h automatically aligns it, which is why it works... -- To view, visit https://review.coreboot.org/c/coreboot/+/35737 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33509befe86ff6e333c559c87a0f45886d737df9 Gerrit-Change-Number: 35737 Gerrit-PatchSet: 2 Gerrit-Owner: Petr Cvek <petrcvekcz(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Petr Cvek <petrcvekcz(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 01 Oct 2019 12:35:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sb/intel/i82801gx: Correctly align register offset
by Arthur Heymans (Code Review) 01 Oct '19

01 Oct '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35737 ) Change subject: sb/intel/i82801gx: Correctly align register offset ...................................................................... Patch Set 2: (3 comments) https://review.coreboot.org/c/coreboot/+/35737/2/src/southbridge/intel/i828… File src/southbridge/intel/i82801gx/sata.c: https://review.coreboot.org/c/coreboot/+/35737/2/src/southbridge/intel/i828… PS2, Line 97: u32 define as u8 * https://review.coreboot.org/c/coreboot/+/35737/2/src/southbridge/intel/i828… PS2, Line 158: ahci_ struct resource *ahci_res = find_resource(dev, PCI_BASE_ADDRESS_5); if (ahci_res != NULL) { ahci_bar = res2mmio(ahci_res); write32(ahci_bar + 0xc, config->sata_ports_implemented); } https://review.coreboot.org/c/coreboot/+/35737/2/src/southbridge/intel/i828… PS2, Line 158: 0x24 PCI_BASE_ADDRESS_5 -- To view, visit https://review.coreboot.org/c/coreboot/+/35737 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33509befe86ff6e333c559c87a0f45886d737df9 Gerrit-Change-Number: 35737 Gerrit-PatchSet: 2 Gerrit-Owner: Petr Cvek <petrcvekcz(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Petr Cvek <petrcvekcz(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 01 Oct 2019 12:30:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sb/intel/i82801gx: Correctly align register offset
by Paul Menzel (Code Review) 01 Oct '19

01 Oct '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35737 ) Change subject: sb/intel/i82801gx: Correctly align register offset ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/35737/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/35737/2//COMMIT_MSG@10 PS2, Line 10: Please add to the commit message, if this fixes an actual problem, and how this is tested. -- To view, visit https://review.coreboot.org/c/coreboot/+/35737 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33509befe86ff6e333c559c87a0f45886d737df9 Gerrit-Change-Number: 35737 Gerrit-PatchSet: 2 Gerrit-Owner: Petr Cvek <petrcvekcz(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Petr Cvek <petrcvekcz(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 01 Oct 2019 11:47:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mediatek/mt8183: Set DRAM voltage for each DRAM frequency
by Hung-Te Lin (Code Review) 01 Oct '19

01 Oct '19

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35017 ) Change subject: mediatek/mt8183: Set DRAM voltage for each DRAM frequency ...................................................................... Patch Set 11: > also I really think we can avoid the use of '#if Xplease try to avoid @huayaXX'. Type. also I really think we can avoid the use of '#if XXX'. -- To view, visit https://review.coreboot.org/c/coreboot/+/35017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9539473ff708f9d0d39eb17bd3fdcb916265d33e Gerrit-Change-Number: 35017 Gerrit-PatchSet: 11 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-Reviewer: Huayang Duan <huayang.duan(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-Reviewer: huayang duan <huayangduan(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 01 Oct 2019 08:27:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mediatek/mt8183: Set DRAM voltage for each DRAM frequency
by Hung-Te Lin (Code Review) 01 Oct '19

01 Oct '19

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35017 ) Change subject: mediatek/mt8183: Set DRAM voltage for each DRAM frequency ...................................................................... Patch Set 11: Code-Review-1 @huayang, please remove the +2 and address the feedbacks in comments. also I really think we can avoid the use of '#if Xplease try to avoid @huayaXX'. -- To view, visit https://review.coreboot.org/c/coreboot/+/35017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9539473ff708f9d0d39eb17bd3fdcb916265d33e Gerrit-Change-Number: 35017 Gerrit-PatchSet: 11 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-Reviewer: Huayang Duan <huayang.duan(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-Reviewer: huayang duan <huayangduan(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 01 Oct 2019 08:27:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: intel/fsp_broadwell_de: Rename from xx_DEV_FUNC
by Frans Hendriks (Code Review) 01 Oct '19

01 Oct '19

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35734 ) Change subject: intel/fsp_broadwell_de: Rename from xx_DEV_FUNC ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/c/coreboot/+/35734/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/35734/1//COMMIT_MSG@7 PS1, Line 7: intel/fsp_broadwell_de: Rename from xx_DEV_FUNC What is the reason for renaming? https://review.coreboot.org/c/coreboot/+/35734/1/src/soc/intel/fsp_broadwel… File src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h: https://review.coreboot.org/c/coreboot/+/35734/1/src/soc/intel/fsp_broadwel… PS1, Line 118: #define PCIE_PORT1_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT1_FUNC) Deleting of these lines is not mentioned in comment -- To view, visit https://review.coreboot.org/c/coreboot/+/35734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a8675a4e613a8efc135b05cde36f166acaa7ed4 Gerrit-Change-Number: 35734 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 01 Oct 2019 07:11:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sb/intel/i82801gx: Correctly align register offset
by HAOUAS Elyes (Code Review) 01 Oct '19

01 Oct '19

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35737 ) Change subject: sb/intel/i82801gx: Correctly align register offset ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/35737 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33509befe86ff6e333c559c87a0f45886d737df9 Gerrit-Change-Number: 35737 Gerrit-PatchSet: 2 Gerrit-Owner: Petr Cvek <petrcvekcz(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Petr Cvek <petrcvekcz(a)gmail.com> Gerrit-Comment-Date: Tue, 01 Oct 2019 05:53:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: intel/i945: Define peg_plugin for potential add-on PCIe card
by Kyösti Mälkki (Code Review) 01 Oct '19

01 Oct '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35677 ) Change subject: intel/i945: Define peg_plugin for potential add-on PCIe card ...................................................................... intel/i945: Define peg_plugin for potential add-on PCIe card Change-Id: I06f6a7ed7a1ce935d154b8c7b11dcb81608329b9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/northbridge/intel/i945/early_init.c 1 file changed, 10 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/35677/1 diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index c53577b..d6d37d9 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -531,6 +531,9 @@ u16 reg16; pci_devfn_t p2peg = PCI_DEV(0, 0x01, 0); + u8 tmp_secondary = 0x0a; + pci_devfn_t peg_plugin = PCI_DEV(tmp_secondary, 0, 0); + printk(BIOS_DEBUG, "Enabling PCI Express x16 Link\n"); reg16 = pci_read_config16(PCI_DEV(0, 0x00, 0), DEVEN); @@ -562,10 +565,10 @@ reg16 |= (1 << 4) | (1 << 0); pci_write_config16(p2peg, SLOTSTS, reg16); - pci_write_config8(p2peg, SBUSN1, 0x00); - pci_write_config8(p2peg, SUBUSN1, 0x00); - pci_write_config8(p2peg, SBUSN1, 0x0a); - pci_write_config8(p2peg, SUBUSN1, 0x0a); + pci_write_config8(p2peg, PCI_SECONDARY_BUS, 0x00); + pci_write_config8(p2peg, PCI_SUBORDINATE_BUS, 0x00); + pci_write_config8(p2peg, PCI_SECONDARY_BUS, tmp_secondary); + pci_write_config8(p2peg, PCI_SUBORDINATE_BUS, tmp_secondary); reg32 = pci_read_config32(p2peg, 0x224); reg32 &= ~(1 << 8); @@ -597,7 +600,7 @@ && --timeout) ; - reg32 = pci_read_config32(PCI_DEV(0x0a, 0x0, 0), 0); + reg32 = pci_read_config32(peg_plugin, PCI_VENDOR_ID); if (reg32 != 0x00000000 && reg32 != 0xffffffff) { printk(BIOS_DEBUG, " Detected PCIe device %04x:%04x\n", reg32 & 0xffff, reg32 >> 16); @@ -623,7 +626,7 @@ && --timeout) ; - reg32 = pci_read_config32(PCI_DEV(0xa, 0x00, 0), 0); + reg32 = pci_read_config32(peg_plugin, PCI_VENDOR_ID); if (reg32 != 0x00000000 && reg32 != 0xffffffff) { printk(BIOS_DEBUG, " Detected PCIe x1 device %04x:%04x\n", reg32 & 0xffff, reg32 >> 16); @@ -651,7 +654,7 @@ // TODO /* pci_write_config32(p2peg, PEGTC, reg32); */ - reg32 = (pci_read_config32(PCI_DEV(0xa, 0, 0), 0x8) >> 8); + reg32 = (pci_read_config32(peg_plugin, 0x8) >> 8); printk(BIOS_DEBUG, "PCIe device class: %06x\n", reg32); if (reg32 == 0x030000) { printk(BIOS_DEBUG, "PCIe device is VGA. Disabling IGD.\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/35677 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06f6a7ed7a1ce935d154b8c7b11dcb81608329b9 Gerrit-Change-Number: 35677 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: intel/i945: Delay bridge VGA IO enable to ramstage
by Kyösti Mälkki (Code Review) 01 Oct '19

01 Oct '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35676 ) Change subject: intel/i945: Delay bridge VGA IO enable to ramstage ...................................................................... intel/i945: Delay bridge VGA IO enable to ramstage Change-Id: Ifc54ecc96b6d9d79d5a16b2d7baeae70b59275c9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/northbridge/intel/i945/early_init.c 1 file changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/35676/1 diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 791baec..c53577b 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -661,11 +661,6 @@ reg32 = pci_read_config32(PCI_DEV(0, 0x0, 0), DEVEN); reg32 &= ~(DEVEN_D2F0 | DEVEN_D2F1); pci_write_config32(PCI_DEV(0, 0x0, 0), DEVEN, reg32); - - /* Set VGA enable bit in PCIe bridge */ - reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL); - reg16 |= PCI_BRIDGE_CTL_VGA; - pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16); } /* Enable GPEs */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc54ecc96b6d9d79d5a16b2d7baeae70b59275c9 Gerrit-Change-Number: 35676 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: intel/i945: Define p2peg for PCIe x16 slot
by Kyösti Mälkki (Code Review) 01 Oct '19

01 Oct '19

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35675 ) Change subject: intel/i945: Define p2peg for PCIe x16 slot ...................................................................... intel/i945: Define p2peg for PCIe x16 slot Change-Id: I0e9dd06376c1076be4a4c41ff87dfd3cf820d7bc Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35675 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/i945/early_init.c 1 file changed, 82 insertions(+), 80 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index ebff49c..791baec 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -529,6 +529,7 @@ u32 timeout; u32 reg32; u16 reg16; + pci_devfn_t p2peg = PCI_DEV(0, 0x01, 0); printk(BIOS_DEBUG, "Enabling PCI Express x16 Link\n"); @@ -536,9 +537,9 @@ reg16 |= DEVEN_D1F0; pci_write_config16(PCI_DEV(0, 0x00, 0), DEVEN, reg16); - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), PEGCC); + reg32 = pci_read_config32(p2peg, PEGCC); reg32 &= ~(1 << 8); - pci_write_config32(PCI_DEV(0, 0x01, 0), PEGCC, reg32); + pci_write_config32(p2peg, PEGCC, reg32); /* We have no success with querying the usual PCIe registers * for link setup success on the i945. Hence we assign a temporary @@ -546,53 +547,53 @@ */ /* First we reset the secondary bus */ - reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL); + reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL); reg16 |= PCI_BRIDGE_CTL_BUS_RESET; - pci_write_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL, reg16); + pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16); /* Read back and clear reset bit. */ - reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL); + reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL); reg16 &= ~PCI_BRIDGE_CTL_BUS_RESET; /* SRESET */ - pci_write_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL, reg16); + pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16); - reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), SLOTSTS); + reg16 = pci_read_config16(p2peg, SLOTSTS); printk(BIOS_DEBUG, "SLOTSTS: %04x\n", reg16); if (!(reg16 & 0x48)) goto disable_pciexpress_x16_link; reg16 |= (1 << 4) | (1 << 0); - pci_write_config16(PCI_DEV(0, 0x01, 0), SLOTSTS, reg16); + pci_write_config16(p2peg, SLOTSTS, reg16); - pci_write_config8(PCI_DEV(0, 0x01, 0), SBUSN1, 0x00); - pci_write_config8(PCI_DEV(0, 0x01, 0), SUBUSN1, 0x00); - pci_write_config8(PCI_DEV(0, 0x01, 0), SBUSN1, 0x0a); - pci_write_config8(PCI_DEV(0, 0x01, 0), SUBUSN1, 0x0a); + pci_write_config8(p2peg, SBUSN1, 0x00); + pci_write_config8(p2peg, SUBUSN1, 0x00); + pci_write_config8(p2peg, SBUSN1, 0x0a); + pci_write_config8(p2peg, SUBUSN1, 0x0a); - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x224); + reg32 = pci_read_config32(p2peg, 0x224); reg32 &= ~(1 << 8); - pci_write_config32(PCI_DEV(0, 0x01, 0), 0x224, reg32); + pci_write_config32(p2peg, 0x224, reg32); MCHBAR16(UPMC1) &= ~((1 << 5) | (1 << 0)); /* Initialize PEG_CAP */ - reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), PEG_CAP); + reg16 = pci_read_config16(p2peg, PEG_CAP); reg16 |= (1 << 8); - pci_write_config16(PCI_DEV(0, 0x01, 0), PEG_CAP, reg16); + pci_write_config16(p2peg, PEG_CAP, reg16); /* Setup SLOTCAP */ /* TODO: These values are mainboard dependent and should * be set from devicetree.cb. */ /* NOTE: SLOTCAP becomes RO after the first write! */ - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), SLOTCAP); + reg32 = pci_read_config32(p2peg, SLOTCAP); reg32 &= 0x0007ffff; reg32 &= 0xfffe007f; - pci_write_config32(PCI_DEV(0, 0x01, 0), SLOTCAP, reg32); + pci_write_config32(p2peg, SLOTCAP, reg32); /* Wait for training to succeed */ printk(BIOS_DEBUG, "PCIe link training ..."); timeout = 0x7ffff; - while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS) >> 16) & 3) != 3) + while ((((pci_read_config32(p2peg, PEGSTS) >> 16) & 3) != 3) && --timeout) ; @@ -605,20 +606,20 @@ printk(BIOS_DEBUG, "Restrain PCIe port to x1\n"); - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS); + reg32 = pci_read_config32(p2peg, PEGSTS); reg32 &= ~(0xf << 1); reg32 |= 1; - pci_write_config32(PCI_DEV(0, 0x01, 0), PEGSTS, reg32); + pci_write_config32(p2peg, PEGSTS, reg32); - reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL); + reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL); reg16 |= PCI_BRIDGE_CTL_BUS_RESET; - pci_write_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL, reg16); + pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16); reg16 &= ~PCI_BRIDGE_CTL_BUS_RESET; - pci_write_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL, reg16); + pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16); printk(BIOS_DEBUG, "PCIe link training ..."); timeout = 0x7ffff; - while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS) >> 16) & 3) != 3) + while ((((pci_read_config32(p2peg, PEGSTS) >> 16) & 3) != 3) && --timeout) ; @@ -633,22 +634,22 @@ } } - reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0xb2); + reg16 = pci_read_config16(p2peg, 0xb2); reg16 >>= 4; reg16 &= 0x3f; /* reg16 == 1 -> x1; reg16 == 16 -> x16 */ printk(BIOS_DEBUG, "PCIe x%d link training succeeded.\n", reg16); - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), PEGTC); + reg32 = pci_read_config32(p2peg, PEGTC); reg32 &= 0xfffffc00; /* clear [9:0] */ if (reg16 == 1) reg32 |= 0x32b; // TODO - /* pci_write_config32(PCI_DEV(0, 0x01, 0), PEGTC, reg32); */ + /* pci_write_config32(p2peg, PEGTC, reg32); */ else if (reg16 == 16) reg32 |= 0x0f4; // TODO - /* pci_write_config32(PCI_DEV(0, 0x01, 0), PEGTC, reg32); */ + /* pci_write_config32(p2peg, PEGTC, reg32); */ reg32 = (pci_read_config32(PCI_DEV(0xa, 0, 0), 0x8) >> 8); printk(BIOS_DEBUG, "PCIe device class: %06x\n", reg32); @@ -662,84 +663,84 @@ pci_write_config32(PCI_DEV(0, 0x0, 0), DEVEN, reg32); /* Set VGA enable bit in PCIe bridge */ - reg16 = pci_read_config16(PCI_DEV(0, 0x1, 0), PCI_BRIDGE_CONTROL); + reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL); reg16 |= PCI_BRIDGE_CTL_VGA; - pci_write_config16(PCI_DEV(0, 0x1, 0), PCI_BRIDGE_CONTROL, reg16); + pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16); } /* Enable GPEs */ - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), PEG_LC); + reg32 = pci_read_config32(p2peg, PEG_LC); reg32 |= (1 << 2) | (1 << 1) | (1 << 0); /* PMEGPE, HPGPE, GENGPE */ - pci_write_config32(PCI_DEV(0, 0x01, 0), PEG_LC, reg32); + pci_write_config32(p2peg, PEG_LC, reg32); /* Virtual Channel Configuration: Only VC0 on PCIe x16 */ - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), VC0RCTL); + reg32 = pci_read_config32(p2peg, VC0RCTL); reg32 &= 0xffffff01; - pci_write_config32(PCI_DEV(0, 0x01, 0), VC0RCTL, reg32); + pci_write_config32(p2peg, VC0RCTL, reg32); /* Extended VC count */ - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), PVCCAP1); + reg32 = pci_read_config32(p2peg, PVCCAP1); reg32 &= ~(7 << 0); - pci_write_config32(PCI_DEV(0, 0x01, 0), PVCCAP1, reg32); + pci_write_config32(p2peg, PVCCAP1, reg32); /* Active State Power Management ASPM */ /* TODO */ /* Clear error bits */ - pci_write_config16(PCI_DEV(0, 0x01, 0), PCISTS1, 0xffff); - pci_write_config16(PCI_DEV(0, 0x01, 0), SSTS1, 0xffff); - pci_write_config16(PCI_DEV(0, 0x01, 0), DSTS, 0xffff); - pci_write_config32(PCI_DEV(0, 0x01, 0), UESTS, 0xffffffff); - pci_write_config32(PCI_DEV(0, 0x01, 0), CESTS, 0xffffffff); - pci_write_config32(PCI_DEV(0, 0x01, 0), 0x1f0, 0xffffffff); - pci_write_config32(PCI_DEV(0, 0x01, 0), 0x228, 0xffffffff); + pci_write_config16(p2peg, PCISTS1, 0xffff); + pci_write_config16(p2peg, SSTS1, 0xffff); + pci_write_config16(p2peg, DSTS, 0xffff); + pci_write_config32(p2peg, UESTS, 0xffffffff); + pci_write_config32(p2peg, CESTS, 0xffffffff); + pci_write_config32(p2peg, 0x1f0, 0xffffffff); + pci_write_config32(p2peg, 0x228, 0xffffffff); /* Program R/WO registers */ - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x308); - pci_write_config32(PCI_DEV(0, 0x01, 0), 0x308, reg32); + reg32 = pci_read_config32(p2peg, 0x308); + pci_write_config32(p2peg, 0x308, reg32); - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x314); - pci_write_config32(PCI_DEV(0, 0x01, 0), 0x314, reg32); + reg32 = pci_read_config32(p2peg, 0x314); + pci_write_config32(p2peg, 0x314, reg32); - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x324); - pci_write_config32(PCI_DEV(0, 0x01, 0), 0x324, reg32); + reg32 = pci_read_config32(p2peg, 0x324); + pci_write_config32(p2peg, 0x324, reg32); - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x328); - pci_write_config32(PCI_DEV(0, 0x01, 0), 0x328, reg32); + reg32 = pci_read_config32(p2peg, 0x328); + pci_write_config32(p2peg, 0x328, reg32); /* Additional PCIe graphics setup */ - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xf0); + reg32 = pci_read_config32(p2peg, 0xf0); reg32 |= (3 << 26); - pci_write_config32(PCI_DEV(0, 0x01, 0), 0xf0, reg32); + pci_write_config32(p2peg, 0xf0, reg32); - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xf0); + reg32 = pci_read_config32(p2peg, 0xf0); reg32 |= (3 << 24); - pci_write_config32(PCI_DEV(0, 0x01, 0), 0xf0, reg32); + pci_write_config32(p2peg, 0xf0, reg32); - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xf0); + reg32 = pci_read_config32(p2peg, 0xf0); reg32 |= (1 << 5); - pci_write_config32(PCI_DEV(0, 0x01, 0), 0xf0, reg32); + pci_write_config32(p2peg, 0xf0, reg32); - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x200); + reg32 = pci_read_config32(p2peg, 0x200); reg32 &= ~(3 << 26); reg32 |= (2 << 26); - pci_write_config32(PCI_DEV(0, 0x01, 0), 0x200, reg32); + pci_write_config32(p2peg, 0x200, reg32); - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xe80); + reg32 = pci_read_config32(p2peg, 0xe80); if (i945_silicon_revision() >= 2) reg32 |= (1 << 12); else reg32 &= ~(1 << 12); - pci_write_config32(PCI_DEV(0, 0x01, 0), 0xe80, reg32); + pci_write_config32(p2peg, 0xe80, reg32); - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xeb4); + reg32 = pci_read_config32(p2peg, 0xeb4); reg32 &= ~(1 << 31); - pci_write_config32(PCI_DEV(0, 0x01, 0), 0xeb4, reg32); + pci_write_config32(p2peg, 0xeb4, reg32); - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xfc); + reg32 = pci_read_config32(p2peg, 0xfc); reg32 |= (1 << 31); - pci_write_config32(PCI_DEV(0, 0x01, 0), 0xfc, reg32); + pci_write_config32(p2peg, 0xfc, reg32); if (i945_silicon_revision() >= 3) { static const u32 reglist[] = { @@ -750,21 +751,21 @@ int i; for (i = 0; i < ARRAY_SIZE(reglist); i++) { - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), reglist[i]); + reg32 = pci_read_config32(p2peg, reglist[i]); reg32 &= 0x0fffffff; reg32 |= (2 << 28); - pci_write_config32(PCI_DEV(0, 0x01, 0), reglist[i], reg32); + pci_write_config32(p2peg, reglist[i], reg32); } } if (i945_silicon_revision() <= 2) { /* Set voltage specific parameters */ - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xe80); + reg32 = pci_read_config32(p2peg, 0xe80); reg32 &= (0xf << 4); /* Default case 1.05V */ if ((MCHBAR32(DFT_STRAP1) & (1 << 20)) == 0) { /* 1.50V */ reg32 |= (7 << 4); } - pci_write_config32(PCI_DEV(0, 0x01, 0), 0xe80, reg32); + pci_write_config32(p2peg, 0xe80, reg32); } return; @@ -775,21 +776,21 @@ MCHBAR16(UPMC1) |= (1 << 5) | (1 << 0); - reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL); + reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL); reg16 |= PCI_BRIDGE_CTL_BUS_RESET; - pci_write_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL, reg16); + pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16); - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x224); + reg32 = pci_read_config32(p2peg, 0x224); reg32 |= (1 << 8); - pci_write_config32(PCI_DEV(0, 0x01, 0), 0x224, reg32); + pci_write_config32(p2peg, 0x224, reg32); - reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL); + reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL); reg16 &= ~PCI_BRIDGE_CTL_BUS_RESET; - pci_write_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL, reg16); + pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16); printk(BIOS_DEBUG, "Wait for link to enter detect state... "); timeout = 0x7fffff; - for (reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS); + for (reg32 = pci_read_config32(p2peg, PEGSTS); (reg32 & 0x000f0000) && --timeout;) ; if (!timeout) @@ -806,6 +807,7 @@ static void i945_setup_root_complex_topology(void) { u32 reg32; + pci_devfn_t p2peg = PCI_DEV(0, 0x01, 0); printk(BIOS_DEBUG, "Setting up Root Complex Topology\n"); /* Egress Port Root Topology */ @@ -840,10 +842,10 @@ /* PCI Express x16 Port Root Topology */ if (pci_read_config8(PCI_DEV(0, 0x00, 0), DEVEN) & DEVEN_D1F0) { - pci_write_config32(PCI_DEV(0, 0x01, 0), LE1A, DEFAULT_EPBAR); - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), LE1D); + pci_write_config32(p2peg, LE1A, DEFAULT_EPBAR); + reg32 = pci_read_config32(p2peg, LE1D); reg32 |= (1 << 0); - pci_write_config32(PCI_DEV(0, 0x01, 0), LE1D, reg32); + pci_write_config32(p2peg, LE1D, reg32); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/35675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e9dd06376c1076be4a4c41ff87dfd3cf820d7bc Gerrit-Change-Number: 35675 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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coreboot-gerrit October 2019