coreboot-gerrit October 2019

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Change in coreboot[master]: sb/intel/i82801gx: Use symbolic name for register, code rework
by Arthur Heymans (Code Review) 02 Oct '19

02 Oct '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35737 ) Change subject: sb/intel/i82801gx: Use symbolic name for register, code rework ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/35737 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33509befe86ff6e333c559c87a0f45886d737df9 Gerrit-Change-Number: 35737 Gerrit-PatchSet: 4 Gerrit-Owner: Petr Cvek <petrcvekcz(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Petr Cvek <petrcvekcz(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 02 Oct 2019 08:20:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: sb/intel/i82801gx: Use symbolic name for register, code rework
by Petr Cvek (Code Review) 02 Oct '19

02 Oct '19

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Change in coreboot[master]: sb/intel/i82801gx: Use symbolic name for register, code rework
by Petr Cvek (Code Review) 02 Oct '19

02 Oct '19

Hello Patrick Rudolph, HAOUAS Elyes, Arthur Heymans, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35737 to look at the new patch set (#4). Change subject: sb/intel/i82801gx: Use symbolic name for register, code rework ...................................................................... sb/intel/i82801gx: Use symbolic name for register, code rework An original code had a wrong register address 0x27 for AHCI BAR. The value was aligned incidentally by the code specific of the pci_read_config32 function to the correct address 0x24. All 0x24 values in sata.c were changed to the symbolic name PCI_BASE_ADDRESS_5 and the code was optimized. An equivalent code was tested on a real hardware. Signed-off-by: Petr Cvek <petrcvekcz(a)gmail.com> Change-Id: I33509befe86ff6e333c559c87a0f45886d737df9 --- M src/southbridge/intel/i82801gx/sata.c 1 file changed, 7 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/35737/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/35737 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33509befe86ff6e333c559c87a0f45886d737df9 Gerrit-Change-Number: 35737 Gerrit-PatchSet: 4 Gerrit-Owner: Petr Cvek <petrcvekcz(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Petr Cvek <petrcvekcz(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: sb/intel/i82801gx: Use symbolic name for register, code rework
by Arthur Heymans (Code Review) 02 Oct '19

02 Oct '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35737 ) Change subject: sb/intel/i82801gx: Use symbolic name for register, code rework ...................................................................... Patch Set 3: Code-Review+2 (1 comment) https://review.coreboot.org/c/coreboot/+/35737/3/src/southbridge/intel/i828… File src/southbridge/intel/i82801gx/sata.c: https://review.coreboot.org/c/coreboot/+/35737/3/src/southbridge/intel/i828… PS3, Line 159: 0xc nit: add comment that this is GHC_PI. -- To view, visit https://review.coreboot.org/c/coreboot/+/35737 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33509befe86ff6e333c559c87a0f45886d737df9 Gerrit-Change-Number: 35737 Gerrit-PatchSet: 3 Gerrit-Owner: Petr Cvek <petrcvekcz(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Petr Cvek <petrcvekcz(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 02 Oct 2019 07:57:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in libgfxinit[master]: gma: Automatically update CDClk and dot clocks
by Nico Huber (Code Review) 02 Oct '19

02 Oct '19

Hello Arthur Heymans, Matt DeVillier, Thomas Heijligen, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/libgfxinit/+/35719 to look at the new patch set (#3). Change subject: gma: Automatically update CDClk and dot clocks ...................................................................... gma: Automatically update CDClk and dot clocks Dot clocks should be limited, depending on CDClk. This comes with a caveat: if a display only works at a specific refresh rate, we will likely fail without knowing. It seems to be better, though, to try at least. We can implement a config switch controlling this beha- viour, later, if needed. If we can raise / lower CDClk with a given set of dot clocks, we have to disable all pipes first, then switch CDClk, and finally enable all pipes with their new configuration. Calling Update_Outputs() with all pipe configs disabled may disable the CDClk. So we have to ensure it is enabled when trying to probe for displays. Change-Id: I375f2bd37c921cd5ed4b0094247df5a34a087188 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M common/hw-gfx-gma-display_probing.adb M common/hw-gfx-gma.adb 2 files changed, 16 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/19/35719/3 -- To view, visit https://review.coreboot.org/c/libgfxinit/+/35719 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I375f2bd37c921cd5ed4b0094247df5a34a087188 Gerrit-Change-Number: 35719 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in libgfxinit[master]: gma bxt: Implement CDClk switching
by Nico Huber (Code Review) 02 Oct '19

02 Oct '19

Hello Arthur Heymans, Matt DeVillier, Thomas Heijligen, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/libgfxinit/+/35718 to look at the new patch set (#3). Change subject: gma bxt: Implement CDClk switching ...................................................................... gma bxt: Implement CDClk switching Again, very similar procedure to the previous generations. The CDClk is limited to 624MHz (no fuses). Dot clocks can run at the full CDClk speed. If all pipes are disabled, we set CDClk to its reference rate. In this state, the display engine is not operational and neither are the DP Aux ports. So we have to implement Enable_CDClk() to allow display probing without any pipe enabled. Change-Id: I7bccbce0625a9893e2dd5c06fd1475a44987989d Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M common/broxton/hw-gfx-gma-power_and_clocks.adb M common/broxton/hw-gfx-gma-power_and_clocks.ads 2 files changed, 62 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/18/35718/3 -- To view, visit https://review.coreboot.org/c/libgfxinit/+/35718 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I7bccbce0625a9893e2dd5c06fd1475a44987989d Gerrit-Change-Number: 35718 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Makefile: Create the build directory before bootblock.bin
by Martin Roth (Code Review) 02 Oct '19

02 Oct '19

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35531 ) Change subject: Makefile: Create the build directory before bootblock.bin ...................................................................... Makefile: Create the build directory before bootblock.bin This was causing a failure when building platforms with no bootblock when building with make -jXX Change-Id: Ic4cd4fe8ac82bd1e9ce114dbd53763538d125af3 Signed-off-by: Martin Roth <martinroth(a)chromium.org> --- M Makefile.inc 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/35531/1 diff --git a/Makefile.inc b/Makefile.inc index 3c3088d..cf8e470 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -504,7 +504,7 @@ @printf " GEN build.h\n" mv $< $@ -build-dirs: +build-dirs $(objcbfs) $(objgenerated): mkdir -p $(objcbfs) $(objgenerated) ####################################################################### @@ -706,7 +706,7 @@ $(OBJCOPY_bootblock) -O binary $< $@ ifneq ($(CONFIG_HAVE_BOOTBLOCK),y) -$(objcbfs)/bootblock.bin: +$(objcbfs)/bootblock.bin: $(objcbfs) dd if=/dev/zero of=$@ bs=64 count=1 endif -- To view, visit https://review.coreboot.org/c/coreboot/+/35531 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4cd4fe8ac82bd1e9ce114dbd53763538d125af3 Gerrit-Change-Number: 35531 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/i82801gx: Use symbolic name for register, code rework
by Petr Cvek (Code Review) 01 Oct '19

01 Oct '19

Petr Cvek has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35737 ) Change subject: sb/intel/i82801gx: Use symbolic name for register, code rework ...................................................................... Patch Set 3: (5 comments) I've had to fix missing parameters for res2mmio in the new version of the patch. https://review.coreboot.org/c/coreboot/+/35737/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/35737/2//COMMIT_MSG@7 PS2, Line 7: Correctly align register offset > Ack Done https://review.coreboot.org/c/coreboot/+/35737/2//COMMIT_MSG@10 PS2, Line 10: > Ack Done https://review.coreboot.org/c/coreboot/+/35737/2/src/southbridge/intel/i828… File src/southbridge/intel/i82801gx/sata.c: https://review.coreboot.org/c/coreboot/+/35737/2/src/southbridge/intel/i828… PS2, Line 97: u32 > Ack Done https://review.coreboot.org/c/coreboot/+/35737/2/src/southbridge/intel/i828… PS2, Line 158: ahci_ > Ack Done https://review.coreboot.org/c/coreboot/+/35737/2/src/southbridge/intel/i828… PS2, Line 158: 0x24 > > if a generic name PCI_BASE_ADDRESS_5 is OK, I'm gonna change the rest of reg 0x24 references in th […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/35737 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33509befe86ff6e333c559c87a0f45886d737df9 Gerrit-Change-Number: 35737 Gerrit-PatchSet: 3 Gerrit-Owner: Petr Cvek <petrcvekcz(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Petr Cvek <petrcvekcz(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 01 Oct 2019 20:58:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Petr Cvek <petrcvekcz(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: sb/intel/i82801gx: Use symbolic name for register, code rework
by Petr Cvek (Code Review) 01 Oct '19

01 Oct '19

Hello Patrick Rudolph, HAOUAS Elyes, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35737 to look at the new patch set (#3). Change subject: sb/intel/i82801gx: Use symbolic name for register, code rework ...................................................................... sb/intel/i82801gx: Use symbolic name for register, code rework An original code had a wrong register address 0x27 for AHCI BAR. The value was aligned incidentally by the code specific of the pci_read_config32 function to the correct address 0x24. All 0x24 values in sata.c were changed to the symbolic name PCI_BASE_ADDRESS_5 and the code was optimized. An equivalent code was tested on a real hardware. Signed-off-by: Petr Cvek <petrcvekcz(a)gmail.com> Change-Id: I33509befe86ff6e333c559c87a0f45886d737df9 --- M src/southbridge/intel/i82801gx/sata.c 1 file changed, 6 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/35737/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/35737 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33509befe86ff6e333c559c87a0f45886d737df9 Gerrit-Change-Number: 35737 Gerrit-PatchSet: 3 Gerrit-Owner: Petr Cvek <petrcvekcz(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Petr Cvek <petrcvekcz(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: HACK trogdor: SoC makefile BLOB support HACK
by mturney mturney (Code Review) 01 Oct '19

01 Oct '19

Hello ashk(a)codeaurora.org, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35508 to look at the new patch set (#6). Change subject: HACK trogdor: SoC makefile BLOB support HACK ...................................................................... HACK trogdor: SoC makefile BLOB support HACK Change-Id: I85a20ef31ec91c6f22221d16fd4c3097c5cb97d1 Signed-off-by: Ashwin Kumar <ashk(a)codeaurora.org> --- M src/soc/qualcomm/sc7180/Makefile.inc 1 file changed, 114 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/35508/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/35508 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85a20ef31ec91c6f22221d16fd4c3097c5cb97d1 Gerrit-Change-Number: 35508 Gerrit-PatchSet: 6 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: ashk(a)codeaurora.org Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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coreboot-gerrit October 2019