coreboot-gerrit October 2019

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Change in coreboot[master]: libpayload: Add fmap_cache to sysinfo_t
by Furquan Shaikh (Code Review) 02 Oct '19

02 Oct '19

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35640 ) Change subject: libpayload: Add fmap_cache to sysinfo_t ...................................................................... libpayload: Add fmap_cache to sysinfo_t Now that FMAP is cached in CBMEM and its pointer is added to coreboot table for quick lookup, this change adds a new member "fmap_cache" to sysinfo_t that can be used by payloads to get to FMAP cache. BUG=b:141723751 Change-Id: If894c20c2de89a9d8564561bc7780c86f3f4135a Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M payloads/libpayload/include/coreboot_tables.h M payloads/libpayload/include/sysinfo.h M payloads/libpayload/libc/coreboot.c 3 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/35640/1 diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index bf2cf02..c24d6ac 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -78,6 +78,7 @@ CB_TAG_VBOOT_WORKBUF = 0x0034, CB_TAG_MMC_INFO = 0x0035, CB_TAG_TCPA_LOG = 0x0036, + CB_TAG_FMAP = 0x0037, CB_TAG_CMOS_OPTION_TABLE = 0x00c8, CB_TAG_OPTION = 0x00c9, CB_TAG_OPTION_ENUM = 0x00ca, diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index 50f0e39..c05be7c 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -128,6 +128,9 @@ uint32_t mtc_size; void *chromeos_vpd; int mmc_early_wake_status; + + /* Pointer to FMAP cache in CBMEM */ + void *fmap_cache; }; extern struct sysinfo_t lib_sysinfo; diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c index 03778b6..e14b144 100644 --- a/payloads/libpayload/libc/coreboot.c +++ b/payloads/libpayload/libc/coreboot.c @@ -239,6 +239,12 @@ info->chromeos_vpd = phys_to_virt(cbmem->cbmem_tab); } +static void cb_parse_fmap_cache(void *ptr, struct sysinfo_t *info) +{ + struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr; + info->fmap_cache = phys_to_virt(cbmem->cbmem_tab); +} + #if CONFIG(LP_TIMER_RDTSC) static void cb_parse_tsc_info(void *ptr, struct sysinfo_t *info) { @@ -412,6 +418,9 @@ case CB_TAG_VPD: cb_parse_vpd(ptr, info); break; + case CB_TAG_FMAP: + cb_parse_fmap_cache(ptr, info); + break; default: cb_parse_arch_specific(rec, info); break; -- To view, visit https://review.coreboot.org/c/coreboot/+/35640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If894c20c2de89a9d8564561bc7780c86f3f4135a Gerrit-Change-Number: 35640 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: binaryPI: implement C_ENVIRONMENT_BOOTBLOCK
by Michał Żygowski (Code Review) 02 Oct '19

02 Oct '19

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35754 ) Change subject: binaryPI: implement C_ENVIRONMENT_BOOTBLOCK ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/35754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If276b867bc9e6bbb4c8f9e44815d4f4b2f0dddac Gerrit-Change-Number: 35754 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Wed, 02 Oct 2019 11:43:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/drallion: Disable GBE in firmware for drallion variants
by Thejaswani Putta (Code Review) 02 Oct '19

02 Oct '19

Hello Thejaswani Putta, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/35509 to review the following change. Change subject: mb/google/drallion: Disable GBE in firmware for drallion variants ...................................................................... mb/google/drallion: Disable GBE in firmware for drallion variants BUG: None TEST: Build and boot, check if 1f.6 is off on drallion variants Signed-off-by: Thejaswani Putta <thejaswani.putta(a)intel.corp-partner.google.com> Change-Id: I4e74b259ce8f5f70833dce94692dcbe33e8504db --- M src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/35509/1 diff --git a/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb b/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb index f2367ff..8cb1aa3 100644 --- a/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb +++ b/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb @@ -417,6 +417,6 @@ device pci 1f.3 on end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI - device pci 1f.6 on end # GbE + device pci 1f.6 off end # GbE end end -- To view, visit https://review.coreboot.org/c/coreboot/+/35509 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e74b259ce8f5f70833dce94692dcbe33e8504db Gerrit-Change-Number: 35509 Gerrit-PatchSet: 1 Gerrit-Owner: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

5 10

Change in coreboot[master]: intel/baytrail: Replace config_of(dev) with config_of_soc()
by Kyösti Mälkki (Code Review) 02 Oct '19

02 Oct '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35670 ) Change subject: intel/baytrail: Replace config_of(dev) with config_of_soc() ...................................................................... intel/baytrail: Replace config_of(dev) with config_of_soc() The function does not otherwise need dev. Change-Id: I75d3283b537151258ed48f7e4e0991dff53a803c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/baytrail/romstage/pmc.c 1 file changed, 1 insertion(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/35670/1 diff --git a/src/soc/intel/baytrail/romstage/pmc.c b/src/soc/intel/baytrail/romstage/pmc.c index 882edf0..2eb3846 100644 --- a/src/soc/intel/baytrail/romstage/pmc.c +++ b/src/soc/intel/baytrail/romstage/pmc.c @@ -41,13 +41,11 @@ { uint32_t reg; uint8_t rid; - const struct device *dev; const struct soc_intel_baytrail_config *cfg = NULL; rid = pci_read_config8(IOSF_PCI_DEV, REVID); - dev = pcidev_on_root(SOC_DEV, SOC_FUNC); - cfg = config_of(dev); + cfg = config_of_soc(); reg = iosf_punit_read(SB_BIOS_CONFIG); /* Write bits 17:16 of SB_BIOS_CONFIG in the PUNIT. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35670 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75d3283b537151258ed48f7e4e0991dff53a803c Gerrit-Change-Number: 35670 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: coreinfo/coreinfo.c: Support both lower and upper case alphabets
by Name of user not set (Code Review) 02 Oct '19

02 Oct '19

Name of user not set #1002476 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35538 ) Change subject: coreinfo/coreinfo.c: Support both lower and upper case alphabets ...................................................................... coreinfo/coreinfo.c: Support both lower and upper case alphabets Modify handle_category_key to handle both upper and lower case alphabets in the coreinfo payload. Change-Id: I3ccbf69e90ba7824ad6ec85d2ca59aa8f40b3006 Signed-off-by: Himanshu Sahdev <himanshusah(a)hcl.com> --- M payloads/coreinfo/coreinfo.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/35538/1 diff --git a/payloads/coreinfo/coreinfo.c b/payloads/coreinfo/coreinfo.c index b731abf..e6b7f2e 100644 --- a/payloads/coreinfo/coreinfo.c +++ b/payloads/coreinfo/coreinfo.c @@ -198,7 +198,9 @@ static void handle_category_key(struct coreinfo_cat *cat, int key) { - if (key >= 'a' && key <= 'z') { + if ((key >= 'a' && key <= 'z') || (key >= 'A' && key <= 'Z')) { + if (key >= 'A' && key <= 'Z') + key = key + 32; int index = key - 'a'; if (index < cat->count) { cat->cur = index; -- To view, visit https://review.coreboot.org/c/coreboot/+/35538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ccbf69e90ba7824ad6ec85d2ca59aa8f40b3006 Gerrit-Change-Number: 35538 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002476 Gerrit-MessageType: newchange

5 8

Change in coreboot[master]: mb/google/drallion: dynamic disable memory channel
by EricR Lai (Code Review) 02 Oct '19

02 Oct '19

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35241 ) Change subject: mb/google/drallion: dynamic disable memory channel ...................................................................... mb/google/drallion: dynamic disable memory channel Disable memory channel by HW strap pin. Using for factory debug. Keep this until the real board come out. BUG=b:139773082 BRANCH=N/A TEST=N/A Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ic5f53f0ba3bd432fbcb7513d2a8aa49d42f7a23e --- M src/mainboard/google/drallion/romstage.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35241/1 diff --git a/src/mainboard/google/drallion/romstage.c b/src/mainboard/google/drallion/romstage.c index 20eee7f..6e62a1e 100644 --- a/src/mainboard/google/drallion/romstage.c +++ b/src/mainboard/google/drallion/romstage.c @@ -16,6 +16,8 @@ #include <ec/google/wilco/romstage.h> #include <soc/cnl_memcfg_init.h> #include <soc/romstage.h> +#include <gpio.h> +#include <variant/gpio.h> static const struct cnl_mb_cfg memcfg = { /* Access memory info through SMBUS. */ @@ -59,5 +61,9 @@ { wilco_ec_romstage_init(); + /* Disable memory channel by HW strap pin */ + memupd->FspmConfig.DisableDimmChannel0 = gpio_get(GPP_F1)? 0 : 3; + memupd->FspmConfig.DisableDimmChannel1 = gpio_get(GPP_F2)? 0 : 3; + cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); } -- To view, visit https://review.coreboot.org/c/coreboot/+/35241 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5f53f0ba3bd432fbcb7513d2a8aa49d42f7a23e Gerrit-Change-Number: 35241 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

8 37

Change in coreboot[master]: mediatek/mt8183: Rename fields of struct sdram_params
by Yu-Ping Wu (Code Review) 02 Oct '19

02 Oct '19

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35738 ) Change subject: mediatek/mt8183: Rename fields of struct sdram_params ...................................................................... mediatek/mt8183: Rename fields of struct sdram_params Two fields of struct sdram_params are renamed for future CL of DRAM full calibration. Field 'impedance' is also removed. Change-Id: I2f9673fd5ea2e62ee971f0d81bdd12aaf565e31c Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c M src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c M src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c M src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c M src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c M src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c M src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c M src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/include/soc/emi.h 10 files changed, 20 insertions(+), 53 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/35738/1 diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c index da6c7d2..fab1240 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c @@ -16,19 +16,15 @@ #include <soc/emi.h> struct sdram_params params = { - .impedance = { - [ODT_OFF] = {0x7, 0x6, 0x0, 0xF}, - [ODT_ON] = {0x9, 0x9, 0x0, 0xF} - }, .wr_level = { [CHANNEL_A] = { {0x22, 0x1b}, {0x22, 0x19} }, [CHANNEL_B] = { {0x24, 0x20}, {0x25, 0x20} } }, - .cbt_cs = { + .cbt_cs_dly = { [CHANNEL_A] = {0x0, 0x0}, [CHANNEL_B] = {0x0, 0x0} }, - .cbt_mr12 = { + .cbt_final_vref = { [CHANNEL_A] = {0x52, 0x52}, [CHANNEL_B] = {0x52, 0x52} }, diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c index 8d855ff..d3c1496 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c @@ -16,19 +16,15 @@ #include <soc/emi.h> struct sdram_params params = { - .impedance = { - [ODT_OFF] = {0x9, 0x7, 0x0, 0xF}, - [ODT_ON] = {0xB, 0x9, 0x0, 0xE} - }, .wr_level = { [CHANNEL_A] = { {0x22, 0x1C}, {0x23, 0x1D} }, [CHANNEL_B] = { {0x26, 0x23}, {0x26, 0x23} } }, - .cbt_cs = { + .cbt_cs_dly = { [CHANNEL_A] = {0x6, 0x5}, [CHANNEL_B] = {0x6, 0x6} }, - .cbt_mr12 = { + .cbt_final_vref = { [CHANNEL_A] = {0x56, 0x58}, [CHANNEL_B] = {0x58, 0x56} }, diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c index 1e0c362..c21cd12 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c @@ -16,19 +16,15 @@ #include <soc/emi.h> struct sdram_params params = { - .impedance = { - [ODT_OFF] = {0x9, 0x7, 0x0, 0xF}, - [ODT_ON] = {0xA, 0x9, 0x0, 0xE} - }, .wr_level = { [CHANNEL_A] = { {0x21, 0x21}, {0x20, 0x20} }, [CHANNEL_B] = { {0x1E, 0x1F}, {0x1D, 0x1E} } }, - .cbt_cs = { + .cbt_cs_dly = { [CHANNEL_A] = {0x1, 0x1}, [CHANNEL_B] = {0x2, 0x2} }, - .cbt_mr12 = { + .cbt_final_vref = { [CHANNEL_A] = {0x56, 0x56}, [CHANNEL_B] = {0x58, 0x5C} }, diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c index 12acc61..4349845 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c @@ -16,19 +16,15 @@ #include <soc/emi.h> struct sdram_params params = { - .impedance = { - [ODT_OFF] = {0x7, 0x6, 0x0, 0xF}, - [ODT_ON] = {0x8, 0x9, 0x0, 0xD} - }, .wr_level = { [CHANNEL_A] = { {0x22, 0x21}, {0x20, 0x21} }, [CHANNEL_B] = { {0x23, 0x27}, {0x23, 0x27} } }, - .cbt_cs = { + .cbt_cs_dly = { [CHANNEL_A] = {0x0, 0x0}, [CHANNEL_B] = {0x6, 0x6} }, - .cbt_mr12 = { + .cbt_final_vref = { [CHANNEL_A] = {0x56, 0x5A}, [CHANNEL_B] = {0x58, 0x58} }, diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c index 8cc0d3d..cab57ce 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c @@ -16,19 +16,15 @@ #include <soc/emi.h> struct sdram_params params = { - .impedance = { - [ODT_OFF] = {0x8, 0x7, 0x0, 0xF}, - [ODT_ON] = {0x9, 0x9, 0x0, 0xD} - }, .wr_level = { [CHANNEL_A] = { {0x21, 0x24}, {0x22, 0x24} }, [CHANNEL_B] = { {0x24, 0x28}, {0x22, 0x27} } }, - .cbt_cs = { + .cbt_cs_dly = { [CHANNEL_A] = {0xC, 0xC}, [CHANNEL_B] = {0xB, 0xB} }, - .cbt_mr12 = { + .cbt_final_vref = { [CHANNEL_A] = {0x58, 0x58}, [CHANNEL_B] = {0x56, 0x56} }, diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c index 512023b..2810ef5 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c @@ -16,19 +16,15 @@ #include <soc/emi.h> struct sdram_params params = { - .impedance = { - [ODT_OFF] = {0x9, 0x7, 0x0, 0xF}, - [ODT_ON] = {0xA, 0x9, 0x0, 0xE} - }, .wr_level = { [CHANNEL_A] = { {0x21, 0x21}, {0x20, 0x20} }, [CHANNEL_B] = { {0x21, 0x28}, {0x21, 0x29} } }, - .cbt_cs = { + .cbt_cs_dly = { [CHANNEL_A] = {0x2, 0x2}, [CHANNEL_B] = {0x2, 0x2} }, - .cbt_mr12 = { + .cbt_final_vref = { [CHANNEL_A] = {0x5E, 0x5E}, [CHANNEL_B] = {0x5E, 0x5C} }, diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c index 0fb5aba..329cc76 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c @@ -16,19 +16,15 @@ #include <soc/emi.h> struct sdram_params params = { - .impedance = { - [ODT_OFF] = {0x5, 0x7, 0x0, 0xF}, - [ODT_ON] = {0x6, 0x9, 0x0, 0xF} - }, .wr_level = { [CHANNEL_A] = { {0x1F, 0x19}, {0x20, 0x1A} }, [CHANNEL_B] = { {0x22, 0x1E}, {0x22, 0x1E} } }, - .cbt_cs = { + .cbt_cs_dly = { [CHANNEL_A] = {0x5, 0x4}, [CHANNEL_B] = {0x8, 0x8} }, - .cbt_mr12 = { + .cbt_final_vref = { [CHANNEL_A] = {0x56, 0x56}, [CHANNEL_B] = {0x56, 0x56} }, diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c index 61060d6..ccb591e 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c @@ -16,19 +16,15 @@ #include <soc/emi.h> struct sdram_params params = { - .impedance = { - [ODT_OFF] = {0x8, 0x7, 0x0, 0xF}, - [ODT_ON] = {0x9, 0x9, 0x0, 0xE} - }, .wr_level = { [CHANNEL_A] = { {0x1F, 0x1C}, {0x1C, 0x1B} }, [CHANNEL_B] = { {0x27, 0x28}, {0x23, 0x28} } }, - .cbt_cs = { + .cbt_cs_dly = { [CHANNEL_A] = {0x3, 0x3}, [CHANNEL_B] = {0x4, 0x6} }, - .cbt_mr12 = { + .cbt_final_vref = { [CHANNEL_A] = {0x5C, 0x5A}, [CHANNEL_B] = {0x5C, 0x5A} }, diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index fcc3b14..f8b1f09 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -252,8 +252,8 @@ { u32 cbt_cs, mr12_value; - cbt_cs = params->cbt_cs[chn][rank]; - mr12_value = params->cbt_mr12[chn][rank]; + cbt_cs = params->cbt_cs_dly[chn][rank]; + mr12_value = params->cbt_final_vref[chn][rank]; /* CBT adjust cs */ clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].ca_cmd[9], diff --git a/src/soc/mediatek/mt8183/include/soc/emi.h b/src/soc/mediatek/mt8183/include/soc/emi.h index 264d918..15889ee 100644 --- a/src/soc/mediatek/mt8183/include/soc/emi.h +++ b/src/soc/mediatek/mt8183/include/soc/emi.h @@ -21,10 +21,9 @@ #include <soc/dramc_common_mt8183.h> struct sdram_params { - u32 impedance[2][4]; u8 wr_level[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]; - u8 cbt_cs[CHANNEL_MAX][RANK_MAX]; - u8 cbt_mr12[CHANNEL_MAX][RANK_MAX]; + u8 cbt_cs_dly[CHANNEL_MAX][RANK_MAX]; + u8 cbt_final_vref[CHANNEL_MAX][RANK_MAX]; u32 emi_cona_val; u32 emi_conh_val; u32 emi_conf_val; -- To view, visit https://review.coreboot.org/c/coreboot/+/35738 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f9673fd5ea2e62ee971f0d81bdd12aaf565e31c Gerrit-Change-Number: 35738 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

3 10

Change in coreboot[master]: sb/intel/common/smihandler: Hook up smmstore
by Patrick Georgi (Code Review) 02 Oct '19

02 Oct '19

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/30012 ) Change subject: sb/intel/common/smihandler: Hook up smmstore ...................................................................... sb/intel/common/smihandler: Hook up smmstore TESTED on Asus P5QC. Change-Id: I20b87f3dcb898656ad31478820dd5153e4053cb2 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30012 Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/southbridge/intel/common/Kconfig M src/southbridge/intel/common/smihandler.c 2 files changed, 26 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index c3bd90d..dfd8975 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -20,6 +20,7 @@ config SOUTHBRIDGE_INTEL_COMMON_SPI def_bool n select SPI_FLASH + select BOOT_DEVICE_SUPPORTS_WRITES config SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN def_bool n diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index daa0959..d61238c 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -27,6 +27,7 @@ #include <halt.h> #include <pc80/mc146818rtc.h> #include <southbridge/intel/common/pmbase.h> +#include <smmstore.h> #include "pmutil.h" @@ -268,6 +269,26 @@ } #endif +static void southbridge_smi_store(void) +{ + u8 sub_command, ret; + em64t101_smm_state_save_area_t *io_smi = + smi_apmc_find_state_save(APM_CNT_SMMSTORE); + uint32_t reg_ebx; + + if (!io_smi) + return; + /* Command and return value in EAX */ + sub_command = (io_smi->rax >> 8) & 0xff; + + /* Parameter buffer in EBX */ + reg_ebx = io_smi->rbx; + + /* drivers/smmstore/smi.c */ + ret = smmstore_exec(sub_command, (uintptr_t *)reg_ebx); + io_smi->rax = ret; +} + static int mainboard_finalized = 0; static void southbridge_smi_apmc(void) @@ -322,6 +343,10 @@ southbridge_smi_gsmi(); break; #endif + case APM_CNT_SMMSTORE: + if (CONFIG(SMMSTORE)) + southbridge_smi_store(); + break; } mainboard_smi_apmc(reg8); -- To view, visit https://review.coreboot.org/c/coreboot/+/30012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20b87f3dcb898656ad31478820dd5153e4053cb2 Gerrit-Change-Number: 30012 Gerrit-PatchSet: 18 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matthew Garrett <mjg59(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: merged

1 0

Change in libgfxinit[master]: gma: Automatically update CDClk and dot clocks
by Nico Huber (Code Review) 02 Oct '19

02 Oct '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/35719 ) Change subject: gma: Automatically update CDClk and dot clocks ...................................................................... Patch Set 3: Verified+1 -- To view, visit https://review.coreboot.org/c/libgfxinit/+/35719 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I375f2bd37c921cd5ed4b0094247df5a34a087188 Gerrit-Change-Number: 35719 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 02 Oct 2019 08:23:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in libgfxinit[master]: gma bxt: Implement CDClk switching
by Nico Huber (Code Review) 02 Oct '19

02 Oct '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/35718 ) Change subject: gma bxt: Implement CDClk switching ...................................................................... Patch Set 3: Verified+1 -- To view, visit https://review.coreboot.org/c/libgfxinit/+/35718 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I7bccbce0625a9893e2dd5c06fd1475a44987989d Gerrit-Change-Number: 35718 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 02 Oct 2019 08:22:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit October 2019