coreboot-gerrit October 2019

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Change in coreboot[master]: google/kukui: force run dram full-k blob
by huayang duan (Code Review) 09 Oct '19

09 Oct '19

huayang duan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35110 ) Change subject: google/kukui: force run dram full-k blob ...................................................................... google/kukui: force run dram full-k blob Force load dram.bin and run it for full dram calibration. BUG=b:134351649 BRANCH=none TEST=emerge-kukui coreboot Change-Id: I8de29b14b1fb24b3b4f351c855c5c4d8f350cc34 Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/mainboard/google/kukui/romstage.c 1 file changed, 53 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/35110/1 diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c index 131d167..f3774a1 100644 --- a/src/mainboard/google/kukui/romstage.c +++ b/src/mainboard/google/kukui/romstage.c @@ -14,6 +14,7 @@ */ #include <arch/stages.h> +#include <assert.h> #include <soc/emi.h> #include <soc/mmu_operations.h> #include <soc/mt6358.h> @@ -33,7 +34,7 @@ int (*dram_init)(void *param); size_t blob_size, region_size; - region_size = _edram_init_code - _dram_init_code; + region_size = REGION_SIZE(dram_init_code); blob_size = cbfs_boot_load_file("dram.bin", _dram_init_code, region_size, CBFS_TYPE_RAW); if (blob_size == 0) { @@ -42,18 +43,43 @@ } dram_init = (int (*)(void *))_dram_init_code; + printk(BIOS_ERR, "dram.bin after _dram_init_code\n"); return dram_init(NULL); } +static const struct sdram_params *get_full_k_param(void) +{ + const struct sdram_params *params = NULL; + + //load params from flash(the params generated by full-k blob) + //TODO + //params = read_params_from_flash() + params = get_sdram_config(); + + return params; +} + +static bool force_full_k_dram = true; static void dram_initialize(void) { - int err = dram_blob_load_and_run(); - if (err == 0) - return; + const struct sdram_params *params = NULL; - printk(BIOS_ERR, "dram_blob error:%d\n", err); - mt_mem_init(get_sdram_config()); + params = get_full_k_param(); + + //if (!params->have_full_k_params) { + if (force_full_k_dram) { + int err = dram_blob_load_and_run(); + if (err == 0) { + printk(BIOS_INFO, "dram_blob load success\n"); + return; + } + printk(BIOS_ERR, "dram_blob error:%d\n", err); + } + + //load params from sdram-ddr-config + params = get_sdram_config(); + mt_mem_init(params); } void platform_romstage_main(void) @@ -69,5 +95,26 @@ pmic_init_scp_voltage(); rtc_boot(); dram_initialize(); + + printk(BIOS_DEBUG, "before do first complex_mem_test \n"); + for (u8 *addr = (u8*)0x40000000; addr < (u8*)0x100000000; addr+=0x40000000) { + int i = complex_mem_test(addr, 0x50000); + + printk(BIOS_DEBUG, "[MEM]addr:0x%p complex R/W mem test %s : %d\n", addr, + (i == 0) ? "pass" : "fail", i); + + ASSERT(i == 0); + } + mtk_mmu_after_dram(); + + printk(BIOS_DEBUG, "before do second complex_mem_test \n"); + for (u8 *addr = (u8*)0x40000000; addr < (u8*)0x100000000; addr+=0x40000000) { + int i = complex_mem_test(addr, 0x50000); + + printk(BIOS_DEBUG, "[MEM]addr:0x%p complex R/W mem test %s : %d\n", addr, + (i == 0) ? "pass" : "fail", i); + + ASSERT(i == 0); + } } -- To view, visit https://review.coreboot.org/c/coreboot/+/35110 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8de29b14b1fb24b3b4f351c855c5c4d8f350cc34 Gerrit-Change-Number: 35110 Gerrit-PatchSet: 1 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mediatek/mt8183: Use calibration result do fast calibration
by huayang duan (Code Review) 09 Oct '19

09 Oct '19

huayang duan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35164 ) Change subject: mediatek/mt8183: Use calibration result do fast calibration ...................................................................... mediatek/mt8183: Use calibration result do fast calibration Load calibration result from flash, if result was correct, use this calibration result do fast calibration to reduce the bootup time. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui. Change-Id: I9ef4265dd369a1c276bb02294696556df927e7bc Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/soc/mediatek/mt8183/dramc_init_setting.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/emi.h M src/soc/mediatek/mt8183/memory.c 5 files changed, 366 insertions(+), 254 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/35164/1 diff --git a/src/soc/mediatek/mt8183/dramc_init_setting.c b/src/soc/mediatek/mt8183/dramc_init_setting.c index 9103c2d..232b4cf 100644 --- a/src/soc/mediatek/mt8183/dramc_init_setting.c +++ b/src/soc/mediatek/mt8183/dramc_init_setting.c @@ -601,45 +601,54 @@ static void dramc_duty_calibration(const struct sdram_params *params, u8 freq_group) { - s8 clkDelay[CHANNEL_MAX] = {0x0}; - s8 dqsDelay[CHANNEL_MAX][DQS_NUMBER] = {0x0}; + if (params->have_full_k_params) { + dramc_dbg("bypass duty calibration\n"); - switch (freq_group) { - case LP4X_DDR1600: - clkDelay[CHANNEL_A] = 2; - clkDelay[CHANNEL_B] = 1; - dqsDelay[CHANNEL_A][0] = 0; - dqsDelay[CHANNEL_A][1] = 0; - dqsDelay[CHANNEL_B][0] = -1; - dqsDelay[CHANNEL_B][1] = 0; - break; - case LP4X_DDR2400: - clkDelay[CHANNEL_A] = clkDelay[CHANNEL_B] = 0; - dqsDelay[CHANNEL_A][0] = 0; - dqsDelay[CHANNEL_A][1] = -2; - dqsDelay[CHANNEL_B][0] = 0; - dqsDelay[CHANNEL_B][1] = -2; - break; - case LP4X_DDR3200: - clkDelay[CHANNEL_A] = clkDelay[CHANNEL_B] = 1; - dqsDelay[CHANNEL_A][0] = 1; - dqsDelay[CHANNEL_A][1] = -2; - dqsDelay[CHANNEL_B][0] = 1; - dqsDelay[CHANNEL_B][1] = -2; - break; - case LP4X_DDR3600: - clkDelay[CHANNEL_A] = 2; - clkDelay[CHANNEL_B] = 1; - dqsDelay[CHANNEL_A][0] = 0; - dqsDelay[CHANNEL_A][1] = 0; - dqsDelay[CHANNEL_B][0] = -1; - dqsDelay[CHANNEL_B][1] = 0; - break; - } + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + dramc_duty_set_clk_delay(chn, params->duty_clk_delay[chn]); + dramc_duty_set_dqs_delay(chn, params->duty_dqs_delay[chn]); + } + } else { + s8 clkDelay[CHANNEL_MAX] = {0x0}; + s8 dqsDelay[CHANNEL_MAX][DQS_NUMBER] = {0x0}; - for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { - dramc_duty_set_clk_delay(chn, clkDelay[chn]); - dramc_duty_set_dqs_delay(chn, dqsDelay[chn]); + switch (freq_group) { + case LP4X_DDR1600: + clkDelay[CHANNEL_A] = 2; + clkDelay[CHANNEL_B] = 1; + dqsDelay[CHANNEL_A][0] = 0; + dqsDelay[CHANNEL_A][1] = 0; + dqsDelay[CHANNEL_B][0] = -1; + dqsDelay[CHANNEL_B][1] = 0; + break; + case LP4X_DDR2400: + clkDelay[CHANNEL_A] = clkDelay[CHANNEL_B] = 0; + dqsDelay[CHANNEL_A][0] = 0; + dqsDelay[CHANNEL_A][1] = -2; + dqsDelay[CHANNEL_B][0] = 0; + dqsDelay[CHANNEL_B][1] = -2; + break; + case LP4X_DDR3200: + clkDelay[CHANNEL_A] = clkDelay[CHANNEL_B] = 1; + dqsDelay[CHANNEL_A][0] = 1; + dqsDelay[CHANNEL_A][1] = -2; + dqsDelay[CHANNEL_B][0] = 1; + dqsDelay[CHANNEL_B][1] = -2; + break; + case LP4X_DDR3600: + clkDelay[CHANNEL_A] = 2; + clkDelay[CHANNEL_B] = 1; + dqsDelay[CHANNEL_A][0] = 0; + dqsDelay[CHANNEL_A][1] = 0; + dqsDelay[CHANNEL_B][0] = -1; + dqsDelay[CHANNEL_B][1] = 0; + break; + } + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + dramc_duty_set_clk_delay(chn, clkDelay[chn]); + dramc_duty_set_dqs_delay(chn, dqsDelay[chn]); + } } } diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index 39ea0b3..220a319 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -244,17 +244,25 @@ static void dramc_cmd_bus_training(u8 chn, u8 rank, u8 freq_group, const struct sdram_params *params) { - u32 cbt_cs, mr12_value; + u32 final_vref, clk_dly, cmd_dly, cs_dly; - cbt_cs = params->cbt_cs[chn][rank]; - mr12_value = params->cbt_mr12[chn][rank]; + clk_dly = params->cbt_clk_dly[chn][rank]; + cmd_dly = params->cbt_cmd_dly[chn][rank]; + cs_dly = params->cbt_cs_dly[chn][rank]; + final_vref = params->cbt_final_vref[chn][rank]; - /* CBT adjust cs */ - clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].ca_cmd[9], - SHU1_CA_CMD9_RG_RK_ARFINE_TUNE_CS_MASK, cbt_cs << 0); + if (params->have_full_k_params) { + /* Set CLK and CA delay */ + clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].ca_cmd[9], + (0x3f << 8) | (0x3f << 24), (cmd_dly << 8) | (clk_dly << 24)); + udelay(1); + } + + /* Set CLK and CS delay */ + clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].ca_cmd[9], 0x3f, cs_dly << 0); /* CBT set vref */ - dramc_mode_reg_write_by_rank(chn, rank, 12, mr12_value); + dramc_mode_reg_write_by_rank(chn, rank, 12, final_vref); } static void dramc_read_dbi_onoff(bool on) @@ -885,112 +893,124 @@ coarse_end = coarse_start + 12; dramc_dbg("[Gating]\n"); - for (u32 coarse_tune = coarse_start; coarse_tune < coarse_end; coarse_tune++) { - u32 dly_coarse_large_rodt = 0, dly_coarse_0p5t_rodt = 0; - u32 dly_coarse_large_rodt_p1 = 4, dly_coarse_0p5t_rodt_p1 = 4; - u8 dly_coarse_large = coarse_tune / RX_DQS_CTL_LOOP; - u8 dly_coarse_0p5t = coarse_tune % RX_DQS_CTL_LOOP; - u32 dly_coarse_large_p1 = (coarse_tune + freqDiv) / RX_DQS_CTL_LOOP; - u32 dly_coarse_0p5t_p1 = (coarse_tune + freqDiv) % RX_DQS_CTL_LOOP; - u32 value = (dly_coarse_large << 3) + dly_coarse_0p5t; + if (params->have_full_k_params) { + dramc_dbg("[bypass Gating]\n"); + } else { + for (u32 coarse_tune = coarse_start; coarse_tune < coarse_end; coarse_tune++) { + u32 dly_coarse_large_rodt = 0, dly_coarse_0p5t_rodt = 0; + u32 dly_coarse_large_rodt_p1 = 4, dly_coarse_0p5t_rodt_p1 = 4; - if (value >= 11) { - value -= 11; - dly_coarse_large_rodt = value >> 3; + u8 dly_coarse_large = coarse_tune / RX_DQS_CTL_LOOP; + u8 dly_coarse_0p5t = coarse_tune % RX_DQS_CTL_LOOP; + u32 dly_coarse_large_p1 = (coarse_tune + freqDiv) / RX_DQS_CTL_LOOP; + u32 dly_coarse_0p5t_p1 = (coarse_tune + freqDiv) % RX_DQS_CTL_LOOP; + u32 value = (dly_coarse_large << 3) + dly_coarse_0p5t; + + if (value >= 11) { + value -= 11; + dly_coarse_large_rodt = value >> 3; dly_coarse_0p5t_rodt = value - (dly_coarse_large_rodt << 3); - value = (dly_coarse_large << 3) + dly_coarse_0p5t - 11; - dly_coarse_large_rodt_p1 = value >> 3; + value = (dly_coarse_large << 3) + dly_coarse_0p5t - 11; + dly_coarse_large_rodt_p1 = value >> 3; dly_coarse_0p5t_rodt_p1 = value - (dly_coarse_large_rodt_p1 << 3); - } + } - clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0, - 0x77777777, - (dly_coarse_large << 0) | (dly_coarse_large << 8) | - (dly_coarse_large << 16) | (dly_coarse_large << 24) | - (dly_coarse_large_p1 << 4) | (dly_coarse_large_p1 << 12) | - (dly_coarse_large_p1 << 20) | (dly_coarse_large_p1 << 28)); - clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg1, - 0x77777777, - (dly_coarse_0p5t << 0) | (dly_coarse_0p5t << 8) | - (dly_coarse_0p5t << 16) | (dly_coarse_0p5t << 24) | - (dly_coarse_0p5t_p1 << 4) | (dly_coarse_0p5t_p1 << 12) | - (dly_coarse_0p5t_p1 << 20) | (dly_coarse_0p5t_p1 << 28)); - clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_odten0, - 0x77777777, - (dly_coarse_large_rodt << 0) | (dly_coarse_large_rodt << 8) | - (dly_coarse_large_rodt << 16) | (dly_coarse_large_rodt << 24) | - (dly_coarse_large_rodt_p1 << 4) | (dly_coarse_large_rodt_p1 << 12) | - (dly_coarse_large_rodt_p1 << 20) | (dly_coarse_large_rodt_p1 << 28)); - clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_odten1, - 0x77777777, - (dly_coarse_0p5t_rodt << 0) | (dly_coarse_0p5t_rodt << 8) | - (dly_coarse_0p5t_rodt << 16) | (dly_coarse_0p5t_rodt << 24) | - (dly_coarse_0p5t_rodt_p1 << 4) | (dly_coarse_0p5t_rodt_p1 << 12) | - (dly_coarse_0p5t_rodt_p1 << 20) | (dly_coarse_0p5t_rodt_p1 << 28)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0, + 0x77777777, + (dly_coarse_large << 0) | (dly_coarse_large << 8) | + (dly_coarse_large << 16) | (dly_coarse_large << 24) | + (dly_coarse_large_p1 << 4) | (dly_coarse_large_p1 << 12) | + (dly_coarse_large_p1 << 20) | (dly_coarse_large_p1 << 28)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg1, + 0x77777777, + (dly_coarse_0p5t << 0) | (dly_coarse_0p5t << 8) | + (dly_coarse_0p5t << 16) | (dly_coarse_0p5t << 24) | + (dly_coarse_0p5t_p1 << 4) | (dly_coarse_0p5t_p1 << 12) | + (dly_coarse_0p5t_p1 << 20) | (dly_coarse_0p5t_p1 << 28)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_odten0, + 0x77777777, + (dly_coarse_large_rodt << 0) | (dly_coarse_large_rodt << 8) | + (dly_coarse_large_rodt << 16) | (dly_coarse_large_rodt << 24) | + (dly_coarse_large_rodt_p1 << 4) | (dly_coarse_large_rodt_p1 << 12) | + (dly_coarse_large_rodt_p1 << 20) | (dly_coarse_large_rodt_p1 << 28)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_odten1, + 0x77777777, + (dly_coarse_0p5t_rodt << 0) | (dly_coarse_0p5t_rodt << 8) | + (dly_coarse_0p5t_rodt << 16) | (dly_coarse_0p5t_rodt << 24) | + (dly_coarse_0p5t_rodt_p1 << 4) | (dly_coarse_0p5t_rodt_p1 << 12) | + (dly_coarse_0p5t_rodt_p1 << 20) | (dly_coarse_0p5t_rodt_p1 << 28)); - for (u8 dly_fine_xt = 0; dly_fine_xt < DQS_GW_FINE_END; dly_fine_xt += 4) { - dramc_set_gating_mode(chn, 0); - write32(&ch[chn].ao.shu[0].rk[rank].dqsien, - dly_fine_xt | (dly_fine_xt << 8)); + for (u8 dly_fine_xt = 0; dly_fine_xt < DQS_GW_FINE_END; dly_fine_xt += 4) { + dramc_set_gating_mode(chn, 0); + write32(&ch[chn].ao.shu[0].rk[rank].dqsien, + dly_fine_xt | (dly_fine_xt << 8)); - dram_phy_reset(chn); + dram_phy_reset(chn); setbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_DQSGCNTRST_SHIFT); udelay(1); clrbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_DQSGCNTRST_SHIFT); - dramc_engine2_run(chn, TE_OP_READ_CHECK); + dramc_engine2_run(chn, TE_OP_READ_CHECK); - u32 result_r = read32(&ch[chn].phy.misc_stberr_rk0_r) & - MISC_STBERR_RK_R_STBERR_RK_R_MASK; - u32 result_f = read32(&ch[chn].phy.misc_stberr_rk0_f) & - MISC_STBERR_RK_F_STBERR_RK_F_MASK; - debug_cnt[0] = read32(&ch[chn].nao.dqsgnwcnt[0]); - debug_cnt[1] = (debug_cnt[0] >> 16) & 0xffff; - debug_cnt[0] &= 0xffff; + u32 result_r = read32(&ch[chn].phy.misc_stberr_rk0_r) & + MISC_STBERR_RK_R_STBERR_RK_R_MASK; + u32 result_f = read32(&ch[chn].phy.misc_stberr_rk0_f) & + MISC_STBERR_RK_F_STBERR_RK_F_MASK; + debug_cnt[0] = read32(&ch[chn].nao.dqsgnwcnt[0]); + debug_cnt[1] = (debug_cnt[0] >> 16) & 0xffff; + debug_cnt[0] &= 0xffff; - dramc_set_gating_mode(chn, 1); - dramc_engine2_run(chn, TE_OP_READ_CHECK); + dramc_set_gating_mode(chn, 1); + dramc_engine2_run(chn, TE_OP_READ_CHECK); - dramc_find_dly_tune(chn, dly_coarse_large, - dly_coarse_0p5t, dly_fine_xt, dqs_high, - dly_coarse_large_cnt, dly_coarse_0p5t_cnt, - dly_fine_tune_cnt, dqs_transition, dqs_done); + dramc_find_dly_tune(chn, dly_coarse_large, + dly_coarse_0p5t, dly_fine_xt, dqs_high, + dly_coarse_large_cnt, dly_coarse_0p5t_cnt, + dly_fine_tune_cnt, dqs_transition, dqs_done); - dramc_dbg("%d %d %d |", dly_coarse_large, - dly_coarse_0p5t, dly_fine_xt); - for (dqs = 0; dqs < DQS_NUMBER; dqs++) - dramc_dbg("%X ", debug_cnt[dqs]); + dramc_dbg("%d %d %d |", dly_coarse_large, + dly_coarse_0p5t, dly_fine_xt); + for (dqs = 0; dqs < DQS_NUMBER; dqs++) + dramc_dbg("%X ", debug_cnt[dqs]); - dramc_dbg(" |"); - for (dqs = 0; dqs < DQS_NUMBER; dqs++) { - dramc_dbg("(%X %X)", - (result_f >> (DQS_BIT_NUMBER * dqs)) & 0xff, - (result_r >> (DQS_BIT_NUMBER * dqs)) & 0xff); + dramc_dbg(" |"); + for (dqs = 0; dqs < DQS_NUMBER; dqs++) { + dramc_dbg("(%X %X)", + (result_f >> (DQS_BIT_NUMBER * dqs)) & 0xff, + (result_r >> (DQS_BIT_NUMBER * dqs)) & 0xff); + } + + dramc_dbg("\n"); + if (dramc_find_gating_window(result_r, result_f, debug_cnt, + dly_coarse_large, dly_coarse_0p5t, pass_begin, pass_count, + pass_count_1, &dly_fine_xt, dqs_high, dqs_done)) + coarse_tune = coarse_end; } - - dramc_dbg("\n"); - if (dramc_find_gating_window(result_r, result_f, debug_cnt, - dly_coarse_large, dly_coarse_0p5t, pass_begin, pass_count, - pass_count_1, &dly_fine_xt, dqs_high, dqs_done)) - coarse_tune = coarse_end; } + + dramc_engine2_end(chn); + write32(&ch[chn].ao.dummy_rd, dummy_rd_backup); } - dramc_engine2_end(chn); - write32(&ch[chn].ao.dummy_rd, dummy_rd_backup); - for (dqs = 0; dqs < DQS_NUMBER; dqs++) { - pass_count[dqs] = dqs_transition[dqs]; - min_fine_tune[dqs] = dly_fine_tune_cnt[dqs]; - min_coarse_tune0p5t[dqs] = dly_coarse_0p5t_cnt[dqs]; - min_coarse_tune2t[dqs] = dly_coarse_large_cnt[dqs]; - + if (params->have_full_k_params) { + dramc_dbg("[bypass Gating params] dqs:%d\n", dqs); + pass_count[dqs] = params->gating_pass_count[chn][rank][dqs]; + min_fine_tune[dqs] = params->gating_fine_tune[chn][rank][dqs]; + min_coarse_tune0p5t[dqs] = params->gating05T[chn][rank][dqs]; + min_coarse_tune2t[dqs] = params->gating2T[chn][rank][dqs]; + } else { + pass_count[dqs] = dqs_transition[dqs]; + min_fine_tune[dqs] = dly_fine_tune_cnt[dqs]; + min_coarse_tune0p5t[dqs] = dly_coarse_0p5t_cnt[dqs]; + min_coarse_tune2t[dqs] = dly_coarse_large_cnt[dqs]; + } u8 tmp_offset = pass_count[dqs] * DQS_GW_FINE_STEP / 2; u8 tmp_value = min_fine_tune[dqs] + tmp_offset; best_fine_tune[dqs] = tmp_value % RX_DLY_DQSIENSTB_LOOP; @@ -1551,20 +1571,34 @@ else use_delay_cell = 0; - for (u8 byte = 0; byte < DQS_NUMBER; byte++) { - center_dly[byte].min_center = 0xffff; - center_dly[byte].max_center = 0; - - for (u8 bit = 0; bit < DQS_BIT_NUMBER; bit++) { - index = bit + 8 * byte; - if (vref_dly[index].win_center < center_dly[byte].min_center) - center_dly[byte].min_center = vref_dly[index].win_center; - if (vref_dly[index].win_center > center_dly[byte].max_center) - center_dly[byte].max_center = vref_dly[index].win_center; + if (params->have_full_k_params && (bypass_tx)) { + dramc_dbg("bypass TX\n"); + for (u8 byte = 0; byte < DQS_NUMBER; byte++) { + center_dly[byte].min_center = params->tx_center_min[chn][rank][byte]; + center_dly[byte].max_center = params->tx_center_max[chn][rank][byte]; + for (u8 bit = 0; bit < DQS_BIT_NUMBER; bit++) { + index = bit + 8 * byte; + vref_dly[index].win_center = params->tx_win_center[chn][rank][index]; + vref_dly[index].best_first = params->tx_first_pass[chn][rank][index]; + vref_dly[index].best_last = params->tx_last_pass[chn][rank][index]; + } } - dramc_dbg("[channel %d] [rank %d] byte:%d, center_dly[byte].min_center:%d, center_dly[byte].max_center:%d\n", - chn, rank, byte, center_dly[byte].min_center, - center_dly[byte].max_center); + } else { + for (u8 byte = 0; byte < DQS_NUMBER; byte++) { + center_dly[byte].min_center = 0xffff; + center_dly[byte].max_center = 0; + + for (u8 bit = 0; bit < DQS_BIT_NUMBER; bit++) { + index = bit + 8 * byte; + if (vref_dly[index].win_center < center_dly[byte].min_center) + center_dly[byte].min_center = vref_dly[index].win_center; + if (vref_dly[index].win_center > center_dly[byte].max_center) + center_dly[byte].max_center = vref_dly[index].win_center; + } + dramc_dbg("[channel %d] [rank %d] byte:%d, center_dly[byte].min_center:%d, center_dly[byte].max_center:%d\n", + chn, rank, byte, center_dly[byte].min_center, + center_dly[byte].max_center); + } } for (u8 byte = 0; byte < DQS_NUMBER; byte++) { @@ -1681,12 +1715,26 @@ u8 fsp = get_freq_fsq(freq_group); u8 vref_range = !fsp; + bool bypass_tx = !fsp; dramc_get_vref_prop(rank, type, fsp, &vref_scan_enable, &vref_begin, &vref_end); dramc_get_dly_range(chn, rank, type, freq_group, dq_precal_result, &dly_begin, &dly_end, params); + if (params->have_full_k_params) { + if (type == RX_WIN_TEST_ENG && vref_scan_enable == 1) { + vref_begin = params->rx_vref[chn]; + vref_end = vref_begin + 1; + dramc_dbg("bypass RX vref:%d\n", vref_begin); + } else if (type == TX_WIN_DQ_ONLY) { + vref_begin = params->tx_vref[chn][rank]; + vref_end = vref_begin + 1; + dramc_dbg("bypass TX vref:%d\n", vref_begin); + } + vref_dly.best_vref = vref_begin; + } + if ((type == RX_WIN_RD_DQC || type == RX_WIN_TEST_ENG) && fsp == FSP_0) dly_step = 2; @@ -1705,98 +1753,112 @@ vref_step = 2; } - if (type == RX_WIN_RD_DQC) { - dramc_rx_rd_dqc_init(chn, rank); - } else { - if (type == RX_WIN_TEST_ENG) - dramc_rx_vref_pre_setting(chn); - dummy_rd_bak_engine2 = read32(&ch[chn].ao.dummy_rd); - dramc_engine2_init(chn, rank, TEST2_1_CAL, TEST2_2_CAL, false); - } - - vref_dly.max_win_sum = 0; - for (vref = vref_begin; vref < vref_end; vref += vref_step) { - small_reg_value = 0xff; - finish_bit = 0; - if (type == TX_WIN_DQ_ONLY) - vref_use = vref | (vref_range << 6); - else - vref_use = vref; - - for (size_t bit = 0; bit < DQ_DATA_WIDTH; bit++) { - win_perbit[bit].first_pass = PASS_RANGE_NA; - win_perbit[bit].last_pass = PASS_RANGE_NA; - win_perbit[bit].best_first = PASS_RANGE_NA; - win_perbit[bit].best_last = PASS_RANGE_NA; + if (params->have_full_k_params && bypass_tx && + (type == TX_WIN_DQ_ONLY || type == TX_WIN_DQ_DQM)) { + dramc_set_tx_best_dly(chn, rank, bypass_tx,vref_dly.perbit_dly, type, + freq_group, dq_precal_result, dly_cell_unit, params); + } else { + if (type == RX_WIN_RD_DQC) { + dramc_rx_rd_dqc_init(chn, rank); + } else { + if (type == RX_WIN_TEST_ENG) + dramc_rx_vref_pre_setting(chn); + dummy_rd_bak_engine2 = read32(&ch[chn].ao.dummy_rd); + dramc_engine2_init(chn, rank, TEST2_1_CAL, TEST2_2_CAL, false); } - if (vref_scan_enable) - dramc_set_vref(chn, rank, type, vref_use); - - if (type == RX_WIN_RD_DQC || type == RX_WIN_TEST_ENG) { - dramc_set_rx_dly_factor(chn, rank, - RX_DQM, FIRST_DQ_DELAY); - dramc_set_rx_dly_factor(chn, rank, - RX_DQ, FIRST_DQ_DELAY); - } - - for (dly = dly_begin; dly < dly_end; dly += dly_step) { - dramc_set_dqdqs_dly(chn, rank, type, &small_reg_value, dly); - - err_value = dram_k_perbit(chn, type); - if (!vref_scan_enable) - dramc_dbg("%d ", dly); + vref_dly.max_win_sum = 0; + for (vref = vref_begin; vref < vref_end; vref += vref_step) { + small_reg_value = 0xff; + finish_bit = 0; + if (type == TX_WIN_DQ_ONLY) + vref_use = vref | (vref_range << 6); + else + vref_use = vref; for (size_t bit = 0; bit < DQ_DATA_WIDTH; bit++) { - bool bit_fail = (err_value & ((u32) 1 << bit)) != 0; - - /* pass window bigger than 7, consider as real pass window */ - if (dramc_check_dqdqs_win(&(win_perbit[bit]), - dly, dly_end, bit_fail) > 7) - finish_bit |= (1 << bit); - - if (vref_scan_enable) - continue; - dramc_dbg("%s", bit_fail ? "x" : "o"); - if (bit % DQS_BIT_NUMBER == 7) - dramc_dbg(" "); + win_perbit[bit].first_pass = PASS_RANGE_NA; + win_perbit[bit].last_pass = PASS_RANGE_NA; + win_perbit[bit].best_first = PASS_RANGE_NA; + win_perbit[bit].best_last = PASS_RANGE_NA; } - if (!vref_scan_enable) - dramc_dbg(" [MSB]\n"); + if (vref_scan_enable) + dramc_set_vref(chn, rank, type, vref_use); - if (finish_bit == 0xffff && (err_value & 0xffff) == 0xffff) { - dramc_dbg("all bits window found, early break! delay=0x%x\n", - dly); - break; + if (type == RX_WIN_RD_DQC || type == RX_WIN_TEST_ENG) { + dramc_set_rx_dly_factor(chn, rank, + RX_DQM, FIRST_DQ_DELAY); + dramc_set_rx_dly_factor(chn, rank, + RX_DQ, FIRST_DQ_DELAY); + } + + if (params->have_full_k_params && (type == RX_WIN_RD_DQC ||type == RX_WIN_TEST_ENG)) { + dramc_dbg("bypass RX params\n"); + for (size_t bit = 0; bit < DQ_DATA_WIDTH; bit++) { + win_perbit[bit].best_first = params->rx_firspass[chn][rank][bit]; + win_perbit[bit].best_last = params->rx_lastpass[chn][rank][bit]; + } + } else { + for (dly = dly_begin; dly < dly_end; dly += dly_step) { + dramc_set_dqdqs_dly(chn, rank, type, &small_reg_value, dly); + + err_value = dram_k_perbit(chn, type); + if (!vref_scan_enable) + dramc_dbg("%d ", dly); + + for (size_t bit = 0; bit < DQ_DATA_WIDTH; bit++) { + bool bit_fail = (err_value & ((u32) 1 << bit)) != 0; + + /* pass window bigger than 7, consider as real pass window */ + if (dramc_check_dqdqs_win(&(win_perbit[bit]), + dly, dly_end, bit_fail) > 7) + finish_bit |= (1 << bit); + + if (vref_scan_enable) + continue; + dramc_dbg("%s", bit_fail ? "x" : "o"); + if (bit % DQS_BIT_NUMBER == 7) + dramc_dbg(" "); + } + + if (!vref_scan_enable) + dramc_dbg(" [MSB]\n"); + + if (finish_bit == 0xffff && (err_value & 0xffff) == 0xffff) { + dramc_dbg("all bits window found, early break! delay=0x%x\n", + dly); + break; + } } } - for (size_t bit = 0; bit < DQ_DATA_WIDTH; bit++) - dramc_dbg("Dq[%zd] win width (%d ~ %d) %d\n", bit, - win_perbit[bit].best_first, win_perbit[bit].best_last, - win_perbit[bit].best_last - win_perbit[bit].best_first); + for (size_t bit = 0; bit < DQ_DATA_WIDTH; bit++) + dramc_dbg("Dq[%zd] win width (%d ~ %d) %d\n", bit, + win_perbit[bit].best_first, win_perbit[bit].best_last, + win_perbit[bit].best_last - win_perbit[bit].best_first); - if (dramk_calc_best_vref(type, vref_use, &vref_dly, win_perbit, &win_min_max)) - break; + if (dramk_calc_best_vref(type, vref_use, &vref_dly, win_perbit, &win_min_max)) + break; + } + + if (type == RX_WIN_RD_DQC) { + dramc_rx_rd_dqc_end(chn); + } else { + dramc_engine2_end(chn); + write32(&ch[chn].ao.dummy_rd, dummy_rd_bak_engine2); + } + + if (vref_scan_enable && type == RX_WIN_TEST_ENG) + dramc_set_vref(chn, rank, type, vref_dly.best_vref); + + if (type == RX_WIN_RD_DQC || type == RX_WIN_TEST_ENG) + dramc_set_rx_best_dly(chn, rank, vref_dly.perbit_dly); + else + dramc_set_tx_best_dly(chn, rank, false, vref_dly.perbit_dly, type, + freq_group, dq_precal_result, dly_cell_unit, params); } - if (type == RX_WIN_RD_DQC) { - dramc_rx_rd_dqc_end(chn); - } else { - dramc_engine2_end(chn); - write32(&ch[chn].ao.dummy_rd, dummy_rd_bak_engine2); - } - - if (vref_scan_enable && type == RX_WIN_TEST_ENG) - dramc_set_vref(chn, rank, type, vref_dly.best_vref); - - if (type == RX_WIN_RD_DQC || type == RX_WIN_TEST_ENG) - dramc_set_rx_best_dly(chn, rank, vref_dly.perbit_dly); - else - dramc_set_tx_best_dly(chn, rank, false, vref_dly.perbit_dly, type, - freq_group, dq_precal_result, dly_cell_unit, params); - if (vref_scan_enable && type == TX_WIN_DQ_ONLY) dramc_set_vref(chn, rank, type, vref_dly.best_vref); @@ -1843,40 +1905,45 @@ u32 dummy_rd_backup = read32(&ch[chn].ao.dummy_rd); dramc_engine2_init(chn, rank, TEST2_1_CAL, TEST2_2_CAL, false); - for (datlat = datlat_start; datlat < DATLAT_TAP_NUMBER; datlat++) { - dramc_dle_factor_handler(chn, datlat, freq_group); + if (params->have_full_k_params) { + best_step = params->rx_datlat[chn][rank]; + dramc_dbg("bypass DATLAT, best_step:%d\n", best_step); + } else { + for (datlat = datlat_start; datlat < DATLAT_TAP_NUMBER; datlat++) { + dramc_dle_factor_handler(chn, datlat, freq_group); - u32 err = dramc_engine2_run(chn, TE_OP_WRITE_READ_CHECK); - if (err == 0) { - if (begin == 0) { - first = datlat; - begin = 1; + u32 err = dramc_engine2_run(chn, TE_OP_WRITE_READ_CHECK); + if (err == 0) { + if (begin == 0) { + first = datlat; + begin = 1; + } + if (begin == 1) { + sum++; + if (sum > 4) + break; + } + } else { + if (begin == 1) + begin = 0xff; } - if (begin == 1) { - sum++; - if (sum > 4) - break; - } - } else { - if (begin == 1) - begin = 0xff; + + dramc_dbg("Datlat=%2d, err_value=0x%4x, sum=%d\n", datlat, err, sum); } - dramc_dbg("Datlat=%2d, err_value=0x%4x, sum=%d\n", datlat, err, sum); + dramc_engine2_end(chn); + write32(&ch[chn].ao.dummy_rd, dummy_rd_backup); + + assert(sum != 0); + + if (sum <= 3) + best_step = first + (sum >> 1); + else + best_step = first + 2; + dramc_dbg("First_step=%d, total pass=%d, best_step=%d\n", + begin, sum, best_step); } - dramc_engine2_end(chn); - write32(&ch[chn].ao.dummy_rd, dummy_rd_backup); - - assert(sum != 0); - - if (sum <= 3) - best_step = first + (sum >> 1); - else - best_step = first + 2; - dramc_dbg("First_step=%d, total pass=%d, best_step=%d\n", - begin, sum, best_step); - dramc_dle_factor_handler(chn, best_step, freq_group); clrsetbits_le32(&ch[chn].ao.padctrl, 0x3 | (0x1 << 3), diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index 818458c..f51428b 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -383,17 +383,19 @@ pmic_set_vdram2_vol(vddq); } -void mt_set_emi(const struct sdram_params *params) +void mt_set_emi(const struct sdram_params *freq_params) { - u32 current_freq = LP4X_HIGH_FREQ; + u8 current_freq = LP4X_HIGH_FREQ; + const struct sdram_params *params = NULL; #if DUAL_FREQ_K - u32 low_freq, middle_freq, high_freq; + u8 low_freq, middle_freq, high_freq; low_freq = LP4X_LOW_FREQ; middle_freq = LP4X_MIDDLE_FREQ; high_freq = LP4X_HIGH_FREQ; current_freq = low_freq; + params = &freq_params[current_freq]; #endif set_dram_voltage_by_freq(current_freq); @@ -402,11 +404,13 @@ #if DUAL_FREQ_K current_freq = middle_freq; + params = &freq_params[current_freq]; set_dram_voltage_by_freq(current_freq); dfs_init_for_calibration(params, current_freq); do_calib(params, current_freq); current_freq = high_freq; + params = &freq_params[current_freq]; set_dram_voltage_by_freq(current_freq); dfs_init_for_calibration(params, current_freq); do_calib(params, current_freq); diff --git a/src/soc/mediatek/mt8183/include/soc/emi.h b/src/soc/mediatek/mt8183/include/soc/emi.h index 264d918..07c4827 100644 --- a/src/soc/mediatek/mt8183/include/soc/emi.h +++ b/src/soc/mediatek/mt8183/include/soc/emi.h @@ -21,10 +21,42 @@ #include <soc/dramc_common_mt8183.h> struct sdram_params { - u32 impedance[2][4]; + bool have_full_k_params; + u16 frequency; u8 wr_level[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]; - u8 cbt_cs[CHANNEL_MAX][RANK_MAX]; - u8 cbt_mr12[CHANNEL_MAX][RANK_MAX]; + + /* DUTY */ + s8 duty_clk_delay[CHANNEL_MAX]; + s8 duty_dqs_delay[CHANNEL_MAX][DQS_NUMBER]; + + /* CBT */ + u8 cbt_final_vref[CHANNEL_MAX][RANK_MAX]; + u8 cbt_clk_dly[CHANNEL_MAX][RANK_MAX]; + u8 cbt_cmd_dly[CHANNEL_MAX][RANK_MAX]; + u8 cbt_cs_dly[CHANNEL_MAX][RANK_MAX]; + + /* Gating */ + u8 gating2T[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]; + u8 gating05T[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]; + u8 gating_fine_tune[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]; + u8 gating_pass_count[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]; + + /* TX perbit */ + u8 tx_vref[CHANNEL_MAX][RANK_MAX]; + u16 tx_center_min[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]; + u16 tx_center_max[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]; + u16 tx_win_center[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH]; + u16 tx_first_pass[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH]; + u16 tx_last_pass[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH]; + + /* datlat */ + u8 rx_datlat[CHANNEL_MAX][RANK_MAX]; + + /* RX perbit */ + u8 rx_vref[CHANNEL_MAX]; + s16 rx_firspass[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH]; + u8 rx_lastpass[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH]; + u32 emi_cona_val; u32 emi_conh_val; u32 emi_conf_val; @@ -47,7 +79,7 @@ size_t sdram_size(void); const struct sdram_params *get_sdram_config(void); void enable_emi_dcm(void); -void mt_set_emi(const struct sdram_params *params); -void mt_mem_init(const struct sdram_params *params); +void mt_set_emi(const struct sdram_params *freq_params); +void mt_mem_init(const struct sdram_params *freq_params); #endif /* SOC_MEDIATEK_MT8183_EMI_H */ diff --git a/src/soc/mediatek/mt8183/memory.c b/src/soc/mediatek/mt8183/memory.c index b2c7441..67f6c65 100644 --- a/src/soc/mediatek/mt8183/memory.c +++ b/src/soc/mediatek/mt8183/memory.c @@ -19,12 +19,12 @@ #include <soc/emi.h> #include <symbols.h> -void mt_mem_init(const struct sdram_params *params) +void mt_mem_init(const struct sdram_params *freq_params) { u64 rank_size[RANK_MAX]; /* memory calibration */ - mt_set_emi(params); + mt_set_emi(freq_params); if (CONFIG(MEMORY_TEST)) { size_t r; -- To view, visit https://review.coreboot.org/c/coreboot/+/35164 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ef4265dd369a1c276bb02294696556df927e7bc Gerrit-Change-Number: 35164 Gerrit-PatchSet: 1 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-MessageType: newchange

7 69

Change in coreboot[master]: soc/mediatek/mt8183: Add the shared 'dramc_param' module
by Patrick Georgi (Code Review) 09 Oct '19

09 Oct '19

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35775 ) Change subject: soc/mediatek/mt8183: Add the shared 'dramc_param' module ...................................................................... soc/mediatek/mt8183: Add the shared 'dramc_param' module The dramc_param module simplifies the communication between coreboot and MTK DRAM full calibration blob, and is shared by both implementations to ensure the same format of parameters. BUG=b:139099592 BRANCH=none TEST=emerge-kukui coreboot Change-Id: I4cfd634da1855a76706aab0b050197251e2ed4dd Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35775 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/soc/mediatek/mt8183/Makefile.inc A src/soc/mediatek/mt8183/dramc_param.c A src/soc/mediatek/mt8183/include/soc/dramc_param.h 3 files changed, 137 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index d1171ef..72a4d9c 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -27,6 +27,7 @@ romstage-y += auxadc.c romstage-y += ../common/cbmem.c emi.c romstage-y += dramc_init_setting.c +romstage-y += dramc_param.c romstage-y += dramc_pi_basic_api.c romstage-y += dramc_pi_calibration_api.c romstage-y += memory.c diff --git a/src/soc/mediatek/mt8183/dramc_param.c b/src/soc/mediatek/mt8183/dramc_param.c new file mode 100644 index 0000000..ef3c191 --- /dev/null +++ b/src/soc/mediatek/mt8183/dramc_param.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include "soc/dramc_param.h" + +struct dramc_param *get_dramc_param_from_blob(void *blob) +{ + return (struct dramc_param *)blob; +} + +int validate_dramc_param(const void *blob) +{ + const struct dramc_param *param = blob; + const struct dramc_param_header *hdr = &param->header; + + if (hdr->magic != DRAMC_PARAM_HEADER_MAGIC) + return DRAMC_ERR_INVALID_MAGIC; + + if (hdr->version != DRAMC_PARAM_HEADER_VERSION) + return DRAMC_ERR_INVALID_VERSION; + + if (hdr->size != sizeof(*param)) + return DRAMC_ERR_INVALID_SIZE; + + /* TODO(hungte) Verify and check hdr->checksum. */ + return DRAMC_SUCCESS; +} + +int is_valid_dramc_param(const void *blob) +{ + return validate_dramc_param(blob) == DRAMC_SUCCESS; +} + +int initialize_dramc_param(void *blob, u16 config) +{ + struct dramc_param *param = blob; + struct dramc_param_header *hdr = &param->header; + + memset(blob, 0, sizeof(*param)); + hdr->magic = DRAMC_PARAM_HEADER_MAGIC; + hdr->size = sizeof(*param); + hdr->version = DRAMC_PARAM_HEADER_VERSION; + hdr->config = config; + return 0; +} diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_param.h b/src/soc/mediatek/mt8183/include/soc/dramc_param.h new file mode 100644 index 0000000..c2df459 --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/dramc_param.h @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_MEDIATEK_MT8183_DRAMC_PARAM_H +#define SOC_MEDIATEK_MT8183_DRAMC_PARAM_H + +#include <stdint.h> +#include <sys/types.h> + +#include "emi.h" + +enum { + DRAMC_PARAM_HEADER_MAGIC = 0x44524d4b, + DRAMC_PARAM_HEADER_VERSION = 1, +}; + +enum DRAMC_PARAM_STATUS_CODES { + DRAMC_SUCCESS = 0, + DRAMC_ERR_INVALID_MAGIC, + DRAMC_ERR_INVALID_VERSION, + DRAMC_ERR_INVALID_SIZE, + DRAMC_ERR_INVALID_CHECKSUM, + DRAMC_ERR_INVALID_FLAGS, + DRAMC_ERR_RECALIBRATE, + DRAMC_ERR_INIT_DRAM, + DRAMC_ERR_COMPLEX_RW_MEM_TEST, + DRAMC_ERR_1ST_COMPLEX_RW_MEM_TEST, + DRAMC_ERR_2ND_COMPLEX_RW_MEM_TEST, +}; + +/* Bit flags */ +enum DRAMC_PARAM_CONFIG { + DRAMC_CONFIG_EMCP = 0x0001, +}; + +enum DRAMC_PARAM_FLAGS { + DRAMC_FLAG_HAS_SAVED_DATA = 0x0001, +}; + +struct dramc_param_header { + u32 status; /* DRAMC_PARAM_STATUS_CODES */ + u32 magic; + u32 version; + u32 size; /* size of whole dramc_param */ + u16 config; /* DRAMC_PARAM_CONFIG */ + u16 flags; /* DRAMC_PARAM_FLAGS */ + u32 checksum; +}; + +struct dramc_param { + struct dramc_param_header header; + struct sdram_params freq_params[DRAM_DFS_SHUFFLE_MAX]; +}; + +struct dramc_param_ops { + struct dramc_param *param; + bool (*read_from_flash)(struct dramc_param *dparam); + bool (*write_to_flash)(const struct dramc_param *dparam); +}; + +struct dramc_param *get_dramc_param_from_blob(void *blob); +int validate_dramc_param(const void *blob); +int is_valid_dramc_param(const void *blob); +int initialize_dramc_param(void *blob, u16 config); + +#endif /* SOC_MEDIATEK_MT8183_DRAMC_PARAM_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4cfd634da1855a76706aab0b050197251e2ed4dd Gerrit-Change-Number: 35775 Gerrit-PatchSet: 13 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mediatek/mt8183: Simplify usage of dramc_engine2_end
by Yu-Ping Wu (Code Review) 09 Oct '19

09 Oct '19

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35749 ) Change subject: mediatek/mt8183: Simplify usage of dramc_engine2_end ...................................................................... mediatek/mt8183: Simplify usage of dramc_engine2_end Since we always write to &ch[chn].ao.dummy_rd after calling dramc_engine2_end(), this write could be merged into dramc_engine2_end() to simplify code. BUG=none BRANCH=none TEST=emerge-kukui coreboot Change-Id: Ibb4bd5ed016118811ad2097098417c19f00f4263 Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c 1 file changed, 7 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/35749/1 diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index f8b1f09..794e4f0 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -607,9 +607,10 @@ return result; } -static void dramc_engine2_end(u8 chn) +static void dramc_engine2_end(u8 chn, u32 dummy_rd) { clrbits_le32(&ch[chn].ao.test2_4, 0x1 << 17); + write32(&ch[chn].ao.dummy_rd, dummy_rd); } static bool dramc_find_gating_window(u32 result_r, u32 result_f, u32 *debug_cnt, @@ -995,8 +996,7 @@ } } - dramc_engine2_end(chn); - write32(&ch[chn].ao.dummy_rd, dummy_rd_backup); + dramc_engine2_end(chn, dummy_rd_backup); for (dqs = 0; dqs < DQS_NUMBER; dqs++) { pass_count[dqs] = dqs_transition[dqs]; @@ -1811,12 +1811,10 @@ break; } - if (type == RX_WIN_RD_DQC) { + if (type == RX_WIN_RD_DQC) dramc_rx_rd_dqc_end(chn); - } else { - dramc_engine2_end(chn); - write32(&ch[chn].ao.dummy_rd, dummy_rd_bak_engine2); - } + else + dramc_engine2_end(chn, dummy_rd_bak_engine2); if (vref_scan_enable && type == RX_WIN_TEST_ENG) dramc_set_vref(chn, rank, type, vref_dly.best_vref); @@ -1895,8 +1893,7 @@ dramc_dbg("Datlat=%2d, err_value=0x%4x, sum=%d\n", datlat, err, sum); } - dramc_engine2_end(chn); - write32(&ch[chn].ao.dummy_rd, dummy_rd_backup); + dramc_engine2_end(chn, dummy_rd_backup); assert(sum != 0); -- To view, visit https://review.coreboot.org/c/coreboot/+/35749 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb4bd5ed016118811ad2097098417c19f00f4263 Gerrit-Change-Number: 35749 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

3 12

Change in coreboot[master]: sb/intel/bd82x6x: Remove setting up lpc decode ranges in ramstage
by Arthur Heymans (Code Review) 09 Oct '19

09 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34978 ) Change subject: sb/intel/bd82x6x: Remove setting up lpc decode ranges in ramstage ...................................................................... sb/intel/bd82x6x: Remove setting up lpc decode ranges in ramstage This is now done during the romstage. Change-Id: I7c1a848ae871ffb73c09ee88f96331d6b823e39d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/bd82x6x/lpc.c 1 file changed, 0 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/34978/1 diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index bd3c993..0036bb1 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -458,18 +458,6 @@ RCBA32_OR(LCTL, 0x3); } -static void pch_decode_init(struct device *dev) -{ - config_t *config = dev->chip_info; - - printk(BIOS_DEBUG, "pch_decode_init\n"); - - pci_write_config32(dev, LPC_GEN1_DEC, config->gen1_dec); - pci_write_config32(dev, LPC_GEN2_DEC, config->gen2_dec); - pci_write_config32(dev, LPC_GEN3_DEC, config->gen3_dec); - pci_write_config32(dev, LPC_GEN4_DEC, config->gen4_dec); -} - static void pch_spi_init(const struct device *const dev) { const config_t *const config = dev->chip_info; @@ -681,7 +669,6 @@ static void pch_lpc_enable_resources(struct device *dev) { - pch_decode_init(dev); return pci_dev_enable_resources(dev); } -- To view, visit https://review.coreboot.org/c/coreboot/+/34978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c1a848ae871ffb73c09ee88f96331d6b823e39d Gerrit-Change-Number: 34978 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

5 6

Change in coreboot[master]: mb/google/drallion: Enable UART console for arcada_cml and sarien_cml
by Bernardo Perez Priego (Code Review) 09 Oct '19

09 Oct '19

Bernardo Perez Priego has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35785 ) Change subject: mb/google/drallion: Enable UART console for arcada_cml and sarien_cml ...................................................................... mb/google/drallion: Enable UART console for arcada_cml and sarien_cml Drallion uses UART 0 for console, other two variants remain as UART 2. BUG=b:139095062 TEST="emerge-drallion coreboot chromeos-bootimage. Console should be visible" Change-Id: I520a07ad6f755bc2e6481329fc69bef9a36e31e2 Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> --- M src/mainboard/google/drallion/Kconfig 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/35785/1 diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig index 35f7150..256f8cb 100644 --- a/src/mainboard/google/drallion/Kconfig +++ b/src/mainboard/google/drallion/Kconfig @@ -84,7 +84,9 @@ config UART_FOR_CONSOLE int - default 0 + default 2 if BOARD_GOOGLE_ARCADA_CML + default 2 if BOARD_GOOGLE_SARIEN_CML + default 0 if BOARD_GOOGLE_DRALLION config VARIANT_DIR string -- To view, visit https://review.coreboot.org/c/coreboot/+/35785 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I520a07ad6f755bc2e6481329fc69bef9a36e31e2 Gerrit-Change-Number: 35785 Gerrit-PatchSet: 1 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-MessageType: newchange

6 8

Change in coreboot[master]: mb/google/hatch: Remove pen device for dratini/dragonair
by Chen Wisley (Code Review) 09 Oct '19

09 Oct '19

Chen Wisley has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35844 ) Change subject: mb/google/hatch: Remove pen device for dratini/dragonair ...................................................................... mb/google/hatch: Remove pen device for dratini/dragonair Dratini/Dragonair doesn't support pen insertion/ejection feature, so remove it. BUG=b:142159117 TEST=emerge-hatch coreboot Change-Id: I64859a162d8dc75ffe55d98b72a056dd72e8de75 Signed-off-by: Wisley Chen <wisley.chen(a)quantatw.com> --- M src/mainboard/google/hatch/variants/dratini/overridetree.cb 1 file changed, 0 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/35844/1 diff --git a/src/mainboard/google/hatch/variants/dratini/overridetree.cb b/src/mainboard/google/hatch/variants/dratini/overridetree.cb index 65649d1..351c82b 100644 --- a/src/mainboard/google/hatch/variants/dratini/overridetree.cb +++ b/src/mainboard/google/hatch/variants/dratini/overridetree.cb @@ -105,17 +105,6 @@ register "hid_desc_reg_offset" = "0x01" device i2c 5d on end end - chip drivers/generic/gpio_keys - register "name" = ""PENH"" - register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A8)" - register "key.wake" = "GPE0_DW0_08" - register "key.wakeup_event_action" = "EV_ACT_ASSERTED" - register "key.dev_name" = ""EJCT"" - register "key.linux_code" = "SW_PEN_INSERTED" - register "key.linux_input_type" = "EV_SW" - register "key.label" = ""pen_eject"" - device generic 0 on end - end end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 -- To view, visit https://review.coreboot.org/c/coreboot/+/35844 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64859a162d8dc75ffe55d98b72a056dd72e8de75 Gerrit-Change-Number: 35844 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: mb/[google/intel/lenovo]/*: fix posix shell bug with SPD files
by Name of user not set (Code Review) 09 Oct '19

09 Oct '19

greg(a)unrelenting.technology has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35867 ) Change subject: mb/[google/intel/lenovo]/*: fix posix shell bug with SPD files ...................................................................... mb/[google/intel/lenovo]/*: fix posix shell bug with SPD files FreeBSD's sh (basic posix shell) did not interpret the '\%o' escape in the same way bash/zsh do. As a result, the decoded files ended up with ASCII numbers instead of the decoded binary data. Change-Id: I95b414d959e5cd4479fcf100adcf390562032c68 Signed-off-by: Greg V <greg(a)unrelenting.technology> --- M src/mainboard/google/auron/variants/auron_paine/spd/Makefile.inc M src/mainboard/google/auron/variants/auron_yuna/spd/Makefile.inc M src/mainboard/google/auron/variants/gandof/spd/Makefile.inc M src/mainboard/google/auron/variants/lulu/spd/Makefile.inc M src/mainboard/google/auron/variants/samus/spd/Makefile.inc M src/mainboard/google/dragonegg/spd/Makefile.inc M src/mainboard/google/drallion/spd/Makefile.inc M src/mainboard/google/eve/spd/Makefile.inc M src/mainboard/google/hatch/spd/Makefile.inc M src/mainboard/google/poppy/spd/Makefile.inc M src/mainboard/intel/kunimitsu/spd/Makefile.inc M src/mainboard/lenovo/t430s/variants/t431s/spd/Makefile.inc M src/mainboard/lenovo/x1_carbon_gen1/spd/Makefile.inc 13 files changed, 13 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/35867/1 diff --git a/src/mainboard/google/auron/variants/auron_paine/spd/Makefile.inc b/src/mainboard/google/auron/variants/auron_paine/spd/Makefile.inc index 26e1a75..44edc70 100644 --- a/src/mainboard/google/auron/variants/auron_paine/spd/Makefile.inc +++ b/src/mainboard/google/auron/variants/auron_paine/spd/Makefile.inc @@ -41,7 +41,7 @@ $(SPD_BIN): $(SPD_DEPS) for f in $+; \ do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ + do printf $$(printf '\\%o' 0x$$c); \ done; \ done > $@ diff --git a/src/mainboard/google/auron/variants/auron_yuna/spd/Makefile.inc b/src/mainboard/google/auron/variants/auron_yuna/spd/Makefile.inc index 26e1a75..44edc70 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/spd/Makefile.inc +++ b/src/mainboard/google/auron/variants/auron_yuna/spd/Makefile.inc @@ -41,7 +41,7 @@ $(SPD_BIN): $(SPD_DEPS) for f in $+; \ do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ + do printf $$(printf '\\%o' 0x$$c); \ done; \ done > $@ diff --git a/src/mainboard/google/auron/variants/gandof/spd/Makefile.inc b/src/mainboard/google/auron/variants/gandof/spd/Makefile.inc index f3a2162..23d0b4e 100644 --- a/src/mainboard/google/auron/variants/gandof/spd/Makefile.inc +++ b/src/mainboard/google/auron/variants/gandof/spd/Makefile.inc @@ -33,7 +33,7 @@ $(SPD_BIN): $(SPD_DEPS) for f in $+; \ do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ + do printf $$(printf '\\%o' 0x$$c); \ done; \ done > $@ diff --git a/src/mainboard/google/auron/variants/lulu/spd/Makefile.inc b/src/mainboard/google/auron/variants/lulu/spd/Makefile.inc index bc1454f..86cb2d2 100644 --- a/src/mainboard/google/auron/variants/lulu/spd/Makefile.inc +++ b/src/mainboard/google/auron/variants/lulu/spd/Makefile.inc @@ -42,7 +42,7 @@ $(SPD_BIN): $(SPD_DEPS) for f in $+; \ do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ + do printf $$(printf '\\%o' 0x$$c); \ done; \ done > $@ diff --git a/src/mainboard/google/auron/variants/samus/spd/Makefile.inc b/src/mainboard/google/auron/variants/samus/spd/Makefile.inc index 6a357c0..a026ef3 100644 --- a/src/mainboard/google/auron/variants/samus/spd/Makefile.inc +++ b/src/mainboard/google/auron/variants/samus/spd/Makefile.inc @@ -41,7 +41,7 @@ $(SPD_BIN): $(SPD_DEPS) for f in $+; \ do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ + do printf $$(printf '\\%o' 0x$$c); \ done; \ done > $@ diff --git a/src/mainboard/google/dragonegg/spd/Makefile.inc b/src/mainboard/google/dragonegg/spd/Makefile.inc index 7aa9505..2fdd9d4 100644 --- a/src/mainboard/google/dragonegg/spd/Makefile.inc +++ b/src/mainboard/google/dragonegg/spd/Makefile.inc @@ -30,7 +30,7 @@ $(SPD_BIN): $(SPD_DEPS) for f in $+; \ do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ + do printf $$(printf '\\%o' 0x$$c); \ done; \ done > $@ diff --git a/src/mainboard/google/drallion/spd/Makefile.inc b/src/mainboard/google/drallion/spd/Makefile.inc index e35544b..9ab7394 100644 --- a/src/mainboard/google/drallion/spd/Makefile.inc +++ b/src/mainboard/google/drallion/spd/Makefile.inc @@ -25,7 +25,7 @@ $(SPD_BIN): $(SPD_DEPS) for f in $+; \ do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ + do printf $$(printf '\\%o' 0x$$c); \ done; \ done > $@ diff --git a/src/mainboard/google/eve/spd/Makefile.inc b/src/mainboard/google/eve/spd/Makefile.inc index c97a818..cb4f8a8 100644 --- a/src/mainboard/google/eve/spd/Makefile.inc +++ b/src/mainboard/google/eve/spd/Makefile.inc @@ -32,7 +32,7 @@ $(SPD_BIN): $(SPD_DEPS) for f in $+; \ do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ + do printf $$(printf '\\%o' 0x$$c); \ done; \ done > $@ diff --git a/src/mainboard/google/hatch/spd/Makefile.inc b/src/mainboard/google/hatch/spd/Makefile.inc index e35544b..9ab7394 100644 --- a/src/mainboard/google/hatch/spd/Makefile.inc +++ b/src/mainboard/google/hatch/spd/Makefile.inc @@ -25,7 +25,7 @@ $(SPD_BIN): $(SPD_DEPS) for f in $+; \ do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ + do printf $$(printf '\\%o' 0x$$c); \ done; \ done > $@ diff --git a/src/mainboard/google/poppy/spd/Makefile.inc b/src/mainboard/google/poppy/spd/Makefile.inc index 444ac00..dd57835 100644 --- a/src/mainboard/google/poppy/spd/Makefile.inc +++ b/src/mainboard/google/poppy/spd/Makefile.inc @@ -5,7 +5,7 @@ define gen_spd_bin for f in $2; \ do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ + do printf $$(printf '\\%o' 0x$$c); \ done; \ done > $1 endef diff --git a/src/mainboard/intel/kunimitsu/spd/Makefile.inc b/src/mainboard/intel/kunimitsu/spd/Makefile.inc index 9856368e..4fa2d7e 100644 --- a/src/mainboard/intel/kunimitsu/spd/Makefile.inc +++ b/src/mainboard/intel/kunimitsu/spd/Makefile.inc @@ -43,7 +43,7 @@ $(SPD_BIN): $(SPD_DEPS) for f in $+; \ do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ + do printf $$(printf '\\%o' 0x$$c); \ done; \ done > $@ diff --git a/src/mainboard/lenovo/t430s/variants/t431s/spd/Makefile.inc b/src/mainboard/lenovo/t430s/variants/t431s/spd/Makefile.inc index 4b9ef55..72657b4 100644 --- a/src/mainboard/lenovo/t430s/variants/t431s/spd/Makefile.inc +++ b/src/mainboard/lenovo/t430s/variants/t431s/spd/Makefile.inc @@ -22,7 +22,7 @@ $(SPD_BIN): $(SPD_DEPS) for f in $+; \ do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ + do printf $$(printf '\\%o' 0x$$c); \ done; \ done > $@ diff --git a/src/mainboard/lenovo/x1_carbon_gen1/spd/Makefile.inc b/src/mainboard/lenovo/x1_carbon_gen1/spd/Makefile.inc index f5c233a..235fc10 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/spd/Makefile.inc +++ b/src/mainboard/lenovo/x1_carbon_gen1/spd/Makefile.inc @@ -24,7 +24,7 @@ $(SPD_BIN): $(SPD_DEPS) for f in $+; \ do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ + do printf $$(printf '\\%o' 0x$$c); \ done; \ done > $@ -- To view, visit https://review.coreboot.org/c/coreboot/+/35867 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95b414d959e5cd4479fcf100adcf390562032c68 Gerrit-Change-Number: 35867 Gerrit-PatchSet: 1 Gerrit-Owner: greg(a)unrelenting.technology Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: greg(a)unrelenting.technology Gerrit-MessageType: newchange

5 5

Change in coreboot[master]: ec/google/chromeec: fix format security warning
by Name of user not set (Code Review) 09 Oct '19

09 Oct '19

greg(a)unrelenting.technology has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35866 ) Change subject: ec/google/chromeec: fix format security warning ...................................................................... ec/google/chromeec: fix format security warning Change-Id: I7a7bcb56523d595e8d4f32849aac53d66d416a12 Signed-off-by: Greg V <greg(a)unrelenting.technology> --- M src/ec/google/chromeec/ec.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/35866/1 diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 1b0f7ee..7c294b6 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -1063,7 +1063,7 @@ if ((cmd_resp.ec_reset_flags & (1 << flag)) != 0) { if (flag_count) printk(BIOS_DEBUG, " | "); - printk(BIOS_DEBUG, reset_flag_strings[flag]); + printk(BIOS_DEBUG, "%s", reset_flag_strings[flag]); flag_count++; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/35866 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a7bcb56523d595e8d4f32849aac53d66d416a12 Gerrit-Change-Number: 35866 Gerrit-PatchSet: 1 Gerrit-Owner: greg(a)unrelenting.technology Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: drivers/spi: ignore -Wvla on clang too
by Name of user not set (Code Review) 09 Oct '19

09 Oct '19

greg(a)unrelenting.technology has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35865 ) Change subject: drivers/spi: ignore -Wvla on clang too ...................................................................... drivers/spi: ignore -Wvla on clang too Change-Id: I99bc6877680b32f2bae78437ab0482baa65496d8 Signed-off-by: Greg V <greg(a)unrelenting.technology> --- M src/drivers/spi/spi_flash.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/35865/1 diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 5dbe1f4..9dfecea 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -100,8 +100,8 @@ #pragma GCC diagnostic push #if defined(__GNUC__) && !defined(__clang__) #pragma GCC diagnostic ignored "-Wstack-usage=" -#pragma GCC diagnostic ignored "-Wvla" #endif +#pragma GCC diagnostic ignored "-Wvla" int spi_flash_cmd_write(const struct spi_slave *spi, const u8 *cmd, size_t cmd_len, const void *data, size_t data_len) { -- To view, visit https://review.coreboot.org/c/coreboot/+/35865 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I99bc6877680b32f2bae78437ab0482baa65496d8 Gerrit-Change-Number: 35865 Gerrit-PatchSet: 1 Gerrit-Owner: greg(a)unrelenting.technology Gerrit-MessageType: newchange

4 3

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coreboot-gerrit October 2019