coreboot-gerrit October 2019

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Change in coreboot[master]: mb/google/glados: port to FSP 2.0
by Michael Niewöhner (Code Review) 10 Oct '19

10 Oct '19

Hello Patrick Rudolph, Matt DeVillier, Paul Menzel, build bot (Jenkins), Nico Huber, Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35921 to look at the new patch set (#4). Change subject: mb/google/glados: port to FSP 2.0 ...................................................................... mb/google/glados: port to FSP 2.0 This patch is part of the patch series to drop support for FSP 1.1 in soc/intel/skylake. The following modifications have been done to migrate the board(s) from FSP 1.1 to FSP 2.0: - remove deprecated devicetree VR_RING domain (only 4 domains in FSP 2.0) - switch to using the FSP default VBT TODO: - testing Change-Id: Id747ef484dfdcb2d346f817976f52073912468d0 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/glados/Kconfig M src/mainboard/google/glados/ramstage.c M src/mainboard/google/glados/romstage.c M src/mainboard/google/glados/spd/spd.c M src/mainboard/google/glados/spd/spd_util.h D src/mainboard/google/glados/variants/asuka/data.vbt M src/mainboard/google/glados/variants/asuka/devicetree.cb M src/mainboard/google/glados/variants/asuka/variant.c M src/mainboard/google/glados/variants/baseboard/include/baseboard/variant.h D src/mainboard/google/glados/variants/caroline/data.vbt M src/mainboard/google/glados/variants/caroline/devicetree.cb M src/mainboard/google/glados/variants/caroline/variant.c D src/mainboard/google/glados/variants/cave/data.vbt M src/mainboard/google/glados/variants/cave/devicetree.cb M src/mainboard/google/glados/variants/cave/variant.c D src/mainboard/google/glados/variants/chell/data.vbt M src/mainboard/google/glados/variants/chell/devicetree.cb M src/mainboard/google/glados/variants/chell/variant.c M src/mainboard/google/glados/variants/glados/devicetree.cb M src/mainboard/google/glados/variants/glados/variant.c D src/mainboard/google/glados/variants/lars/data.vbt M src/mainboard/google/glados/variants/lars/devicetree.cb M src/mainboard/google/glados/variants/lars/variant.c D src/mainboard/google/glados/variants/sentry/data.vbt M src/mainboard/google/glados/variants/sentry/devicetree.cb M src/mainboard/google/glados/variants/sentry/variant.c 26 files changed, 196 insertions(+), 308 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/35921/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/35921 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id747ef484dfdcb2d346f817976f52073912468d0 Gerrit-Change-Number: 35921 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/supermicro: Add Supermicro X9SCL+-F
by Christoph Pomaska (Code Review) 10 Oct '19

10 Oct '19

Christoph Pomaska has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34873 ) Change subject: mb/supermicro: Add Supermicro X9SCL+-F ...................................................................... mb/supermicro: Add Supermicro X9SCL+-F This port is not working correctly at the moment as coreboot gets stuck in or before postCAR. What works: - RAMinit - Serial (RS232) What does not work: - basically everything else Further notes: - To prevent problems its recommended to always flash after powering the power supply, disable and reenable power supply before flashing. Change-Id: I9b4bf0f3caa2533b416637ce5baf4c4aad2ad94a Signed-off-by: Christoph Pomaska <c.pomaska(a)hosting.de> --- A src/mainboard/supermicro/x9scl-f/Kconfig A src/mainboard/supermicro/x9scl-f/Kconfig.name A src/mainboard/supermicro/x9scl-f/Makefile.inc A src/mainboard/supermicro/x9scl-f/acpi/ec.asl A src/mainboard/supermicro/x9scl-f/acpi/platform.asl A src/mainboard/supermicro/x9scl-f/acpi/superio.asl A src/mainboard/supermicro/x9scl-f/acpi_tables.c A src/mainboard/supermicro/x9scl-f/board_info.txt A src/mainboard/supermicro/x9scl-f/devicetree.cb A src/mainboard/supermicro/x9scl-f/dsdt.asl A src/mainboard/supermicro/x9scl-f/gpio.c A src/mainboard/supermicro/x9scl-f/hda_verb.c A src/mainboard/supermicro/x9scl-f/mainboard.c A src/mainboard/supermicro/x9scl-f/romstage.c 14 files changed, 618 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/34873/1 diff --git a/src/mainboard/supermicro/x9scl-f/Kconfig b/src/mainboard/supermicro/x9scl-f/Kconfig new file mode 100644 index 0000000..f4bead2 --- /dev/null +++ b/src/mainboard/supermicro/x9scl-f/Kconfig @@ -0,0 +1,64 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Hosting.de GmbH +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## + +if BOARD_SUPERMICRO_X9SCL_PLUS_F + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select USE_NATIVE_RAMINIT + select SUPERIO_NUVOTON_NCT6776 + select SUPERIO_NUVOTON_NCT6776_COM_A + select SUPERIO_NUVOTON_WPCM450 + select MAINBOARD_USES_IFD_GBE_REGION + select NO_STAGE_CACHE + +config MAINBOARD_DIR + string + default "supermicro/x9scl-f" + +config MAINBOARD_PART_NUMBER + string + default "X9SCL+-F" + +config DRAM_RESET_GATE_GPIO # FIXME: check this + int + default 60 + +config MAX_CPUS + int + default 8 + +config VGA_BIOS_FILE + string + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/vgabios.bin" + +config VGA_BIOS_ID + string + depends on VGA_BIOS + default "10sb,0532" + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/supermicro/x9scl-f/Kconfig.name b/src/mainboard/supermicro/x9scl-f/Kconfig.name new file mode 100644 index 0000000..fd73657 --- /dev/null +++ b/src/mainboard/supermicro/x9scl-f/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_SUPERMICRO_X9SCL_PLUS_F + bool "X9SCL+-F" diff --git a/src/mainboard/supermicro/x9scl-f/Makefile.inc b/src/mainboard/supermicro/x9scl-f/Makefile.inc new file mode 100644 index 0000000..3dae61e --- /dev/null +++ b/src/mainboard/supermicro/x9scl-f/Makefile.inc @@ -0,0 +1 @@ +romstage-y += gpio.c diff --git a/src/mainboard/supermicro/x9scl-f/acpi/ec.asl b/src/mainboard/supermicro/x9scl-f/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/supermicro/x9scl-f/acpi/ec.asl diff --git a/src/mainboard/supermicro/x9scl-f/acpi/platform.asl b/src/mainboard/supermicro/x9scl-f/acpi/platform.asl new file mode 100644 index 0000000..b269aa7 --- /dev/null +++ b/src/mainboard/supermicro/x9scl-f/acpi/platform.asl @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Hosting.de GmbH + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ +} diff --git a/src/mainboard/supermicro/x9scl-f/acpi/superio.asl b/src/mainboard/supermicro/x9scl-f/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/supermicro/x9scl-f/acpi/superio.asl diff --git a/src/mainboard/supermicro/x9scl-f/acpi_tables.c b/src/mainboard/supermicro/x9scl-f/acpi_tables.c new file mode 100644 index 0000000..315379d --- /dev/null +++ b/src/mainboard/supermicro/x9scl-f/acpi_tables.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2019 Hosting.de GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +/* FIXME: check this function. */ +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/supermicro/x9scl-f/board_info.txt b/src/mainboard/supermicro/x9scl-f/board_info.txt new file mode 100644 index 0000000..a14680e --- /dev/null +++ b/src/mainboard/supermicro/x9scl-f/board_info.txt @@ -0,0 +1,7 @@ +Category: server +Board URL: +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2011 diff --git a/src/mainboard/supermicro/x9scl-f/devicetree.cb b/src/mainboard/supermicro/x9scl-f/devicetree.cb new file mode 100644 index 0000000..d12f2e6f88 --- /dev/null +++ b/src/mainboard/supermicro/x9scl-f/devicetree.cb @@ -0,0 +1,107 @@ +chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gfx.link_frequency_270_mhz" = "0" + register "gfx.ndid" = "3" + register "gfx.use_spread_spectrum_clock" = "0" + register "gpu_cpu_backlight" = "0x00000000" + register "gpu_dp_b_hotplug" = "0" + register "gpu_dp_c_hotplug" = "0" + register "gpu_dp_d_hotplug" = "0" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "0" + register "gpu_panel_power_backlight_on_delay" = "0" + register "gpu_panel_power_cycle_delay" = "0" + register "gpu_panel_power_down_delay" = "0" + register "gpu_panel_power_up_delay" = "0" + register "gpu_pch_backlight" = "0x00000000" + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax # FIXME: check all registers + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on + end + device lapic 0xacac off + end + end + end + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x00fc0a01" + register "gen2_dec" = "0x00fc1641" + register "gen3_dec" = "0x00040ca1" + register "gen4_dec" = "0x001c03e1" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x3f" + register "spi_lvscc" = "0x0" + register "spi_uvscc" = "0x0" + device pci 16.0 off # Management Engine Interface 1 + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 off # Intel Gigabit Ethernet + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x15d9 0x0624 + end + device pci 1b.0 off # High Definition Audio + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x15d9 0x0624 + end + device pci 1c.1 off # PCIe Port #2 + end + device pci 1c.2 off # PCIe Port #3 + end + device pci 1c.3 off # PCIe Port #4 + end + device pci 1c.4 on # PCIe Port #5 + subsystemid 0x15d9 0x0624 + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 on # PCIe Port #7 + subsystemid 0x15d9 0x0624 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x15d9 0x0624 + end + device pci 1e.0 on # PCI bridge + subsystemid 0x15d9 0x0624 + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x15d9 0x0624 + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x15d9 0x0624 + end + device pci 1f.3 on # SMBus + subsystemid 0x15d9 0x0624 + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x15d9 0x0624 + end + device pci 01.0 off # PCIe Bridge for discrete graphics + end + device pci 02.0 off # Internal graphics + end + end +end diff --git a/src/mainboard/supermicro/x9scl-f/dsdt.asl b/src/mainboard/supermicro/x9scl-f/dsdt.asl new file mode 100644 index 0000000..1f86a1d --- /dev/null +++ b/src/mainboard/supermicro/x9scl-f/dsdt.asl @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Hosting.de GmbH + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI 2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + /* Some generic macros */ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/supermicro/x9scl-f/gpio.c b/src/mainboard/supermicro/x9scl-f/gpio.c new file mode 100644 index 0000000..8567313 --- /dev/null +++ b/src/mainboard/supermicro/x9scl-f/gpio.c @@ -0,0 +1,198 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2019 Hosting.de GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_OUTPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio7 = GPIO_LEVEL_HIGH, + .gpio11 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_INVERT, + .gpio1 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/supermicro/x9scl-f/hda_verb.c b/src/mainboard/supermicro/x9scl-f/hda_verb.c new file mode 100644 index 0000000..a5b6e19 --- /dev/null +++ b/src/mainboard/supermicro/x9scl-f/hda_verb.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> + * Copyright (C) 2019 Hosting.de GmbH + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = {}; +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/supermicro/x9scl-f/mainboard.c b/src/mainboard/supermicro/x9scl-f/mainboard.c new file mode 100644 index 0000000..7992796 --- /dev/null +++ b/src/mainboard/supermicro/x9scl-f/mainboard.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Hosting.de GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> + +static void mainboard_enable(struct device *dev) +{ + /* FIXME: fix those values*/ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/supermicro/x9scl-f/romstage.c b/src/mainboard/supermicro/x9scl-f/romstage.c new file mode 100644 index 0000000..426d1c9 --- /dev/null +++ b/src/mainboard/supermicro/x9scl-f/romstage.c @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2019 Hosting.de GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <device/mmio.h> +#include <device/pci_ops.h> +#include <device/pnp_ops.h> +#include <console/console.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6776/nct6776.h> + +#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) + +void pch_enable_lpc(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x370f); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); +} + +void mainboard_rcba_config(void) +{ +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/34873 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b4bf0f3caa2533b416637ce5baf4c4aad2ad94a Gerrit-Change-Number: 34873 Gerrit-PatchSet: 1 Gerrit-Owner: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-MessageType: newchange

2 8

Change in coreboot[master]: nb/intel/pineview/Kconfig: Remove romcc leftover
by Arthur Heymans (Code Review) 10 Oct '19

10 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35948 ) Change subject: nb/intel/pineview/Kconfig: Remove romcc leftover ...................................................................... nb/intel/pineview/Kconfig: Remove romcc leftover This is unused since C_ENVIRONMENT_BOOTBLOCK is used. Change-Id: Id5af41e455d211eba89cfeb625f4c728b4145da7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/pineview/Kconfig 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/35948/1 diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index d1d776b..edf4f23 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -30,10 +30,6 @@ select PARALLEL_MP select C_ENVIRONMENT_BOOTBLOCK -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "northbridge/intel/pineview/bootblock.c" - config VGA_BIOS_ID string default "8086,a001" -- To view, visit https://review.coreboot.org/c/coreboot/+/35948 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5af41e455d211eba89cfeb625f4c728b4145da7 Gerrit-Change-Number: 35948 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

5 5

Change in coreboot[master]: util/inteltool: set num of cores depends on CPUID
by Patrick Rudolph (Code Review) 10 Oct '19

10 Oct '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35918 ) Change subject: util/inteltool: set num of cores depends on CPUID ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/35918/2/util/inteltool/cpu.c File util/inteltool/cpu.c: https://review.coreboot.org/c/coreboot/+/35918/2/util/inteltool/cpu.c@2259 PS2, Line 2259: unsigned int max_core_limit = cpu->max_core_limit ? cpu->max_core_limit : 8; why don't you detect the current cpu core/thread count of the running system? -- To view, visit https://review.coreboot.org/c/coreboot/+/35918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a4408f286f245d1d109adf98f430ad7a6b1b2fa Gerrit-Change-Number: 35918 Gerrit-PatchSet: 2 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 10 Oct 2019 14:07:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel: sgx: get rid of UEFI-style usage of global variable
by Michael Niewöhner (Code Review) 10 Oct '19

10 Oct '19

Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35882 ) Change subject: soc/intel: sgx: get rid of UEFI-style usage of global variable ...................................................................... soc/intel: sgx: get rid of UEFI-style usage of global variable Rework SGX enable status in a clean way without using a global variable. Change-Id: Ida6458eb46708df8fd238122aed41b57ca48c15b Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/apollolake/cpu.c M src/soc/intel/common/block/include/intelblocks/sgx.h M src/soc/intel/common/block/sgx/sgx.c M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/cpu.c 5 files changed, 19 insertions(+), 59 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/35882/1 diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 3349627..8056777 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -72,10 +72,12 @@ void soc_core_init(struct device *cpu) { + config_t *conf = config_of_soc(); + /* Clear out pending MCEs */ /* TODO(adurbin): Some of these banks are core vs package scope. For now every CPU clears every bank. */ - if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX) || + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX && conf->sgx_enable) || acpi_get_sleep_type() == ACPI_S5) mca_configure(); @@ -89,7 +91,7 @@ enable_pm_timer_emulation(); /* Configure Core PRMRR for SGX. */ - if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX)) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX) && conf->sgx_enable) prmrr_core_configure(); /* Set Max Non-Turbo ratio if RAPL is disabled. */ @@ -253,9 +255,11 @@ static void post_mp_init(void) { + config_t *conf = config_of_soc(); + smm_southbridge_enable(PWRBTN_EN | GBL_EN); - if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX)) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX) && conf->sgx_enable) mp_run_on_all_cpus(sgx_configure, NULL); } @@ -293,11 +297,3 @@ /* Do nothing because MCHECK while loading microcode and enabling * IA untrusted mode takes care of necessary locking */ } - -int soc_fill_sgx_param(struct sgx_param *sgx_param) -{ - config_t *conf = config_of_soc(); - - sgx_param->enable = conf->sgx_enable; - return 0; -} diff --git a/src/soc/intel/common/block/include/intelblocks/sgx.h b/src/soc/intel/common/block/include/intelblocks/sgx.h index 502483f..693dd20 100644 --- a/src/soc/intel/common/block/include/intelblocks/sgx.h +++ b/src/soc/intel/common/block/include/intelblocks/sgx.h @@ -18,10 +18,6 @@ #include <soc/nvs.h> -struct sgx_param { - uint8_t enable; -}; - /* * Lock SGX memory. * CPU specific code needs to provide the implementation. @@ -40,10 +36,6 @@ */ void sgx_configure(void *unused); -/* SOC specific API to get SGX params. - * returns 0, if able to get SGX params; otherwise returns -1 */ -int soc_fill_sgx_param(struct sgx_param *sgx_param); - /* Fill GNVS data with SGX status, EPC base and length */ void sgx_fill_gnvs(global_nvs_t *gnvs); diff --git a/src/soc/intel/common/block/sgx/sgx.c b/src/soc/intel/common/block/sgx/sgx.c index 60714d9..0edf50f 100644 --- a/src/soc/intel/common/block/sgx/sgx.c +++ b/src/soc/intel/common/block/sgx/sgx.c @@ -25,9 +25,6 @@ #include <soc/pci_devs.h> #include <string.h> -static bool sgx_param_valid; -static struct sgx_param g_sgx_param; - static inline uint64_t sgx_resource(uint32_t low, uint32_t high) { uint64_t val; @@ -36,28 +33,6 @@ return val; } -static const struct sgx_param *get_sgx_param(void) -{ - if (sgx_param_valid) - return &g_sgx_param; - - memset(&g_sgx_param, 0, sizeof(g_sgx_param)); - if (soc_fill_sgx_param(&g_sgx_param) < 0) { - printk(BIOS_ERR, "SGX : Failed to get soc sgx param\n"); - return NULL; - } - sgx_param_valid = true; - printk(BIOS_INFO, "SGX : param.enable = %d\n", g_sgx_param.enable); - - return &g_sgx_param; -} - -static int soc_sgx_enabled(void) -{ - const struct sgx_param *sgx_param = get_sgx_param(); - return sgx_param ? sgx_param->enable : 0; -} - static int is_sgx_supported(void) { struct cpuid_result cpuid_regs; @@ -79,7 +54,7 @@ } prmrr_base, prmrr_mask; msr_t msr; - if (!soc_sgx_enabled() || !is_sgx_supported()) + if (!is_sgx_supported()) return; msr = rdmsr(MSR_PRMRR_PHYS_MASK); @@ -204,7 +179,7 @@ { const void *microcode_patch = intel_mp_current_microcode(); - if (!soc_sgx_enabled() || !is_sgx_supported() || !is_prmrr_set()) { + if (!is_sgx_supported() || !is_prmrr_set()) { printk(BIOS_ERR, "SGX: pre-conditions not met\n"); return; } @@ -234,9 +209,9 @@ { struct cpuid_result cpuid_regs; - if (!soc_sgx_enabled() || !is_sgx_supported()) { + if (!is_sgx_supported()) { printk(BIOS_DEBUG, - "SGX: not enabled or not supported. skip gnvs fill\n"); + "SGX: not supported. skip gnvs fill\n"); return; } diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index de37341..69593b4 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -205,7 +205,7 @@ gnvs->u2we = config->usb2_wake_enable_bitmap; gnvs->u3we = config->usb3_wake_enable_bitmap; - if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX)) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX) && config->sgx_enable) sgx_fill_gnvs(gnvs); } diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 5424c91..8f93e31 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -423,6 +423,8 @@ /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { + config_t *conf = config_of_soc(); + /* Clear out pending MCEs */ /* TODO(adurbin): This should only be done on a cold boot. Also, some * of these banks are core vs package scope. For now every CPU clears @@ -455,7 +457,8 @@ enable_turbo(); /* Configure Core PRMRR for SGX. */ - prmrr_core_configure(); + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX) && conf->sgx_enable) + prmrr_core_configure(); } static void per_cpu_smm_trigger(void) @@ -477,6 +480,7 @@ static void post_mp_init(void) { int ret = 0; + config_t *conf = config_of_soc(); /* Set Max Ratio */ cpu_set_max_ratio(); @@ -493,7 +497,8 @@ ret |= mp_run_on_all_cpus(vmx_configure, NULL); - ret |= mp_run_on_all_cpus(sgx_configure, NULL); + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX) && conf->sgx_enable) + ret |= mp_run_on_all_cpus(sgx_configure, NULL); ret |= mp_run_on_all_cpus(fc_lock_configure, NULL); @@ -559,11 +564,3 @@ wrmsr(MSR_LT_LOCK_MEMORY, msr); } } - -int soc_fill_sgx_param(struct sgx_param *sgx_param) -{ - config_t *conf = config_of_soc(); - - sgx_param->enable = conf->sgx_enable; - return 0; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/35882 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida6458eb46708df8fd238122aed41b57ca48c15b Gerrit-Change-Number: 35882 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-MessageType: newchange

3 11

Change in coreboot[master]: mb/{ibase/mb899,kontron/986lcd-m}: Use pnp_write_hwm5_index function
by HAOUAS Elyes (Code Review) 10 Oct '19

10 Oct '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35901 ) Change subject: mb/{ibase/mb899,kontron/986lcd-m}: Use pnp_write_hwm5_index function ...................................................................... mb/{ibase/mb899,kontron/986lcd-m}: Use pnp_write_hwm5_index function Change-Id: If30a17d053da8f0758085fc36469b564d46049cd Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/ibase/mb899/superio_hwm.c M src/mainboard/kontron/986lcd-m/mainboard.c 2 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/35901/1 diff --git a/src/mainboard/ibase/mb899/superio_hwm.c b/src/mainboard/ibase/mb899/superio_hwm.c index 7fb45f9..fd4ac47 100644 --- a/src/mainboard/ibase/mb899/superio_hwm.c +++ b/src/mainboard/ibase/mb899/superio_hwm.c @@ -19,6 +19,7 @@ #include <console/console.h> #include <device/device.h> #include <pc80/mc146818rtc.h> +#include <superio/hwm5_conf.h> #include "superio_hwm.h" @@ -35,8 +36,7 @@ static void hwm_write(u8 reg, u8 value) { - outb(reg, HWM_BASE + 0x05); - outb(value, HWM_BASE + 0x06); + pnp_write_hwm5_index(HWM_BASE, reg, value) } static void hwm_bank(u8 bank) diff --git a/src/mainboard/kontron/986lcd-m/mainboard.c b/src/mainboard/kontron/986lcd-m/mainboard.c index 85b704e..ed175c4 100644 --- a/src/mainboard/kontron/986lcd-m/mainboard.c +++ b/src/mainboard/kontron/986lcd-m/mainboard.c @@ -21,6 +21,7 @@ #include <drivers/intel/gma/int15.h> #include <pc80/mc146818rtc.h> #include <arch/io.h> +#include <superio/hwm5_conf.h> /* Hardware Monitor */ @@ -28,8 +29,7 @@ static void hwm_write(u8 reg, u8 value) { - outb(reg, hwm_base + 0x05); - outb(value, hwm_base + 0x06); + pnp_write_hwm5_index(hwm_base, reg, value) } static void hwm_bank(u8 bank) -- To view, visit https://review.coreboot.org/c/coreboot/+/35901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If30a17d053da8f0758085fc36469b564d46049cd Gerrit-Change-Number: 35901 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: soc/intel: Add function to set DPR
by Patrick Rudolph (Code Review) 10 Oct '19

10 Oct '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33417 ) Change subject: soc/intel: Add function to set DPR ...................................................................... Patch Set 9: (1 comment) https://review.coreboot.org/c/coreboot/+/33417/7/src/soc/intel/fsp_broadwel… File src/soc/intel/fsp_broadwell_de/ramstage.c: https://review.coreboot.org/c/coreboot/+/33417/7/src/soc/intel/fsp_broadwel… PS7, Line 31: #include <soc/broadwell_de.h> > > Feel free to address those conflicts, but keep in mind that BroadwellDE is a server platform, whil […] The function prototypes are the same, so it doesn't matter which header is used. As SOC_INTEL_COMMON_BLOCK_SA isn't used on fsp_broadwell_de there's no problem. -- To view, visit https://review.coreboot.org/c/coreboot/+/33417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43d2b50a7a6bb41146be99e645cd2ac6a6c9f703 Gerrit-Change-Number: 33417 Gerrit-PatchSet: 9 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 10 Oct 2019 12:36:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: build: Mark bootblock files on x86 as IBB
by Patrick Rudolph (Code Review) 10 Oct '19

10 Oct '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31497 ) Change subject: build: Mark bootblock files on x86 as IBB ...................................................................... Patch Set 14: (1 comment) https://review.coreboot.org/c/coreboot/+/31497/13//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/31497/13//COMMIT_MSG@10 PS13, Line 10: be used > That is duplicated. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/31497 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I83313f035e7fb7e1eb484b323862522e28cb73d4 Gerrit-Change-Number: 31497 Gerrit-PatchSet: 14 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Amol N Sukerkar <amol.n.sukerkar(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kai Michaelis <kai.michaelis(a)9elements.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Thu, 10 Oct 2019 12:33:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: util/cbfstool: Add optional argument ibb
by Patrick Rudolph (Code Review) 10 Oct '19

10 Oct '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29744 ) Change subject: util/cbfstool: Add optional argument ibb ...................................................................... Patch Set 21: (3 comments) https://review.coreboot.org/c/coreboot/+/29744/20/util/cbfstool/cbfstool.c File util/cbfstool/cbfstool.c: https://review.coreboot.org/c/coreboot/+/29744/20/util/cbfstool/cbfstool.c@… PS20, Line 453: const bool ibb) > Let's use param.ibb directly instead of adding more cruft to this function signature. Done https://review.coreboot.org/c/coreboot/+/29744/20/util/cbfstool/cbfstool.c@… PS20, Line 548: ibb > param. […] Done https://review.coreboot.org/c/coreboot/+/29744/20/util/cbfstool/cbfstool.c@… PS20, Line 1279: O > Bikeshedding time: 'O' seems like an awkward choice. […] Removed. only --ibb will work for now. -- To view, visit https://review.coreboot.org/c/coreboot/+/29744 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb4857c894b9ee1edc464c0a1216cdda29937bbd Gerrit-Change-Number: 29744 Gerrit-PatchSet: 21 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Amol N Sukerkar <amol.n.sukerkar(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kai Michaelis <kai.michaelis(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 10 Oct 2019 12:32:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: David Hendricks <david.hendricks(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: build: Mark bootblock files on x86 as IBB
by Patrick Rudolph (Code Review) 10 Oct '19

10 Oct '19

Hello Patrick Rudolph, Aaron Durbin, Julius Werner, Subrata Banik, build bot (Jenkins), Kai Michaelis, Patrick Georgi, Amol N Sukerkar, Roy Wen, Huang Jin, Lee Leahy, David Hendricks, Christian Walter, Philipp Deppenwiese, Martin Roth, Jens Drenhaus, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/31497 to look at the new patch set (#14). Change subject: build: Mark bootblock files on x86 as IBB ...................................................................... build: Mark bootblock files on x86 as IBB * Add cbfsoption --ibb to mark files as IBB * Will be used by "Legacy FIT TXT" boot Change-Id: I83313f035e7fb7e1eb484b323862522e28cb73d4 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Makefile.inc M src/drivers/intel/fsp1_0/Makefile.inc M src/drivers/intel/fsp1_1/Makefile.inc M src/drivers/intel/fsp2_0/Makefile.inc M src/security/intel/txt/Makefile.inc M src/security/vboot/Makefile.inc 6 files changed, 33 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/31497/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/31497 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I83313f035e7fb7e1eb484b323862522e28cb73d4 Gerrit-Change-Number: 31497 Gerrit-PatchSet: 14 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Amol N Sukerkar <amol.n.sukerkar(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kai Michaelis <kai.michaelis(a)9elements.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit October 2019