coreboot-gerrit October 2019

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Change in coreboot[master]: build: Mark bootblock files on x86 as IBB
by Philipp Deppenwiese (Code Review) 11 Oct '19

11 Oct '19

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31497 ) Change subject: build: Mark bootblock files on x86 as IBB ...................................................................... Patch Set 14: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31497 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I83313f035e7fb7e1eb484b323862522e28cb73d4 Gerrit-Change-Number: 31497 Gerrit-PatchSet: 14 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Amol N Sukerkar <amol.n.sukerkar(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kai Michaelis <kai.michaelis(a)9elements.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Fri, 11 Oct 2019 16:35:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: util/cbfstool: Add optional argument ibb
by Philipp Deppenwiese (Code Review) 11 Oct '19

11 Oct '19

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29744 ) Change subject: util/cbfstool: Add optional argument ibb ...................................................................... Patch Set 22: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29744 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb4857c894b9ee1edc464c0a1216cdda29937bbd Gerrit-Change-Number: 29744 Gerrit-PatchSet: 22 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Amol N Sukerkar <amol.n.sukerkar(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kai Michaelis <kai.michaelis(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 11 Oct 2019 16:34:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/purism: Don't select NO_POST
by Nico Huber (Code Review) 11 Oct '19

11 Oct '19

Hello Matt DeVillier, Benjamin Doron, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/35956 to review the following change. Change subject: mb/purism: Don't select NO_POST ...................................................................... mb/purism: Don't select NO_POST The NO_POST option covers more than classical port 80 output, hence selecting it seems wrong in this case. The default is still rather user pratonizing, but let's keep it. As a side effect, this fixes the ability to override the default for NO_POST which Kconfig rejected while these boards selected it. (Seems like a bug in Kconfig, though.) Change-Id: I896b08812b1aa6ce249d7acc8073ebcc0f72eace Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/mainboard/purism/librem_bdw/Kconfig M src/mainboard/purism/librem_skl/Kconfig 2 files changed, 7 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/35956/1 diff --git a/src/mainboard/purism/librem_bdw/Kconfig b/src/mainboard/purism/librem_bdw/Kconfig index 7f7519c..9424a7e 100644 --- a/src/mainboard/purism/librem_bdw/Kconfig +++ b/src/mainboard/purism/librem_bdw/Kconfig @@ -7,7 +7,6 @@ select HAVE_ACPI_TABLES select INTEL_INT15 select SOC_INTEL_BROADWELL - select NO_POST # This platform does not have any way to see POST codes if BOARD_PURISM_BASEBOARD_LIBREM_BDW @@ -73,5 +72,8 @@ default "8086,1616" if BOARD_PURISM_LIBREM13_V1 default "8086,162b" if BOARD_PURISM_LIBREM15_V2 +# This platform has limited means to display POST codes +config NO_POST + default y endif diff --git a/src/mainboard/purism/librem_skl/Kconfig b/src/mainboard/purism/librem_skl/Kconfig index ecde9e4..cc0e98a 100644 --- a/src/mainboard/purism/librem_skl/Kconfig +++ b/src/mainboard/purism/librem_skl/Kconfig @@ -10,7 +10,6 @@ select MAINBOARD_USES_FSP2_0 select SPD_READ_BY_WORD select MAINBOARD_HAS_LPC_TPM - select NO_POST # This platform does not have any way to see POST codes if BOARD_PURISM_BASEBOARD_LIBREM_SKL @@ -68,4 +67,8 @@ hex default 0xe00000 +# This platform has limited means to display POST codes +config NO_POST + default y + endif -- To view, visit https://review.coreboot.org/c/coreboot/+/35956 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I896b08812b1aa6ce249d7acc8073ebcc0f72eace Gerrit-Change-Number: 35956 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/braswell/chip.c: Configure LPSS devices in correct mode
by Aaron Durbin (Code Review) 11 Oct '19

11 Oct '19

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29284 ) Change subject: soc/intel/braswell/chip.c: Configure LPSS devices in correct mode ...................................................................... Patch Set 11: (1 comment) https://review.coreboot.org/c/coreboot/+/29284/11//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/29284/11//COMMIT_MSG@11 PS11, Line 11: ACPI mode, functions > 1 are not available on the PCI bus, even pcdEnableXXXXX is set to Is this actually the case or that function 0 disappears and that w/o a function 0 probing doesn't occur because it's against PCI standard? My recollection was the latter. And below your further comments suggest that as well. I don't think the devices disappear off the bus. -- To view, visit https://review.coreboot.org/c/coreboot/+/29284 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie271d8cb9f30f0c0ba538f1530cfb82f1306fea8 Gerrit-Change-Number: 29284 Gerrit-PatchSet: 11 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Wim Vervoorn Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Fri, 11 Oct 2019 13:55:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation/mainboard/facebook: Add rev 1.3
by Paul Menzel (Code Review) 11 Oct '19

11 Oct '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35955 ) Change subject: Documentation/mainboard/facebook: Add rev 1.3 ...................................................................... Patch Set 1: Code-Review+1 (2 comments) https://review.coreboot.org/c/coreboot/+/35955/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/35955/1//COMMIT_MSG@9 PS1, Line 9: Added Add https://review.coreboot.org/c/coreboot/+/35955/1//COMMIT_MSG@12 PS1, Line 12: Please fix typos in separate commits in the future. -- To view, visit https://review.coreboot.org/c/coreboot/+/35955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaba6f28368e2e4ca412122b5fa28ed93c705f4df Gerrit-Change-Number: 35955 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Wim Vervoorn Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 11 Oct 2019 13:10:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: sb/intel/i82801gx: Move CIR init to a common place
by Arthur Heymans (Code Review) 11 Oct '19

11 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35795 ) Change subject: sb/intel/i82801gx: Move CIR init to a common place ...................................................................... sb/intel/i82801gx: Move CIR init to a common place Change-Id: Ia10c050785170fc743f7aef918f4849dbdd6840e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/apple/macbook21/romstage.c M src/mainboard/asrock/g41c-gs/romstage.c M src/mainboard/asus/p5gc-mx/romstage.c M src/mainboard/asus/p5qpl-am/romstage.c M src/mainboard/foxconn/g41s-k/romstage.c M src/mainboard/getac/p470/romstage.c M src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c M src/mainboard/gigabyte/ga-g41m-es2l/romstage.c M src/mainboard/ibase/mb899/romstage.c M src/mainboard/intel/d945gclf/romstage.c M src/mainboard/intel/dg41wv/romstage.c M src/mainboard/kontron/986lcd-m/romstage.c M src/mainboard/lenovo/t60/romstage.c M src/mainboard/lenovo/thinkcentre_a58/romstage.c M src/mainboard/lenovo/x60/romstage.c M src/mainboard/lenovo/z61t/romstage.c M src/mainboard/roda/rk886ex/romstage.c M src/northbridge/intel/pineview/early_init.c M src/southbridge/intel/bd82x6x/pch.c M src/southbridge/intel/i82801gx/Makefile.inc A src/southbridge/intel/i82801gx/early_cir.c M src/southbridge/intel/i82801gx/i82801gx.h 22 files changed, 77 insertions(+), 324 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/35795/1 diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index 32a7871..89db57e 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -195,31 +195,7 @@ reg32 |= (1 << 31) | (1 << 27); pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); - RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(GCS); - reg32 |= (1 << 6); - RCBA32(GCS) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - /* next step only on ich7m b0 and later: */ - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; + ich7_setup_cir(); } void mainboard_romstage_entry(void) diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c index 0228499..b3d1777 100644 --- a/src/mainboard/asrock/g41c-gs/romstage.c +++ b/src/mainboard/asrock/g41c-gs/romstage.c @@ -65,11 +65,7 @@ RCBA8(OIC) = 0x03; RCBA8(OIC); - reg32 = RCBA32(GCS); - reg32 |= (1 << 5); - RCBA32(GCS) = reg32; - - RCBA32(CG) = 0x00000001; + ich7_setup_cir(); } static void ich7_enable_lpc(void) diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c index 632ef05..20a2b56 100644 --- a/src/mainboard/asus/p5gc-mx/romstage.c +++ b/src/mainboard/asus/p5gc-mx/romstage.c @@ -145,31 +145,7 @@ reg32 |= (1 << 31) | (1 << 27); pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); - RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030509; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(GCS); - reg32 |= (1 << 6); - RCBA32(GCS) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - // next step only on ich7m b0 and later: - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; + ich7_setup_cir(); } void mainboard_romstage_entry(void) diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c index dc589a5..dd48e59 100644 --- a/src/mainboard/asus/p5qpl-am/romstage.c +++ b/src/mainboard/asus/p5qpl-am/romstage.c @@ -142,10 +142,7 @@ RCBA8(0x31ff) = 0x03; RCBA8(0x31ff); - reg32 = RCBA32(GCS); - reg32 |= (1 << 5); - RCBA32(GCS) = reg32; - RCBA32(CG) = 0x00000001; + ich7_setup_cir(); } static void ich7_enable_lpc(void) diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/romstage.c index a22c90c..0bfbbfe 100644 --- a/src/mainboard/foxconn/g41s-k/romstage.c +++ b/src/mainboard/foxconn/g41s-k/romstage.c @@ -67,7 +67,8 @@ RCBA8(OIC); RCBA32(FD) |= FD_INTLAN; - RCBA32(CG) = 0x00000001; + + ich7_setup_cir(); } static void ich7_enable_lpc(void) diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index a7c64bd..0b7aea4 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -204,31 +204,7 @@ reg32 |= (1 << 31) | (1 << 27); pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); - RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(0x3410); - reg32 |= (1 << 6); - RCBA32(0x3410) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - // next step only on ich7m b0 and later: - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; + ich7_setup_cir(); } void mainboard_romstage_entry(void) diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c index eaf05a2..65750cf 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c @@ -107,31 +107,7 @@ reg32 |= (1 << 31) | (1 << 27); pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); - RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030509; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(GCS); - reg32 |= (1 << 6); - RCBA32(GCS) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - // next step only on ich7m b0 and later: - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; + ich7_setup_cir(); } void mainboard_romstage_entry(void) diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index 989a0cb..d4ce940 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -96,16 +96,7 @@ RCBA8(OIC) = 0x03; RCBA8(OIC); - RCBA32(GCS) = 0x00190464; - RCBA32(CG) = 0x00000000; - RCBA32(0x3430) = 0x00000001; - RCBA32(0x3e00) = 0xff000001; - RCBA32(0x3e08) = 0x00000080; - RCBA32(0x3e0c) = 0x00800000; - RCBA32(0x3e40) = 0xff000001; - RCBA32(0x3e48) = 0x00000080; - RCBA32(0x3e4c) = 0x00800000; - RCBA32(0x3f00) = 0x0000000b; + ich7_setup_cir(); } static void ich7_enable_lpc(void) diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 82dbba5..1c3202f 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -169,31 +169,7 @@ reg32 |= (1 << 31) | (1 << 27); pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); - RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(GCS); - reg32 |= (1 << 6); - RCBA32(GCS) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - // next step only on ich7m b0 and later: - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; + ich7_setup_cir(); } void mainboard_romstage_entry(void) diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index bad2b6d..f6fc8df 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -89,31 +89,7 @@ reg32 |= (1 << 31) | (1 << 27); pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); - RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(0x3410); - reg32 |= (1 << 6); - RCBA32(0x3410) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - // next step only on ich7m b0 and later: - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; + ich7_setup_cir(); } void mainboard_romstage_entry(void) diff --git a/src/mainboard/intel/dg41wv/romstage.c b/src/mainboard/intel/dg41wv/romstage.c index 74f8622..f27499b 100644 --- a/src/mainboard/intel/dg41wv/romstage.c +++ b/src/mainboard/intel/dg41wv/romstage.c @@ -55,10 +55,7 @@ RCBA8(0x31ff) = 0x03; RCBA8(0x31ff); - reg32 = RCBA32(GCS); - reg32 |= (1 << 5); - RCBA32(GCS) = reg32; - RCBA32(CG) = 0x00000001; + ich7_setup_cir(); } static void ich7_enable_lpc(void) diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index cee7c2a..2c2ad8b 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -213,31 +213,7 @@ reg32 |= (1 << 31) | (1 << 27); pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); - RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(GCS); - reg32 |= (1 << 6); - RCBA32(GCS) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - /* next step only on ich7m b0 and later: */ - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; + ich7_setup_cir(); } void mainboard_romstage_entry(void) diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index 9e83220..1fe16a9 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -129,31 +129,7 @@ reg32 |= (1 << 31) | (1 << 27); pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); - RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(GCS); - reg32 |= (1 << 6); - RCBA32(GCS) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - // next step only on ich7m b0 and later: - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; + ich7_setup_cir(); } void mainboard_romstage_entry(void) diff --git a/src/mainboard/lenovo/thinkcentre_a58/romstage.c b/src/mainboard/lenovo/thinkcentre_a58/romstage.c index e4abab5..7329f0b 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/romstage.c +++ b/src/mainboard/lenovo/thinkcentre_a58/romstage.c @@ -41,10 +41,7 @@ RCBA8(0x31ff) = 0x03; RCBA8(0x31ff); - reg32 = RCBA32(GCS); - reg32 |= (1 << 5); - RCBA32(GCS) = reg32; - RCBA32(CG) = 0x00000001; + ich7_setup_cir(); } static void ich7_enable_lpc(void) diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 5a8ab94..8189f8a 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -129,31 +129,7 @@ reg32 |= (1 << 31) | (1 << 27); pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); - RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(GCS); - reg32 |= (1 << 6); - RCBA32(GCS) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - // next step only on ich7m b0 and later: - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; + ich7_setup_cir(); } void mainboard_romstage_entry(void) diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c index 7f12091..09d5dae 100644 --- a/src/mainboard/lenovo/z61t/romstage.c +++ b/src/mainboard/lenovo/z61t/romstage.c @@ -129,31 +129,7 @@ reg32 |= (1 << 31) | (1 << 27); pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); - RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(GCS); - reg32 |= (1 << 6); - RCBA32(GCS) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - // next step only on ich7m b0 and later: - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; + ich7_setup_cir(); } void mainboard_romstage_entry(void) diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index 93b24a0..b1622ef 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -169,31 +169,7 @@ reg32 |= (1 << 31) | (1 << 27); pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); - RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(GCS); - reg32 |= (1 << 6); - RCBA32(GCS) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - /* next step only on ich7m b0 and later: */ - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; + ich7_setup_cir(); } static void init_artec_dongle(void) diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index be6a5e2..1638f0e 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -135,26 +135,8 @@ pci_write_config8(LPC, 0x8, 0x1d); pci_write_config8(LPC, 0x8, 0x0); RCBA32(0x3410) = 0x00020465; - RCBA32(0x88) = 0x0011d000; - RCBA32(0x1fc) = 0x60f; - RCBA32(0x1f4) = 0x86000040; - RCBA32(0x214) = 0x10030509; - RCBA32(0x218) = 0x00020504; - RCBA32(0x220) = 0xc5; - RCBA32(0x3430) = 0x1; - RCBA32(0x2027) = 0x38f6a70d; - RCBA16(0x3e08) = 0x0080; - RCBA16(0x3e48) = 0x0080; - RCBA32(0x3e0e) = 0x00000080; - RCBA32(0x3e4e) = 0x00000080; - RCBA32(0x2034) = 0xb24577cc; - RCBA32(0x1c) = 0x03128010; - RCBA32(0x2010) = 0x400; - RCBA32(0x3400) = 0x4; - RCBA32(0x2080) = 0x18006007; - RCBA32(0x20a0) = 0x18006007; - RCBA32(0x20c0) = 0x18006007; - RCBA32(0x20e0) = 0x18006007; + + ich7_setup_cir(); pci_write_config32(PCI_DEV(0, 0x1d, 0), 0xca, 0x1); pci_write_config32(PCI_DEV(0, 0x1d, 1), 0xca, 0x1); diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index 475def3..4156bf7e 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -62,7 +62,7 @@ int pch_silicon_supported(int type, int rev) { int cur_type = pch_silicon_type(); - int cur_rev = pch_silicon_revision(); + int cur_rev = pch_silicon_1revision(); switch (type) { case PCH_TYPE_CPT: diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc index 237c2d5..2e9d31a 100644 --- a/src/southbridge/intel/i82801gx/Makefile.inc +++ b/src/southbridge/intel/i82801gx/Makefile.inc @@ -35,5 +35,6 @@ smm-y += smihandler.c romstage-y += early_smbus.c +romstage-y += early_cir.c endif diff --git a/src/southbridge/intel/i82801gx/early_cir.c b/src/southbridge/intel/i82801gx/early_cir.c new file mode 100644 index 0000000..08f8019 --- /dev/null +++ b/src/southbridge/intel/i82801gx/early_cir.c @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include "i82801gx.h" + +/* Chipset Initialization Registers magic */ +void ich7_setup_cir(void) +{ + uint32_t reg32; + uint8_t revision = pci_read_config8(PCI_DEV(0, 31, 0), PCI_REVISION_ID); + uint16_t pci_id = pci_read_config16(PCI_DEV(0, 31, 0), PCI_DEVICE_ID); + + RCBA32(0x0088) = 0x0011d000; + RCBA16(0x01fc) = 0x060f; + RCBA32(0x01f4) = 0x86000040; + RCBA32(0x0214) = 0x10030549; + RCBA32(0x0218) = 0x00020504; + RCBA8(0x0220) = 0xc5; + reg32 = RCBA32(GCS); + reg32 |= (1 << 6); + RCBA32(GCS) = reg32; + RCBA32_AND_OR(0x3430, ~(3 << 0), 1 << 0); + RCBA16(0x0200) = 0x2008; + RCBA8(0x2027) = 0x0d; + RCBA16(0x3e08) |= (1 << 7); + RCBA16(0x3e48) |= (1 << 7); + RCBA32(0x3e0e) |= (1 << 7); + RCBA32(0x3e4e) |= (1 << 7); + + /* Only on mobile variants of revision b0 or later */ + switch (pci_id) { + case 0x27b9: + case 0x27bc: + case 0x27bd: + if (revision > 2) { + reg32 = RCBA32(0x2034); + reg32 &= ~(0x0f << 16); + reg32 |= (5 << 16); + RCBA32(0x2034) = reg32; + } + } +} diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index d615b40..8c85331 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -48,6 +48,7 @@ int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf); int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, const u8 *buf); +void ich7_setup_cir(void); #endif #define MAINBOARD_POWER_OFF 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/35795 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia10c050785170fc743f7aef918f4849dbdd6840e Gerrit-Change-Number: 35795 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

2 12

Change in coreboot[master]: mb/facebook/fbg1701: separate cpld support
by Wim Vervoorn (Code Review) 11 Oct '19

11 Oct '19

Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35962 ) Change subject: mb/facebook/fbg1701: separate cpld support ...................................................................... mb/facebook/fbg1701: separate cpld support Move all code involving the cpld to a single file. Also address the issues reported by clang-format. BUG=N/A TEST=tested on fbg1701 board Change-Id: I8f456bcfd966213e60a894d685a563957b089f29 Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M src/mainboard/facebook/fbg1701/Makefile.inc A src/mainboard/facebook/fbg1701/cpld.c A src/mainboard/facebook/fbg1701/cpld.h M src/mainboard/facebook/fbg1701/mainboard.c M src/mainboard/facebook/fbg1701/mainboard.h M src/mainboard/facebook/fbg1701/onboard.h M src/mainboard/facebook/fbg1701/ramstage.c 7 files changed, 341 insertions(+), 292 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/35962/1 diff --git a/src/mainboard/facebook/fbg1701/Makefile.inc b/src/mainboard/facebook/fbg1701/Makefile.inc index c414470..7341291 100644 --- a/src/mainboard/facebook/fbg1701/Makefile.inc +++ b/src/mainboard/facebook/fbg1701/Makefile.inc @@ -24,6 +24,7 @@ bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += com_init.c +ramstage-y += cpld.c ramstage-y += gpio.c ramstage-y += hda_verb.c ramstage-y += irqroute.c @@ -31,6 +32,8 @@ ramstage-y += ramstage.c ramstage-y += w25q64.c +romstage-y += cpld.c + cbfs-files-$(CONFIG_FSP1_1_DISPLAY_LOGO) += logo.bmp logo.bmp-file := $(call strip_quotes,$(CONFIG_FSP1_1_LOGO_FILE_NAME)) logo.bmp-type := raw diff --git a/src/mainboard/facebook/fbg1701/cpld.c b/src/mainboard/facebook/fbg1701/cpld.c new file mode 100755 index 0000000..354a757 --- /dev/null +++ b/src/mainboard/facebook/fbg1701/cpld.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include "cpld.h" + +/* Reset DSI bridge */ +void cpld_reset_bridge(void) +{ + outb(CPLD_CMD_RESET_DSI_BRIDGE_ACTIVE, CPLD_RESET_PORT); + outb(CPLD_CMD_RESET_DSI_BRIDGE_INACTIVE, CPLD_RESET_PORT); +} + +/* Read PCB version */ +unsigned int cpld_read_pcb_version(void) +{ + return ((inb(CPLD_PCB_VERSION_PORT) & CPLD_PCB_VERSION_MASK) >> CPLD_PCB_VERSION_BIT); +} diff --git a/src/mainboard/facebook/fbg1701/cpld.h b/src/mainboard/facebook/fbg1701/cpld.h new file mode 100755 index 0000000..c7ae613 --- /dev/null +++ b/src/mainboard/facebook/fbg1701/cpld.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef CPLD_H +#define CPLD_H + +/* CPLD definitions */ +#define CPLD_PCB_VERSION_PORT 0x283 +#define CPLD_PCB_VERSION_MASK 0xF0 +#define CPLD_PCB_VERSION_BIT 4 + +#define CPLD_RESET_PORT 0x287 +#define CPLD_CMD_RESET_DSI_BRIDGE_ACTIVE 0x20 +#define CPLD_CMD_RESET_DSI_BRIDGE_INACTIVE 0x00 + +unsigned int cpld_read_pcb_version(void); +void cpld_reset_bridge(void); + +#endif diff --git a/src/mainboard/facebook/fbg1701/mainboard.c b/src/mainboard/facebook/fbg1701/mainboard.c old mode 100644 new mode 100755 index a8cb34c..8524b24 --- a/src/mainboard/facebook/fbg1701/mainboard.c +++ b/src/mainboard/facebook/fbg1701/mainboard.c @@ -16,10 +16,7 @@ * GNU General Public License for more details. */ -#include <arch/io.h> #include <device/device.h> -#include "mainboard.h" -#include "onboard.h" /* * Declare the resources we are using @@ -39,13 +36,6 @@ res->flags = IORESOURCE_IRQ | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -/* Read PCB version */ -unsigned int mainboard_read_pcb_version(void) -{ - return ((inb(CPLD_PCB_VERSION_PORT) & CPLD_PCB_VERSION_MASK) >> - CPLD_PCB_VERSION_BIT); -} - /* * mainboard_enable is executed as first thing after * enumerate_buses(). diff --git a/src/mainboard/facebook/fbg1701/mainboard.h b/src/mainboard/facebook/fbg1701/mainboard.h old mode 100644 new mode 100755 index 3cace54..e161da0 --- a/src/mainboard/facebook/fbg1701/mainboard.h +++ b/src/mainboard/facebook/fbg1701/mainboard.h @@ -16,7 +16,6 @@ #ifndef MAINBOARD_H #define MAINBOARD_H -unsigned int mainboard_read_pcb_version(void); void *load_logo(size_t *logo_size); #endif diff --git a/src/mainboard/facebook/fbg1701/onboard.h b/src/mainboard/facebook/fbg1701/onboard.h old mode 100644 new mode 100755 index 330fe0f..cb784da --- a/src/mainboard/facebook/fbg1701/onboard.h +++ b/src/mainboard/facebook/fbg1701/onboard.h @@ -19,28 +19,19 @@ #define ONBOARD_H /* SD CARD gpio */ -#define SDCARD_CD 81 /* Not used */ +#define SDCARD_CD 81 /* Not used */ -#define ITE8528_CMD_PORT 0x6E -#define ITE8528_DATA_PORT 0x6F - -/* CPLD definitions */ -#define CPLD_PCB_VERSION_PORT 0x283 -#define CPLD_PCB_VERSION_MASK 0xF0 -#define CPLD_PCB_VERSION_BIT 4 - -#define CPLD_RESET_PORT 0x287 -#define CPLD_CMD_RESET_DSI_BRIDGE_ACTIVE 0x20 -#define CPLD_CMD_RESET_DSI_BRIDGE_INACTIVE 0x00 +#define ITE8528_CMD_PORT 0x6E +#define ITE8528_DATA_PORT 0x6F /* Define the items to be measured or verified */ -#define FSP (const char *)"fsp.bin" -#define CMOS_LAYOUT (const char *)"cmos_layout.bin" -#define RAMSTAGE (const char *)"fallback/ramstage" -#define ROMSTAGE (const char *)"fallback/romstage" -#define PAYLOAD (const char *)"fallback/payload" -#define POSTCAR (const char *)"fallback/postcar" -#define OP_ROM_VBT (const char *)"vbt.bin" -#define MICROCODE (const char *)"cpu_microcode_blob.bin" +#define FSP (const char *)"fsp.bin" +#define CMOS_LAYOUT (const char *)"cmos_layout.bin" +#define RAMSTAGE (const char *)"fallback/ramstage" +#define ROMSTAGE (const char *)"fallback/romstage" +#define PAYLOAD (const char *)"fallback/payload" +#define POSTCAR (const char *)"fallback/postcar" +#define OP_ROM_VBT (const char *)"vbt.bin" +#define MICROCODE (const char *)"cpu_microcode_blob.bin" #endif diff --git a/src/mainboard/facebook/fbg1701/ramstage.c b/src/mainboard/facebook/fbg1701/ramstage.c old mode 100644 new mode 100755 index c5fb798..ae2dbbf --- a/src/mainboard/facebook/fbg1701/ramstage.c +++ b/src/mainboard/facebook/fbg1701/ramstage.c @@ -21,6 +21,8 @@ #include "mainboard.h" #include "onboard.h" +#include "cpld.h" + struct edp_data { u8 payload_length; u8 address; @@ -31,318 +33,321 @@ static const struct edp_data b101uan01_table[] = { /* set eDP bridge to 1200x1920 */ /* IO */ - { 6, 0x68, { 0x08, 0x00, 0x01, 0x00, 0x00, 0x00 } }, + {6, 0x68, {0x08, 0x00, 0x01, 0x00, 0x00, 0x00}}, /* Boot */ - { 6, 0x68, { 0x10, 0x00, 0x78, 0x69, 0x00, 0x00 } }, - { 6, 0x68, { 0x10, 0x04, 0x02, 0x08, 0x02, 0x00 } }, - { 6, 0x68, { 0x10, 0x08, 0x23, 0x00, 0x87, 0x02 } }, - { 6, 0x68, { 0x10, 0x0C, 0x19, 0x04, 0x00, 0x23 } }, - { 6, 0x68, { 0x10, 0x10, 0x06, 0x00, 0x67, 0x00 } }, - { 6, 0x68, { 0x10, 0x14, 0x01, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF } }, + {6, 0x68, {0x10, 0x00, 0x78, 0x69, 0x00, 0x00}}, + {6, 0x68, {0x10, 0x04, 0x02, 0x08, 0x02, 0x00}}, + {6, 0x68, {0x10, 0x08, 0x23, 0x00, 0x87, 0x02}}, + {6, 0x68, {0x10, 0x0C, 0x19, 0x04, 0x00, 0x23}}, + {6, 0x68, {0x10, 0x10, 0x06, 0x00, 0x67, 0x00}}, + {6, 0x68, {0x10, 0x14, 0x01, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF}}, /* Internal */ - { 3, 0x68, { 0xB0, 0x05, 0x0A, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB0, 0x06, 0x03, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB0, 0x07, 0x16, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB0, 0x08, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB0, 0x09, 0x21, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB0, 0x0A, 0x07, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x10, 0x14, 0x03, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF } }, + {3, 0x68, {0xB0, 0x05, 0x0A, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB0, 0x06, 0x03, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB0, 0x07, 0x16, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB0, 0x08, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB0, 0x09, 0x21, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB0, 0x0A, 0x07, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x10, 0x14, 0x03, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF}}, /* eDP */ - { 3, 0x68, { 0x80, 0x03, 0x41, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB4, 0x00, 0x0D, 0x00, 0x00, 0x00 } }, + {3, 0x68, {0x80, 0x03, 0x41, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB4, 0x00, 0x0D, 0x00, 0x00, 0x00}}, /* DPRX */ - { 3, 0x68, { 0xB8, 0x8E, 0xFF, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x8F, 0xFF, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x9A, 0xFF, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x9B, 0xFF, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x00, 0x0E, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x26, 0x02, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x01, 0x20, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0xC0, 0xF1, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0xC1, 0xF1, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0xC2, 0xF0, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0xC3, 0xF0, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0xC4, 0xF0, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0xC5, 0xF0, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0xC6, 0xF0, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0xC7, 0xF0, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x0B, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x33, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x5B, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x10, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x38, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x60, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x15, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x3D, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x65, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x1A, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x42, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x6A, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x1F, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x47, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x6F, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x24, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x4C, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x74, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x29, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x51, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x79, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x2E, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x56, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x7E, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x90, 0x10, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x91, 0x0F, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x92, 0xF6, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x93, 0x10, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x94, 0x0F, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x95, 0xF6, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x96, 0x10, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x97, 0x0F, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x98, 0xF6, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x99, 0x10, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x9A, 0x0F, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x9B, 0xF6, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x8A, 0x03, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x96, 0x03, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0xD1, 0x07, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0xB0, 0x07, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x8B, 0x04, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x8C, 0x45, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x8D, 0x05, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x97, 0x04, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x98, 0xE0, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x99, 0x2E, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0x80, 0x0E, 0x00, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x10, 0x14, 0x07, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF } }, + {3, 0x68, {0xB8, 0x8E, 0xFF, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x8F, 0xFF, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x9A, 0xFF, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x9B, 0xFF, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x00, 0x0E, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x26, 0x02, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x01, 0x20, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0xC0, 0xF1, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0xC1, 0xF1, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0xC2, 0xF0, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0xC3, 0xF0, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0xC4, 0xF0, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0xC5, 0xF0, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0xC6, 0xF0, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0xC7, 0xF0, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x0B, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x33, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x5B, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x10, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x38, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x60, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x15, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x3D, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x65, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x1A, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x42, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x6A, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x1F, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x47, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x6F, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x24, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x4C, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x74, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x29, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x51, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x79, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x2E, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x56, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x7E, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x90, 0x10, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x91, 0x0F, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x92, 0xF6, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x93, 0x10, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x94, 0x0F, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x95, 0xF6, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x96, 0x10, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x97, 0x0F, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x98, 0xF6, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x99, 0x10, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x9A, 0x0F, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x9B, 0xF6, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x8A, 0x03, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x96, 0x03, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0xD1, 0x07, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0xB0, 0x07, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x8B, 0x04, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x8C, 0x45, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x8D, 0x05, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x97, 0x04, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x98, 0xE0, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x99, 0x2E, 0x00, 0x00, 0x00}}, + {3, 0x68, {0x80, 0x0E, 0x00, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x10, 0x14, 0x07, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF}}, /* Video size */ - { 6, 0x68, { 0x01, 0x48, 0xB0, 0x04, 0x00, 0x00 } }, - { 6, 0x68, { 0x29, 0x20, 0x10, 0x0E, 0x0B, 0x3E } }, + {6, 0x68, {0x01, 0x48, 0xB0, 0x04, 0x00, 0x00}}, + {6, 0x68, {0x29, 0x20, 0x10, 0x0E, 0x0B, 0x3E}}, /* eDP */ - { 3, 0x68, { 0xB6, 0x31, 0xFF, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0x80, 0x01, 0x14, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0x80, 0x02, 0x02, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB6, 0x08, 0x0B, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x00, 0x1E, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0x87, 0x00, 0x00, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x50, 0x10, 0x00, 0x00, 0x9D, 0x00 } }, - { 6, 0x68, { 0x00, 0x8C, 0x40, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x00, 0x80, 0x02, 0x00, 0x00, 0x00 } }, + {3, 0x68, {0xB6, 0x31, 0xFF, 0x00, 0x00, 0x00}}, + {3, 0x68, {0x80, 0x01, 0x14, 0x00, 0x00, 0x00}}, + {3, 0x68, {0x80, 0x02, 0x02, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB6, 0x08, 0x0B, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x00, 0x1E, 0x00, 0x00, 0x00}}, + {3, 0x68, {0x87, 0x00, 0x00, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x50, 0x10, 0x00, 0x00, 0x9D, 0x00}}, + {6, 0x68, {0x00, 0x8C, 0x40, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x00, 0x80, 0x02, 0x00, 0x00, 0x00}}, /* Link Training */ - { 3, 0x68, { 0x82, 0x02, 0xFF, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0x82, 0x03, 0xFF, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0x82, 0x04, 0xFF, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x21, 0x58, 0x09, 0x00, 0x28, 0x00 } }, - { 6, 0x68, { 0x21, 0x60, 0x07, 0x00, 0x0F, 0x00 } }, - { 6, 0x68, { 0x21, 0x64, 0x28, 0x23, 0x00, 0x00 } }, - { 6, 0x68, { 0x21, 0x68, 0x0E, 0x00, 0x00, 0x00 } }, + {3, 0x68, {0x82, 0x02, 0xFF, 0x00, 0x00, 0x00}}, + {3, 0x68, {0x82, 0x03, 0xFF, 0x00, 0x00, 0x00}}, + {3, 0x68, {0x82, 0x04, 0xFF, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x21, 0x58, 0x09, 0x00, 0x28, 0x00}}, + {6, 0x68, {0x21, 0x60, 0x07, 0x00, 0x0F, 0x00}}, + {6, 0x68, {0x21, 0x64, 0x28, 0x23, 0x00, 0x00}}, + {6, 0x68, {0x21, 0x68, 0x0E, 0x00, 0x00, 0x00}}, /* DSI */ - { 6, 0x68, { 0x20, 0x7C, 0x81, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x20, 0x50, 0x00, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x20, 0x1C, 0x01, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x20, 0x60, 0xFF, 0xFF, 0xFF, 0xFF } }, + {6, 0x68, {0x20, 0x7C, 0x81, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x20, 0x50, 0x00, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x20, 0x1C, 0x01, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x20, 0x60, 0xFF, 0xFF, 0xFF, 0xFF}}, /* GPIO */ - { 6, 0x68, { 0x08, 0x04, 0x00, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x00, 0x84, 0x0F, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x00, 0x84, 0x00, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x00, 0x84, 0x0F, 0x00, 0x00, 0x00 } }, + {6, 0x68, {0x08, 0x04, 0x00, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x00, 0x80, 0x0F, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x00, 0x84, 0x0F, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x00, 0x84, 0x00, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x00, 0x84, 0x0F, 0x00, 0x00, 0x00}}, /* DSI clock */ - { 6, 0x68, { 0x20, 0x50, 0x20, 0x00, 0x00, 0x00 } }, + {6, 0x68, {0x20, 0x50, 0x20, 0x00, 0x00, 0x00}}, /* LCD init */ - { 6, 0x68, { 0x22, 0xFC, 0x15, 0x01, 0x00, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0x8C, 0x80, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0xC7, 0x50, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0xC5, 0x50, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0x85, 0x04, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0x86, 0x08, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0x83, 0xAA, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0x84, 0x11, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0x9C, 0x10, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0xA9, 0x4B, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x05, 0x11, 0x00, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x05, 0x29, 0x00, 0x81 } }, - { 6, 0x68, { 0x2A, 0x10, 0x10, 0x00, 0x04, 0x80 } }, - { 6, 0x68, { 0x2A, 0x04, 0x01, 0x00, 0x00, 0x00 } }, + {6, 0x68, {0x22, 0xFC, 0x15, 0x01, 0x00, 0x81}}, + {6, 0x68, {0x22, 0xFC, 0x15, 0x8C, 0x80, 0x81}}, + {6, 0x68, {0x22, 0xFC, 0x15, 0xC7, 0x50, 0x81}}, + {6, 0x68, {0x22, 0xFC, 0x15, 0xC5, 0x50, 0x81}}, + {6, 0x68, {0x22, 0xFC, 0x15, 0x85, 0x04, 0x81}}, + {6, 0x68, {0x22, 0xFC, 0x15, 0x86, 0x08, 0x81}}, + {6, 0x68, {0x22, 0xFC, 0x15, 0x83, 0xAA, 0x81}}, + {6, 0x68, {0x22, 0xFC, 0x15, 0x84, 0x11, 0x81}}, + {6, 0x68, {0x22, 0xFC, 0x15, 0x9C, 0x10, 0x81}}, + {6, 0x68, {0x22, 0xFC, 0x15, 0xA9, 0x4B, 0x81}}, + {6, 0x68, {0x22, 0xFC, 0x05, 0x11, 0x00, 0x81}}, + {6, 0x68, {0x22, 0xFC, 0x05, 0x29, 0x00, 0x81}}, + {6, 0x68, {0x2A, 0x10, 0x10, 0x00, 0x04, 0x80}}, + {6, 0x68, {0x2A, 0x04, 0x01, 0x00, 0x00, 0x00}}, /* Check Video */ - { 6, 0x68, { 0x01, 0x54, 0x01, 0x00, 0x00, 0x00 } }, + {6, 0x68, {0x01, 0x54, 0x01, 0x00, 0x00, 0x00}}, /* End of table */ - { 0, 0x00, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } }, + {0, 0x00, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}, }; static const struct edp_data b101uan08_table[] = { /* set eDP bridge to 1200x1920 */ /* IO Voltage Setting */ - { 6, 0x68, { 0x08, 0x00, 0x01, 0x00, 0x00, 0x00 } }, + {6, 0x68, {0x08, 0x00, 0x01, 0x00, 0x00, 0x00}}, /* Boot Settings */ - { 6, 0x68, { 0x10, 0x00, 0x78, 0x69, 0x00, 0x00 } }, - { 6, 0x68, { 0x10, 0x04, 0x02, 0x08, 0x02, 0x00 } }, - { 6, 0x68, { 0x10, 0x08, 0x22, 0x00, 0xA0, 0x02 } }, - { 6, 0x68, { 0x10, 0x0C, 0x50, 0x04, 0x00, 0x03 } }, - { 6, 0x68, { 0x10, 0x10, 0x10, 0x0D, 0x06, 0x01 } }, - { 6, 0x68, { 0x10, 0x14, 0x01, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF } }, + {6, 0x68, {0x10, 0x00, 0x78, 0x69, 0x00, 0x00}}, + {6, 0x68, {0x10, 0x04, 0x02, 0x08, 0x02, 0x00}}, + {6, 0x68, {0x10, 0x08, 0x22, 0x00, 0xA0, 0x02}}, + {6, 0x68, {0x10, 0x0C, 0x50, 0x04, 0x00, 0x03}}, + {6, 0x68, {0x10, 0x10, 0x10, 0x0D, 0x06, 0x01}}, + {6, 0x68, {0x10, 0x14, 0x01, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF}}, /* Internal PCLK settings for Non Present or REFCLK=26MHz */ - { 3, 0x68, { 0xB0, 0x05, 0x0A, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB0, 0x06, 0x03, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB0, 0x07, 0x16, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB0, 0x08, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB0, 0x09, 0x21, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB0, 0x0A, 0x07, 0x00, 0x00, 0x00 } }, + {3, 0x68, {0xB0, 0x05, 0x0A, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB0, 0x06, 0x03, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB0, 0x07, 0x16, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB0, 0x08, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB0, 0x09, 0x21, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB0, 0x0A, 0x07, 0x00, 0x00, 0x00}}, /* DSI Clock setting for Non Preset or REFCLK=26MHz */ - { 6, 0x68, { 0x41, 0xB0, 0xC1, 0x22, 0x04, 0x00 } }, - { 6, 0x68, { 0x41, 0xBC, 0x01, 0x0E, 0x00, 0x00 } }, - { 6, 0x68, { 0x41, 0xC0, 0x30, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x10, 0x14, 0x03, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF } }, + {6, 0x68, {0x41, 0xB0, 0xC1, 0x22, 0x04, 0x00}}, + {6, 0x68, {0x41, 0xBC, 0x01, 0x0E, 0x00, 0x00}}, + {6, 0x68, {0x41, 0xC0, 0x30, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x10, 0x14, 0x03, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF}}, /* Additional Settng for eDP */ - { 3, 0x68, { 0x80, 0x03, 0x41, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB4, 0x00, 0x0D, 0x00, 0x00, 0x00 } }, + {3, 0x68, {0x80, 0x03, 0x41, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB4, 0x00, 0x0D, 0x00, 0x00, 0x00}}, /* DPRX CAD Register Setting */ - { 3, 0x68, { 0xB8, 0x8E, 0xFF, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x8F, 0xFF, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x9A, 0xFF, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x9B, 0xFF, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x00, 0x0E, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x26, 0x02, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x01, 0x20, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0xC0, 0xF1, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0xC1, 0xF1, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0xC2, 0xF0, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0xC3, 0xF0, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0xC4, 0xF0, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0xC5, 0xF0, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0xC6, 0xF0, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0xC7, 0xF0, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x0B, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x33, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x5B, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x10, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x38, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x60, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x15, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x3D, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x65, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x1A, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x42, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x6A, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x1F, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x47, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x6F, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x24, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x4C, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x74, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x29, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x51, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x79, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x2E, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x56, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x7E, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x90, 0x10, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x91, 0x0F, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x92, 0xF6, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x93, 0x10, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x94, 0x0F, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x95, 0xF6, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x96, 0x10, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x97, 0x0F, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x98, 0xF6, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x99, 0x10, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x9A, 0x0F, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x9B, 0xF6, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x8A, 0x03, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x96, 0x03, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0xD1, 0x07, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0xB0, 0x07, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x8B, 0x04, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x8C, 0x45, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x8D, 0x05, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x97, 0x04, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x98, 0xE0, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x99, 0x2E, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0x80, 0x0E, 0x00, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x10, 0x14, 0x07, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF } }, + {3, 0x68, {0xB8, 0x8E, 0xFF, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x8F, 0xFF, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x9A, 0xFF, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x9B, 0xFF, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x00, 0x0E, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x26, 0x02, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x01, 0x20, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0xC0, 0xF1, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0xC1, 0xF1, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0xC2, 0xF0, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0xC3, 0xF0, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0xC4, 0xF0, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0xC5, 0xF0, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0xC6, 0xF0, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0xC7, 0xF0, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x0B, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x33, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x5B, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x10, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x38, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x60, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x15, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x3D, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x65, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x1A, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x42, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x6A, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x1F, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x47, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x6F, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x24, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x4C, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x74, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x29, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x51, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x79, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x2E, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x56, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x7E, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x90, 0x10, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x91, 0x0F, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x92, 0xF6, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x93, 0x10, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x94, 0x0F, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x95, 0xF6, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x96, 0x10, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x97, 0x0F, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x98, 0xF6, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x99, 0x10, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x9A, 0x0F, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x9B, 0xF6, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x8A, 0x03, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x96, 0x03, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0xD1, 0x07, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0xB0, 0x07, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x8B, 0x04, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x8C, 0x45, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x8D, 0x05, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x97, 0x04, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x98, 0xE0, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x99, 0x2E, 0x00, 0x00, 0x00}}, + {3, 0x68, {0x80, 0x0E, 0x00, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x10, 0x14, 0x07, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF}}, /* Video size Related Settings for Non Present */ - { 6, 0x68, { 0x01, 0x48, 0xB0, 0x04, 0x00, 0x00 } }, - { 6, 0x68, { 0x29, 0x20, 0x10, 0x0E, 0x0B, 0x3E } }, + {6, 0x68, {0x01, 0x48, 0xB0, 0x04, 0x00, 0x00}}, + {6, 0x68, {0x29, 0x20, 0x10, 0x0E, 0x0B, 0x3E}}, /* eDP Settings for Link Training*/ - { 3, 0x68, { 0xB6, 0x31, 0xFF, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0x80, 0x01, 0x14, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0x80, 0x02, 0x02, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB6, 0x08, 0x0B, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x00, 0x1E, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0x87, 0x00, 0x00, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x50, 0x10, 0x00, 0x00, 0x9D, 0x00 } }, - { 6, 0x68, { 0x00, 0x8C, 0x40, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x00, 0x80, 0x02, 0x00, 0x00, 0x00 } }, + {3, 0x68, {0xB6, 0x31, 0xFF, 0x00, 0x00, 0x00}}, + {3, 0x68, {0x80, 0x01, 0x14, 0x00, 0x00, 0x00}}, + {3, 0x68, {0x80, 0x02, 0x02, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB6, 0x08, 0x0B, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x00, 0x1E, 0x00, 0x00, 0x00}}, + {3, 0x68, {0x87, 0x00, 0x00, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x50, 0x10, 0x00, 0x00, 0x9D, 0x00}}, + {6, 0x68, {0x00, 0x8C, 0x40, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x00, 0x80, 0x02, 0x00, 0x00, 0x00}}, /* Link Training */ - { 3, 0x68, { 0x82, 0x02, 0xFF, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0x82, 0x03, 0xFF, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0x82, 0x04, 0xFF, 0x00, 0x00, 0x00 } }, + {3, 0x68, {0x82, 0x02, 0xFF, 0x00, 0x00, 0x00}}, + {3, 0x68, {0x82, 0x03, 0xFF, 0x00, 0x00, 0x00}}, + {3, 0x68, {0x82, 0x04, 0xFF, 0x00, 0x00, 0x00}}, /* DSI Transition Time Setting for Non Preset */ - { 6, 0x68, { 0x21, 0x54, 0x0D, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x21, 0x58, 0x06, 0x00, 0x2A, 0x00 } }, - { 6, 0x68, { 0x21, 0x5C, 0x07, 0x00, 0x0E, 0x00 } }, - { 6, 0x68, { 0x21, 0x60, 0x07, 0x00, 0x10, 0x00 } }, - { 6, 0x68, { 0x21, 0x64, 0x10, 0x27, 0x00, 0x00 } }, - { 6, 0x68, { 0x21, 0x68, 0x0E, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x21, 0x6C, 0x0A, 0x00, 0x0E, 0x00 } }, - { 6, 0x68, { 0x21, 0x78, 0x0E, 0x00, 0x0D, 0x00 } }, + {6, 0x68, {0x21, 0x54, 0x0D, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x21, 0x58, 0x06, 0x00, 0x2A, 0x00}}, + {6, 0x68, {0x21, 0x5C, 0x07, 0x00, 0x0E, 0x00}}, + {6, 0x68, {0x21, 0x60, 0x07, 0x00, 0x10, 0x00}}, + {6, 0x68, {0x21, 0x64, 0x10, 0x27, 0x00, 0x00}}, + {6, 0x68, {0x21, 0x68, 0x0E, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x21, 0x6C, 0x0A, 0x00, 0x0E, 0x00}}, + {6, 0x68, {0x21, 0x78, 0x0E, 0x00, 0x0D, 0x00}}, /* DSI Start */ - { 6, 0x68, { 0x20, 0x7C, 0x81, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x20, 0x50, 0x00, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x20, 0x1C, 0x01, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x20, 0x60, 0xFF, 0xFF, 0xFF, 0xFF } }, + {6, 0x68, {0x20, 0x7C, 0x81, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x20, 0x50, 0x00, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x20, 0x1C, 0x01, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x20, 0x60, 0xFF, 0xFF, 0xFF, 0xFF}}, /* GPIO for LCD control*/ - { 6, 0x68, { 0x08, 0x04, 0x00, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x00, 0x84, 0x0F, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x00, 0x84, 0x00, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x00, 0x84, 0x0F, 0x00, 0x00, 0x00 } }, + {6, 0x68, {0x08, 0x04, 0x00, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x00, 0x80, 0x0F, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x00, 0x84, 0x0F, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x00, 0x84, 0x00, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x00, 0x84, 0x0F, 0x00, 0x00, 0x00}}, /* DSI Hs Clock Mode */ - { 6, 0x68, { 0x20, 0x50, 0x20, 0x00, 0x00, 0x00 } }, + {6, 0x68, {0x20, 0x50, 0x20, 0x00, 0x00, 0x00}}, /* LCD Initialization */ - { 6, 0x68, { 0x22, 0xFC, 0x15, 0xBF, 0xA5, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0x01, 0x00, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0x8F, 0xA5, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0x83, 0xAA, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0x84, 0x11, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0xA9, 0x48, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0x83, 0x00, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0x84, 0x00, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0x8F, 0x00, 0x81 } }, - { 6, 0x68, { 0x2A, 0x10, 0x10, 0x00, 0x04, 0x80 } }, - { 6, 0x68, { 0x2A, 0x04, 0x01, 0x00, 0x00, 0x00 } }, + {6, 0x68, {0x22, 0xFC, 0x15, 0xBF, 0xA5, 0x81}}, + {6, 0x68, {0x22, 0xFC, 0x15, 0x01, 0x00, 0x81}}, + {6, 0x68, {0x22, 0xFC, 0x15, 0x8F, 0xA5, 0x81}}, + {6, 0x68, {0x22, 0xFC, 0x15, 0x83, 0xAA, 0x81}}, + {6, 0x68, {0x22, 0xFC, 0x15, 0x84, 0x11, 0x81}}, + {6, 0x68, {0x22, 0xFC, 0x15, 0xA9, 0x48, 0x81}}, + {6, 0x68, {0x22, 0xFC, 0x15, 0x83, 0x00, 0x81}}, + {6, 0x68, {0x22, 0xFC, 0x15, 0x84, 0x00, 0x81}}, + {6, 0x68, {0x22, 0xFC, 0x15, 0x8F, 0x00, 0x81}}, + {6, 0x68, {0x2A, 0x10, 0x10, 0x00, 0x04, 0x80}}, + {6, 0x68, {0x2A, 0x04, 0x01, 0x00, 0x00, 0x00}}, /* Check if eDP video is coming */ - { 6, 0x68, { 0x01, 0x54, 0x01, 0x00, 0x00, 0x00 } }, + {6, 0x68, {0x01, 0x54, 0x01, 0x00, 0x00, 0x00}}, /* End of table */ - { 0, 0x00, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } }, + {0, 0x00, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}, }; static void mainboard_configure_edp_bridge(void) { const struct edp_data *edptable; unsigned int loops; + unsigned int pcb_version; int status; - if (mainboard_read_pcb_version() < 7) + pcb_version = cpld_read_pcb_version(); + printk(BIOS_DEBUG, "PCB version: %x\n", pcb_version); + + if (pcb_version < 7) edptable = b101uan01_table; else edptable = b101uan08_table; /* reset bridge */ - outb(CPLD_CMD_RESET_DSI_BRIDGE_ACTIVE, CPLD_RESET_PORT); - outb(CPLD_CMD_RESET_DSI_BRIDGE_INACTIVE, CPLD_RESET_PORT); + cpld_reset_bridge(); while (edptable->payload_length) { loops = 5; do { status = smbus_i2c_block_write(edptable->address, - edptable->payload_length, - (u8 *)&edptable->data[0]); + edptable->payload_length, + (u8 *)&edptable->data[0]); } while (--loops && (status < 0)); if (loops == 0) { -- To view, visit https://review.coreboot.org/c/coreboot/+/35962 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f456bcfd966213e60a894d685a563957b089f29 Gerrit-Change-Number: 35962 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn Gerrit-MessageType: newchange

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Change in coreboot[master]: vendorcode/eltan/Kconfig: Hide the Kconfig options when lacking support
by Arthur Heymans (Code Review) 11 Oct '19

11 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35954 ) Change subject: vendorcode/eltan/Kconfig: Hide the Kconfig options when lacking support ...................................................................... vendorcode/eltan/Kconfig: Hide the Kconfig options when lacking support The vendorcode/eltan mboot and verified boot options only build if a few other Kconfig options are defined. Change-Id: Ie333d2fbf294e23ec01df06ee551e2d09541c744 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/facebook/fbg1701/Kconfig M src/vendorcode/eltan/Kconfig 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/35954/1 diff --git a/src/mainboard/facebook/fbg1701/Kconfig b/src/mainboard/facebook/fbg1701/Kconfig index 0aa4acc..a607705 100644 --- a/src/mainboard/facebook/fbg1701/Kconfig +++ b/src/mainboard/facebook/fbg1701/Kconfig @@ -30,6 +30,7 @@ select DISABLE_HPET select INTEL_GMA_HAVE_VBT select GENERIC_SPD_BIN + select USE_VENDORCODE_ELTAN config ONBOARD_SAMSUNG_MEM bool "Onboard memory manufacturer Samsung" diff --git a/src/vendorcode/eltan/Kconfig b/src/vendorcode/eltan/Kconfig index 731dd2c..dc756ab 100644 --- a/src/vendorcode/eltan/Kconfig +++ b/src/vendorcode/eltan/Kconfig @@ -13,5 +13,10 @@ ## GNU General Public License for more details. ## +config USE_VENDORCODE_ELTAN + bool + +if USE_VENDORCODE_ELTAN source src/vendorcode/eltan/security/mboot/Kconfig source src/vendorcode/eltan/security/verified_boot/Kconfig +endif -- To view, visit https://review.coreboot.org/c/coreboot/+/35954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie333d2fbf294e23ec01df06ee551e2d09541c744 Gerrit-Change-Number: 35954 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: vendorcode/siemens: Remove sourcing non existing Kconfig files
by Arthur Heymans (Code Review) 11 Oct '19

11 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35953 ) Change subject: vendorcode/siemens: Remove sourcing non existing Kconfig files ...................................................................... vendorcode/siemens: Remove sourcing non existing Kconfig files There is only one subdir in vendorcode/siemens and it does not feature a Kconfig file. Change-Id: I136743344465cea9c769234aa84d9ebe874ef0d2 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/vendorcode/siemens/Kconfig 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/35953/1 diff --git a/src/vendorcode/siemens/Kconfig b/src/vendorcode/siemens/Kconfig index 8bbab62..6684b8a 100644 --- a/src/vendorcode/siemens/Kconfig +++ b/src/vendorcode/siemens/Kconfig @@ -16,5 +16,3 @@ config USE_SIEMENS_HWILIB bool default n - -source "src/vendorcode/siemens/*/Kconfig" -- To view, visit https://review.coreboot.org/c/coreboot/+/35953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I136743344465cea9c769234aa84d9ebe874ef0d2 Gerrit-Change-Number: 35953 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation/mainboard/facebook: Add rev 1.3
by Frans Hendriks (Code Review) 11 Oct '19

11 Oct '19

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35955 ) Change subject: Documentation/mainboard/facebook: Add rev 1.3 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/35955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaba6f28368e2e4ca412122b5fa28ed93c705f4df Gerrit-Change-Number: 35955 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Wim Vervoorn Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 11 Oct 2019 06:27:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit October 2019