coreboot-gerrit October 2019

coreboot-gerrit@coreboot.org

1 participants
1921 discussions

Change in coreboot[master]: [UNTESTED]nb/intel/nehalem: Start VBOOT in bootblock with a separate ...
by Arthur Heymans (Code Review) 13 Oct '19

13 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35952 ) Change subject: [UNTESTED]nb/intel/nehalem: Start VBOOT in bootblock with a separate verstage ...................................................................... [UNTESTED]nb/intel/nehalem: Start VBOOT in bootblock with a separate verstage Change-Id: Ia2b2f2b95510388599266264eaed0d64ce9b6ec5 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/nehalem/Kconfig 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/35952/1 diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index e37923e..e45ba43 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -28,7 +28,8 @@ config VBOOT select VBOOT_MUST_REQUEST_DISPLAY - select VBOOT_STARTS_IN_ROMSTAGE + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE config MMCONF_BUS_NUMBER int -- To view, visit https://review.coreboot.org/c/coreboot/+/35952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2b2f2b95510388599266264eaed0d64ce9b6ec5 Gerrit-Change-Number: 35952 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: nb/intel/nehalem: Move to C_ENVIRONMENT_BOOTBLOCK
by Arthur Heymans (Code Review) 13 Oct '19

13 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35951 ) Change subject: nb/intel/nehalem: Move to C_ENVIRONMENT_BOOTBLOCK ...................................................................... nb/intel/nehalem: Move to C_ENVIRONMENT_BOOTBLOCK A few notable changes: - Microcode init is done in assembly during the CAR init. - The DCACHE_BSP_STACK_SIZE is set to 0x2000, which is the same size against which the romstage stack guards protected. This might need to be increased as in the past the stack guard mechanism reported issues, but with C_ENVIRONMENT_BOOTBLOCK the location of the stack is less forgiving for overflows. - The romstage mainboard_lpc_init() hook is removed in favor of the existing bootblock_mainboard_early_init(). Change-Id: Iccd7ceaa35db49e170bfb901bbff1c1a11223c63 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/model_2065x/Kconfig M src/cpu/intel/model_2065x/Makefile.inc D src/cpu/intel/model_2065x/bootblock.c M src/mainboard/lenovo/x201/Makefile.inc A src/mainboard/lenovo/x201/early_init.c M src/mainboard/lenovo/x201/romstage.c M src/mainboard/packardbell/ms2290/romstage.c M src/northbridge/intel/nehalem/Kconfig M src/northbridge/intel/nehalem/Makefile.inc M src/northbridge/intel/nehalem/bootblock.c M src/northbridge/intel/nehalem/romstage.c M src/southbridge/intel/ibexpeak/Kconfig M src/southbridge/intel/ibexpeak/Makefile.inc M src/southbridge/intel/ibexpeak/bootblock.c M src/southbridge/intel/ibexpeak/early_pch.c M src/southbridge/intel/ibexpeak/pch.h 16 files changed, 57 insertions(+), 107 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/35951/1 diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 897a3b4..5727511 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -23,10 +23,6 @@ select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP -config BOOTBLOCK_CPU_INIT - string - default "cpu/intel/model_2065x/bootblock.c" - config SMM_TSEG_SIZE hex default 0x800000 diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc index dde4234..1428421 100644 --- a/src/cpu/intel/model_2065x/Makefile.inc +++ b/src/cpu/intel/model_2065x/Makefile.inc @@ -15,7 +15,10 @@ cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-25-*) -cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S +bootblock-y += ../car/non-evict/cache_as_ram.S +bootblock-y += ../car/bootblock.c +bootblock-y += ../../x86/early_reset.S + postcar-y += ../car/non-evict/exit_car.S romstage-y += ../car/romstage.c diff --git a/src/cpu/intel/model_2065x/bootblock.c b/src/cpu/intel/model_2065x/bootblock.c deleted file mode 100644 index 399f5e0..0000000 --- a/src/cpu/intel/model_2065x/bootblock.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <arch/cpu.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> -#include <arch/io.h> -#include <halt.h> - -#include <cpu/intel/microcode/microcode.c> - -#if CONFIG(SOUTHBRIDGE_INTEL_IBEXPEAK) -#include <southbridge/intel/ibexpeak/pch.h> -#include "model_2065x.h" -#else -#error "CPU must be paired with Intel Ibex Peak southbridge" -#endif - -static void set_var_mtrr(unsigned int reg, unsigned int base, unsigned int size, - unsigned int type) - -{ - /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */ - /* FIXME: It only support 4G less range */ - msr_t basem, maskm; - basem.lo = base | type; - basem.hi = 0; - wrmsr(MTRR_PHYS_BASE(reg), basem); - maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; - maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; - wrmsr(MTRR_PHYS_MASK(reg), maskm); -} - -static void enable_rom_caching(void) -{ - msr_t msr; - - disable_cache(); - set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT); - enable_cache(); - - /* Enable Variable MTRRs */ - msr.hi = 0x00000000; - msr.lo = 0x00000800; - wrmsr(MTRR_DEF_TYPE_MSR, msr); -} - -static void bootblock_cpu_init(void) -{ - enable_rom_caching(); - intel_update_microcode_from_cbfs(); -} diff --git a/src/mainboard/lenovo/x201/Makefile.inc b/src/mainboard/lenovo/x201/Makefile.inc index f972356..548beff 100644 --- a/src/mainboard/lenovo/x201/Makefile.inc +++ b/src/mainboard/lenovo/x201/Makefile.inc @@ -13,6 +13,8 @@ ## GNU General Public License for more details. ## +bootblock-y += early_init.c + smm-y += dock.c smm-y += smihandler.c romstage-y += dock.c diff --git a/src/mainboard/lenovo/x201/early_init.c b/src/mainboard/lenovo/x201/early_init.c new file mode 100644 index 0000000..7383381 --- /dev/null +++ b/src/mainboard/lenovo/x201/early_init.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * Copyright (C) 2013 Vladimir Serbinenko <phcoder(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <ec/acpi/ec.h> + +void bootblock_mainboard_early_init(void) +{ + /* Enable USB Power. We need to do it early for usbdebug to work. */ + ec_set_bit(0x3b, 4); +} diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 81752e8..99875ed 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -24,12 +24,6 @@ #include <southbridge/intel/ibexpeak/pch.h> #include <northbridge/intel/nehalem/nehalem.h> -void mainboard_lpc_init(void) -{ - /* Enable USB Power. We need to do it early for usbdebug to work. */ - ec_set_bit(0x3b, 4); -} - const struct southbridge_usb_port mainboard_usb_ports[] = { /* Enabled, Current table lookup index, OC map */ { 1, IF1_557, 0 }, diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index 61e14f2..4d94329 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -22,10 +22,6 @@ #include <southbridge/intel/ibexpeak/pch.h> #include <northbridge/intel/nehalem/nehalem.h> -void mainboard_lpc_init(void) -{ -} - /* Seems copied from Lenovo Thinkpad x201, might be wrong */ const struct southbridge_usb_port mainboard_usb_ports[] = { /* Enabled, Current table lookup index, OC map */ diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index 3adf698..e37923e 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -21,6 +21,8 @@ select INTEL_GMA_ACPI select CACHE_MRC_SETTINGS select HAVE_DEBUG_RAM_SETUP + select C_ENVIRONMENT_BOOTBLOCK + select BOOTBLOCK_CONSOLE if NORTHBRIDGE_INTEL_NEHALEM @@ -48,9 +50,12 @@ hex default 0x10000 -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "northbridge/intel/nehalem/bootblock.c" +config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + help + The amount of anticipated stack usage in CAR by bootblock and + other stages. config MRC_CACHE_SIZE hex diff --git a/src/northbridge/intel/nehalem/Makefile.inc b/src/northbridge/intel/nehalem/Makefile.inc index 3b12bb5..225f0ce 100644 --- a/src/northbridge/intel/nehalem/Makefile.inc +++ b/src/northbridge/intel/nehalem/Makefile.inc @@ -15,6 +15,8 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_NEHALEM),y) +bootblock-y += bootblock.c + ramstage-y += memmap.c ramstage-y += northbridge.c ramstage-y += smi.c diff --git a/src/northbridge/intel/nehalem/bootblock.c b/src/northbridge/intel/nehalem/bootblock.c index f96ff56..46cdef0 100644 --- a/src/northbridge/intel/nehalem/bootblock.c +++ b/src/northbridge/intel/nehalem/bootblock.c @@ -12,8 +12,9 @@ */ #include <device/pci_ops.h> +#include <cpu/intel/car/bootblock.h> -static void bootblock_northbridge_init(void) +void bootblock_early_northbridge_init(void) { pci_io_write_config32(PCI_DEV(0xff, 0x00, 1), 0x50, CONFIG_MMCONF_BASE_ADDRESS | 1); pci_io_write_config32(PCI_DEV(0xff, 0x00, 1), 0x54, 0); diff --git a/src/northbridge/intel/nehalem/romstage.c b/src/northbridge/intel/nehalem/romstage.c index 54766de..8188303 100644 --- a/src/northbridge/intel/nehalem/romstage.c +++ b/src/northbridge/intel/nehalem/romstage.c @@ -45,11 +45,6 @@ /* TODO, make this configurable */ nehalem_early_initialization(NEHALEM_MOBILE); - pch_pre_console_init(); - - /* Initialize console device(s) */ - console_init(); - early_pch_init(); /* Read PM1_CNT, DON'T CLEAR IT or raminit will fail! */ diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index 00eb413..53240cb 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -51,10 +51,6 @@ int default 60 -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/intel/ibexpeak/bootblock.c" - config SERIRQ_CONTINUOUS_MODE bool default n diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc index 8c4443c..e3b5fa6 100644 --- a/src/southbridge/intel/ibexpeak/Makefile.inc +++ b/src/southbridge/intel/ibexpeak/Makefile.inc @@ -15,6 +15,8 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK),y) +bootblock-y += bootblock.c + ramstage-y += pch.c ramstage-y += azalia.c ramstage-y += lpc.c @@ -37,6 +39,7 @@ smm-y += smihandler.c me.c ../bd82x6x/me_8.x.c +bootblock-y += early_pch.c romstage-y += early_pch.c romstage-y += early_smbus.c romstage-y +=../bd82x6x/early_me.c diff --git a/src/southbridge/intel/ibexpeak/bootblock.c b/src/southbridge/intel/ibexpeak/bootblock.c index 0086fe3..6a29865 100644 --- a/src/southbridge/intel/ibexpeak/bootblock.c +++ b/src/southbridge/intel/ibexpeak/bootblock.c @@ -14,6 +14,7 @@ */ #include <device/pci_ops.h> +#include <cpu/intel/car/bootblock.h> #include "pch.h" /* @@ -32,18 +33,7 @@ static void enable_port80_on_lpc(void) { - pci_devfn_t dev = PCH_LPC_DEV; - - /* Enable port 80 POST on LPC */ - pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1); -#if 0 - RCBA32(GCS) &= (~0x04); -#else - volatile u32 *gcs = (volatile u32 *)(DEFAULT_RCBA + GCS); - u32 reg32 = *gcs; - reg32 = reg32 & ~0x04; - *gcs = reg32; -#endif + RCBA32(GCS) &= ~4; } static void set_spi_speed(void) @@ -66,12 +56,19 @@ RCBA8(0x3893) = ssfc; } -static void bootblock_southbridge_init(void) +void bootblock_early_southbridge_init(void) { enable_spi_prefetch(); + + /* Enable RCBA */ + pci_devfn_t lpc_dev = PCI_DEV(0, 0x1f, 0); + pci_write_config32(lpc_dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + enable_port80_on_lpc(); set_spi_speed(); /* Enable upper 128bytes of CMOS */ RCBA32(RC) = (1 << 2); + + pch_pre_console_init(); } diff --git a/src/southbridge/intel/ibexpeak/early_pch.c b/src/southbridge/intel/ibexpeak/early_pch.c index ccd8f74..eb6350d 100644 --- a/src/southbridge/intel/ibexpeak/early_pch.c +++ b/src/southbridge/intel/ibexpeak/early_pch.c @@ -83,7 +83,6 @@ void pch_pre_console_init(void) { early_lpc_init(); - mainboard_lpc_init(); } void early_pch_init(void) diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 1449ee9..14a355c 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -68,7 +68,6 @@ void early_thermal_init(void); void southbridge_configure_default_intmap(void); void pch_setup_cir(int chipset_type); -void mainboard_lpc_init(void); enum current_lookup_idx { IF1_F57 = 0, -- To view, visit https://review.coreboot.org/c/coreboot/+/35951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccd7ceaa35db49e170bfb901bbff1c1a11223c63 Gerrit-Change-Number: 35951 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 11

Change in coreboot[master]: [WIP]mb/lenovo/x201: Add VBOOT support
by Arthur Heymans (Code Review) 13 Oct '19

13 Oct '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35959 ) Change subject: [WIP]mb/lenovo/x201: Add VBOOT support ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/c/coreboot/+/35959/1/src/mainboard/lenovo/x201/… File src/mainboard/lenovo/x201/Kconfig: https://review.coreboot.org/c/coreboot/+/35959/1/src/mainboard/lenovo/x201/… PS1, Line 37: config VBOOT_VBNV_OFFSET : hex : default 0x2a TODO: cmos_layout. -- To view, visit https://review.coreboot.org/c/coreboot/+/35959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d524988e991457032f63a947606d1b3581de5e7 Gerrit-Change-Number: 35959 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 13 Oct 2019 12:02:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: [UNTEST]sb/intel/ibexpeak: Move some early PCH init after console init
by Arthur Heymans (Code Review) 13 Oct '19

13 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35949 ) Change subject: [UNTEST]sb/intel/ibexpeak: Move some early PCH init after console init ...................................................................... [UNTEST]sb/intel/ibexpeak: Move some early PCH init after console init Some of the initialization isn't necessary before console INIT is done. TEST: is EHCI DEBUG fine before power settings are done? Change-Id: I0c33efd98844f7188e0258cf9f90049d45145e7c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/nehalem/romstage.c M src/southbridge/intel/ibexpeak/early_pch.c M src/southbridge/intel/ibexpeak/pch.h 3 files changed, 9 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/35949/1 diff --git a/src/northbridge/intel/nehalem/romstage.c b/src/northbridge/intel/nehalem/romstage.c index c465a99..54766de 100644 --- a/src/northbridge/intel/nehalem/romstage.c +++ b/src/northbridge/intel/nehalem/romstage.c @@ -45,11 +45,13 @@ /* TODO, make this configurable */ nehalem_early_initialization(NEHALEM_MOBILE); - early_pch_init(); + pch_pre_console_init(); /* Initialize console device(s) */ console_init(); + early_pch_init(); + /* Read PM1_CNT, DON'T CLEAR IT or raminit will fail! */ reg32 = inl(DEFAULT_PMBASE + 0x04); printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); diff --git a/src/southbridge/intel/ibexpeak/early_pch.c b/src/southbridge/intel/ibexpeak/early_pch.c index 2707eb2..ccd8f74 100644 --- a/src/southbridge/intel/ibexpeak/early_pch.c +++ b/src/southbridge/intel/ibexpeak/early_pch.c @@ -80,10 +80,14 @@ RCBA32(FD2) = 1; } -void early_pch_init(void) +void pch_pre_console_init(void) { early_lpc_init(); mainboard_lpc_init(); +} + +void early_pch_init(void) +{ early_gpio_init(); /* TODO, make this configurable */ pch_setup_cir(NEHALEM_MOBILE); diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index b963237..1449ee9 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -62,6 +62,7 @@ int smbus_block_write(unsigned device, unsigned cmd, u8 bytes, const u8 *buf); #endif +void pch_pre_console_init(void); void early_pch_init(void); void early_thermal_init(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/35949 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c33efd98844f7188e0258cf9f90049d45145e7c Gerrit-Change-Number: 35949 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: drivers/pc80/rtc: Cache the cmos_layout.bin in cbmem
by Arthur Heymans (Code Review) 12 Oct '19

12 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35828 ) Change subject: drivers/pc80/rtc: Cache the cmos_layout.bin in cbmem ...................................................................... drivers/pc80/rtc: Cache the cmos_layout.bin in cbmem TODO: Move this as a cbmem lb_table record and have applications use it as such. Change-Id: Ie2ef9f623fef8a87465ddc7f85a23282f616cdec Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/commonlib/include/commonlib/cbmem_id.h M src/drivers/pc80/rtc/mc146818rtc.c M src/lib/coreboot_table.c 3 files changed, 49 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/35828/1 diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index 30bf88a..26831d7 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -77,6 +77,7 @@ #define CBMEM_ID_ROM2 0x524f4d32 #define CBMEM_ID_ROM3 0x524f4d33 #define CBMEM_ID_FMAP 0x464d4150 +#define CBMEM_ID_CMOS_LAYOUT 0x90b91aa4 #define CBMEM_ID_TO_NAME_TABLE \ { CBMEM_ID_ACPI, "ACPI " }, \ diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c index ecb02e8..b6d2f8e 100644 --- a/src/drivers/pc80/rtc/mc146818rtc.c +++ b/src/drivers/pc80/rtc/mc146818rtc.c @@ -30,6 +30,7 @@ #include <security/vboot/vbnv.h> #include <security/vboot/vbnv_layout.h> #include <types.h> +#include <cbmem.h> /* There's no way around this include guard. option_table.h is autogenerated */ #if CONFIG(USE_OPTION_TABLE) @@ -279,6 +280,50 @@ return CB_SUCCESS; } +static void layout_register_cache(int unused) +{ + const struct cbmem_entry *e; + struct mem_region_device mdev; + + if (!CONFIG(USE_OPTION_TABLE)) + return; + + e = cbmem_entry_find(CBMEM_ID_CMOS_LAYOUT); + + if (!e) + return; + + mem_region_device_ro_init(&mdev, cbmem_entry_start(e), cbmem_entry_size(e)); + car_set_var(layout_rdev, mdev.rdev); + car_set_ptr(layout_rdev_p, car_get_ptr(&layout_rdev)); + +} + +static void layout_setup_cache(int unused) +{ + struct region_device rdev; + struct cmos_option_table *cmos_layout_cbmem; + + if (!CONFIG(USE_OPTION_TABLE)) + return; + + if (locate_cmos_layout(&rdev) != CB_SUCCESS) + return; + + struct cmos_option_table *ct = rdev_mmap_full(&rdev); + cmos_layout_cbmem = cbmem_add(CBMEM_ID_CMOS_LAYOUT, ct->size); + if (cmos_layout_cbmem == NULL) + return; + + memcpy(cmos_layout_cbmem, ct, ct->size); + + layout_register_cache(unused); +} + +ROMSTAGE_CBMEM_INIT_HOOK(layout_setup_cache) +POSTCAR_CBMEM_INIT_HOOK(layout_register_cache) +RAMSTAGE_CBMEM_INIT_HOOK(layout_register_cache) + enum cb_err get_option(void *dest, const char *name) { struct cmos_option_table *ct; diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index d3576e6..8665891 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -508,14 +508,14 @@ #if CONFIG(USE_OPTION_TABLE) { struct cmos_option_table *option_table = - cbfs_boot_map_with_leak("cmos_layout.bin", - CBFS_COMPONENT_CMOS_LAYOUT, NULL); + cbmem_find(CBMEM_ID_CMOS_LAYOUT); if (option_table) { struct lb_record *rec_dest = lb_new_record(head); /* Copy the option config table, it's already a * lb_record... + * TODO just use a CMBMEM pointer... */ - memcpy(rec_dest, option_table, option_table->size); + memcpy(rec_dest, option_table, option_table->size); /* Create cmos checksum entry in coreboot table */ lb_cmos_checksum(head); } else { -- To view, visit https://review.coreboot.org/c/coreboot/+/35828 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie2ef9f623fef8a87465ddc7f85a23282f616cdec Gerrit-Change-Number: 35828 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 2

Change in coreboot[master]: drivers/pc80/rtc: Cache cmos_layout.bin region device
by Arthur Heymans (Code Review) 12 Oct '19

12 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35827 ) Change subject: drivers/pc80/rtc: Cache cmos_layout.bin region device ...................................................................... drivers/pc80/rtc: Cache cmos_layout.bin region device This avoids needing to search for the cmos_layout.bin cbfs file each time cmos_get or cmos_set is called. Change-Id: Ic7679269f28d090e9a99625d68b37e0bf02b061a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/pc80/rtc/mc146818rtc.c 1 file changed, 14 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/35827/1 diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c index 9ea5414..ecb02e8 100644 --- a/src/drivers/pc80/rtc/mc146818rtc.c +++ b/src/drivers/pc80/rtc/mc146818rtc.c @@ -17,6 +17,7 @@ #include <arch/acpi.h> #include <arch/io.h> +#include <arch/early_variables.h> #include <bcd.h> #include <fallback.h> #include <version.h> @@ -242,10 +243,19 @@ return CB_SUCCESS; } +static struct region_device layout_rdev CAR_GLOBAL; +static struct region_device *layout_rdev_p CAR_GLOBAL; + static enum cb_err locate_cmos_layout(struct region_device *rdev) { uint32_t cbfs_type = CBFS_COMPONENT_CMOS_LAYOUT; struct cbfsf fh; + struct region_device *cmos_layout_rdev = car_get_ptr(layout_rdev_p); + + if (cmos_layout_rdev) { + rdev = cmos_layout_rdev; + return CB_SUCCESS; + } /* * In case VBOOT is enabled and this function is called from SMM, @@ -261,7 +271,10 @@ return CB_CMOS_LAYOUT_NOT_FOUND; } - cbfs_file_data(rdev, &fh); + cbfs_file_data(cmos_layout_rdev, &fh); + + car_set_var(layout_rdev, *cmos_layout_rdev); + car_set_ptr(layout_rdev_p, car_get_ptr(&layout_rdev)); return CB_SUCCESS; } -- To view, visit https://review.coreboot.org/c/coreboot/+/35827 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7679269f28d090e9a99625d68b37e0bf02b061a Gerrit-Change-Number: 35827 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: intel/broadwell: Hook libgfxinit up
by Arthur Heymans (Code Review) 12 Oct '19

12 Oct '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/20100 ) Change subject: intel/broadwell: Hook libgfxinit up ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/20100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5d0c2c12b1ff8f95ba4e0223a3e9aff27547acd Gerrit-Change-Number: 20100 Gerrit-PatchSet: 6 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 12 Oct 2019 19:50:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/skylake: Fix platform reporting in console
by Michael Niewöhner (Code Review) 12 Oct '19

12 Oct '19

Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35763 ) Change subject: soc/intel/skylake: Fix platform reporting in console ...................................................................... soc/intel/skylake: Fix platform reporting in console The 100 series PCH is reported as "SKL" platform which does support SKL and KBL and thus leads to confusion. Fix the platforms reported in the console to be reported as "KBL/SKL <pch name>". Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Change-Id: Ida60f619308388adc180a5652908e5a947c17c0f --- M src/soc/intel/skylake/chip_fsp20.c 1 file changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/35763/1 diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index e46e52c..17bbc31d 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -55,7 +55,7 @@ * D29:[F0 - F7] 0xA118 - 0xA11F * D27:[F0 - F3] 0xA167 - 0xA16A */ -static const struct pcie_entry pcie_table_skl_pch_h[] = { +static const struct pcie_entry pcie_table_spt_pch_h[] = { {PCH_DEVFN_PCIE1, 8}, {PCH_DEVFN_PCIE9, 8}, {PCH_DEVFN_PCIE17, 4}, @@ -68,7 +68,7 @@ * D29:[F0 - F7] 0xA298 - 0xA29F * D27:[F0 - F7] 0xA2E7 - 0xA2EE */ -static const struct pcie_entry pcie_table_kbl_pch_h[] = { +static const struct pcie_entry pcie_table_unp_pch_h[] = { {PCH_DEVFN_PCIE1, 8}, {PCH_DEVFN_PCIE9, 8}, {PCH_DEVFN_PCIE17, 8}, @@ -80,7 +80,7 @@ * D28:[F0 - F7] 0x9D10 - 0x9D17 * D29:[F0 - F3] 0x9D18 - 0x9D1B */ -static const struct pcie_entry pcie_table_skl_pch_lp[] = { +static const struct pcie_entry pcie_table_spt_pch_lp[] = { {PCH_DEVFN_PCIE1, 8}, {PCH_DEVFN_PCIE9, 4}, }; @@ -148,17 +148,17 @@ id_mask = id & ~0xf; printk(BIOS_INFO, "Override DT after FSP-S, PCH is "); if (id_mask == (PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1 & ~0xf)) { - printk(BIOS_INFO, "KBL/SKL PCH-LP SKU\n"); - pcie_update_device_tree(&pcie_table_skl_pch_lp[0], - ARRAY_SIZE(pcie_table_skl_pch_lp)); + printk(BIOS_INFO, "KBL/SKL Sunrise Point PCH-LP SKU\n"); + pcie_update_device_tree(&pcie_table_spt_pch_lp[0], + ARRAY_SIZE(pcie_table_spt_pch_lp)); } else if (id_mask == (PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP1 & ~0xf)) { - printk(BIOS_INFO, "KBL PCH-H SKU\n"); - pcie_update_device_tree(&pcie_table_kbl_pch_h[0], - ARRAY_SIZE(pcie_table_kbl_pch_h)); + printk(BIOS_INFO, "KBL/SKL Sunrise Point PCH-H SKU\n"); + pcie_update_device_tree(&pcie_table_spt_pch_h[0], + ARRAY_SIZE(pcie_table_spt_pch_h)); } else if (id_mask == (PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP1 & ~0xf)) { - printk(BIOS_INFO, "SKL PCH-H SKU\n"); - pcie_update_device_tree(&pcie_table_skl_pch_h[0], - ARRAY_SIZE(pcie_table_skl_pch_h)); + printk(BIOS_INFO, "KBL/SKL Union Point PCH-H SKU\n"); + pcie_update_device_tree(&pcie_table_unp_pch_h[0], + ARRAY_SIZE(pcie_table_unp_pch_h)); } else { printk(BIOS_ERR, "[BUG] PCIE Root Port id 0x%x" " is not found\n", id); -- To view, visit https://review.coreboot.org/c/coreboot/+/35763 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida60f619308388adc180a5652908e5a947c17c0f Gerrit-Change-Number: 35763 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-MessageType: newchange

3 28

Change in coreboot[master]: intel/broadwell: Hook libgfxinit up
by Nico Huber (Code Review) 12 Oct '19

12 Oct '19

Hello Patrick Rudolph, Matt DeVillier, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/20100 to look at the new patch set (#6). Change subject: intel/broadwell: Hook libgfxinit up ...................................................................... intel/broadwell: Hook libgfxinit up As VGA_ROM_RUN and libgfxinit are mutually exclusive in Kconfig, we don't have to guard all the VGA BIOS if's and can assume gfx_get_init_done() returns 0 until all the quirks are handled. Then, we can run libgfxinit. Change-Id: Id5d0c2c12b1ff8f95ba4e0223a3e9aff27547acd Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/intel/broadwell/igd.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/20100/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/20100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5d0c2c12b1ff8f95ba4e0223a3e9aff27547acd Gerrit-Change-Number: 20100 Gerrit-PatchSet: 6 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: device/pci_device.c: Use verified boot to check oprom
by Frans Hendriks (Code Review) 12 Oct '19

12 Oct '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30810 Change subject: device/pci_device.c: Use verified boot to check oprom ...................................................................... device/pci_device.c: Use verified boot to check oprom Before oprom is executed, no check is performed if rom passes verification. Add call to verified_boot_should_run_oprom() to verify the oprom. BUG=N/A TEST=Created verified binary and verify logging on Portwell PQ-M107 Change-Id: Iec5092e85d34940ea3a3bb1192ea49f3bc3e5b27 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/device/pci_device.c M src/include/device/pci_rom.h 2 files changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/30810/1 diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 82033a6..40012f9 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -16,6 +16,7 @@ * Copyright (C) 2005-2009 coresystems GmbH * (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -802,6 +803,10 @@ if (!should_run_oprom(dev)) return; + if (IS_ENABLED(CONFIG_VERIFIED_BOOT)) + if (!verified_boot_should_run_oprom(rom)) + return; + run_bios(dev, (unsigned long)ram); gfx_set_init_done(1); printk(BIOS_DEBUG, "VGA Option ROM was run\n"); diff --git a/src/include/device/pci_rom.h b/src/include/device/pci_rom.h index a4aa52a..865fea3 100644 --- a/src/include/device/pci_rom.h +++ b/src/include/device/pci_rom.h @@ -1,3 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + #ifndef PCI_ROM_H #define PCI_ROM_H #include <endian.h> @@ -47,4 +63,5 @@ u32 map_oprom_vendev(u32 vendev); +int verified_boot_should_run_oprom(struct rom_header *rom_header); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/30810 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec5092e85d34940ea3a3bb1192ea49f3bc3e5b27 Gerrit-Change-Number: 30810 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

8 12

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2019