coreboot-gerrit October 2019

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Change in ...coreboot[master]: [UNTESTED]cpu/intel/model_1067x/mp_init: Implement get_microcode_info
by Arthur Heymans (Code Review) 13 Oct '19

13 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31600 Change subject: [UNTESTED]cpu/intel/model_1067x/mp_init: Implement get_microcode_info ...................................................................... [UNTESTED]cpu/intel/model_1067x/mp_init: Implement get_microcode_info Fixes microcode not being updated. Change-Id: Iee7a3897362b63bc6d7b9827da47c1cb24135278 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/model_1067x/mp_init.c 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/31600/1 diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c index acd56c8..1a6110b 100644 --- a/src/cpu/intel/model_1067x/mp_init.c +++ b/src/cpu/intel/model_1067x/mp_init.c @@ -49,6 +49,13 @@ smm_initialize(); } +static void get_microcode_info(const void **microcode, int *parallel) +{ + microcode_patch = intel_microcode_find(); + *microcode = microcode_patch; + *parallel = 1; +} + #define SMRR_SUPPORTED (1 << 11) static void per_cpu_smm_trigger(void) @@ -98,6 +105,7 @@ .pre_mp_init = pre_mp_init, .get_cpu_count = get_cpu_count, .get_smm_info = smm_info, + .get_microcode_info = get_microcode_info, .pre_mp_smm_init = pre_mp_smm_init, .per_cpu_smm_trigger = per_cpu_smm_trigger, .relocation_handler = smm_relocation_handler, -- To view, visit https://review.coreboot.org/c/coreboot/+/31600 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee7a3897362b63bc6d7b9827da47c1cb24135278 Gerrit-Change-Number: 31600 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: cpu/intel/common: Compute the TSC tick freq based on FSB
by Arthur Heymans (Code Review) 13 Oct '19

13 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31203 Change subject: cpu/intel/common: Compute the TSC tick freq based on FSB ...................................................................... cpu/intel/common: Compute the TSC tick freq based on FSB This allows the cbmem utility to compute timestamps based on coreboot tables without relying on other userspace components. Change-Id: Ie87adec950dc51f4f873c0d852a325b3ff9b18bf Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/common/fsb.c 1 file changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/31203/1 diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c index 1f7c391..cf258bd 100644 --- a/src/cpu/intel/common/fsb.c +++ b/src/cpu/intel/common/fsb.c @@ -11,7 +11,9 @@ * GNU General Public License for more details. */ +#include <console/console.h> #include <cpu/cpu.h> +#include <cpu/x86/tsc.h> #include <cpu/x86/msr.h> #include <cpu/intel/speedstep.h> #include <cpu/intel/fsb.h> @@ -83,3 +85,27 @@ printk(BIOS_ERR, "FSB not supported or not found\n"); return -1; } + +unsigned long tsc_freq_mhz(void) +{ + msr_t msr; + unsigned long multiplier; + struct cpuinfo_x86 c; + + get_fms(&c, cpuid_eax(1)); + + msr = rdmsr(IA32_PLATFORM_ID); + multiplier = (msr.lo & SPEEDSTEP_RATIO_VALUE_MASK) + >> SPEEDSTEP_RATIO_SHIFT; + if ((c.x86 == 6 && c.x86_model == 0xe) || (c.x86 == 0xf)) { + /* Looks like Yonah CPUs don't have the frequency ratio in + IA32_PLATFORM_ID. Use IA32_PERF_STATUS instead, the reading + should be reliable as those CPUs don't have turbo mode. */ + msr = rdmsr(IA32_PERF_STATUS); + multiplier = (msr.hi & SPEEDSTEP_RATIO_VALUE_MASK) + >> SPEEDSTEP_RATIO_SHIFT; + } + + printk(BIOS_DEBUG, "CPU freq %ld\n", multiplier * get_ia32_fsb()); + return multiplier * get_ia32_fsb(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/31203 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie87adec950dc51f4f873c0d852a325b3ff9b18bf Gerrit-Change-Number: 31203 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: arch/x86/timestamp.c: Don't depend on CONFIG_TSC_CONSTANT_RATE
by Arthur Heymans (Code Review) 13 Oct '19

13 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31202 Change subject: arch/x86/timestamp.c: Don't depend on CONFIG_TSC_CONSTANT_RATE ...................................................................... arch/x86/timestamp.c: Don't depend on CONFIG_TSC_CONSTANT_RATE timestamp_tick_freq_mhz() is used to populate the coreboot tables which cbmem can use to determine timestamps without needing userspace tools to get the TSC frequency rate. CONFIG_TSC_CONSTANT_RATE depends on CONFIG_UDELAY_TSC which is not the case on all targets that could still make use of this functionality. Change-Id: I8c34eb811e27d2a91ccf1ca6f48a638da5f6cfd9 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/timestamp.c 1 file changed, 13 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/31202/1 diff --git a/src/arch/x86/timestamp.c b/src/arch/x86/timestamp.c index b5257c4..f7b5541 100644 --- a/src/arch/x86/timestamp.c +++ b/src/arch/x86/timestamp.c @@ -21,14 +21,20 @@ return rdtscll(); } +/* We want build to fail on targets with CONFIG_TSC_CONSTANT_RATE + if an implementation is lacking since it used to compute udelays. + FIXME: provide an implementation on every target to get rid of this.*/ +#if !IS_ENABLED(CONFIG_TSC_CONSTANT_RATE) +unsigned long __weak tsc_freq_mhz(void) +{ + /* Default to not knowing TSC frequency. cbmem will have to fallback + * on trying to determine it in userspace. */ + return 0; +} +#endif + int timestamp_tick_freq_mhz(void) { /* Chipsets that have a constant TSC provide this value correctly. */ - if (IS_ENABLED(CONFIG_TSC_CONSTANT_RATE)) - return tsc_freq_mhz(); - - /* Filling tick_freq_mhz = 0 in timestamps-table will trigger - * userspace utility to try deduce it from the running system. - */ - return 0; + return tsc_freq_mhz(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/31202 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c34eb811e27d2a91ccf1ca6f48a638da5f6cfd9 Gerrit-Change-Number: 31202 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/intel/i82801gx: Add a mb hook to override the SPI opmenu
by Arthur Heymans (Code Review) 13 Oct '19

13 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30888 Change subject: sb/intel/i82801gx: Add a mb hook to override the SPI opmenu ...................................................................... sb/intel/i82801gx: Add a mb hook to override the SPI opmenu By default the SPI configuration gets locked down, but the default opmenu setting could not work with some SPI flashes. This fixes unmodified flashrom not being able to flash the Thinkpad X60 with CONFIG_INTEL_CHIPSET_LOCKDOWN set. Change-Id: I43e6abcc5c761720b31bc023016cb71b860e76ed Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/x60/mainboard.c M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/i82801gx/lpc.c 3 files changed, 126 insertions(+), 47 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/30888/1 diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index 5cf0d26..f770cf9 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -22,10 +22,12 @@ #include <arch/io.h> #include <ec/acpi/ec.h> #include <northbridge/intel/i945/i945.h> +#include <southbridge/intel/i82801gx/i82801gx.h> #include "dock.h" #include <drivers/intel/gma/int15.h> #include <drivers/lenovo/lenovo.h> #include <arch/acpigen.h> +#include <spi_flash.h> #define PANEL INT15_5F35_CL_DISPLAY_DEFAULT @@ -68,6 +70,60 @@ return ARRAY_SIZE(cst_entries); } +/* + * SPI lockdown configuration for SST25VF016B. + */ +#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ +#define SPI_OPTYPE_0 0x01 /* Write, no address */ + +#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ +#define SPI_OPTYPE_1 0x03 /* Write, address required */ + +#define SPI_OPMENU_2 0x03 /* READ: Read Data */ +#define SPI_OPTYPE_2 0x02 /* Read, address required */ + +#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ +#define SPI_OPTYPE_3 0x00 /* Read, no address */ + +#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ +#define SPI_OPTYPE_4 0x03 /* Write, address required */ + +#define SPI_OPMENU_5 0x9f /* RDID: Read ID */ +#define SPI_OPTYPE_5 0x00 /* Read, no address */ + +#define SPI_OPMENU_6 0xad /* Auto Address Increment Word Program */ +#define SPI_OPTYPE_6 0x01 /* Write, address required */ + +#define SPI_OPMENU_7 0x04 /* Write Disable */ +#define SPI_OPTYPE_7 0x01 /* Write, no address */ + +#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ +#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ + (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ + (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ + (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0 << 0)) +#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ + (SPI_OPMENU_5 << 8) | (SPI_OPMENU_4 << 0)) +#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ + (SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0)) +#define SPI_VSCC (WG_64_BYTE | EO(0x20) | BES_4_KB) + +static const struct spi_config spi_config_sst = { + .preop = SPI_OPPREFIX, + .optype = SPI_OPTYPE, + .opmenu = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER }, +}; + + +void mainboard_override_spi_config(struct spi_config *cfg) +{ + const struct spi_flash *flash = boot_device_spi_flash(); + + if (strcmp(flash->name, "SST25VF016B") == 0) { + memcpy(cfg, &spi_config_sst, sizeof(*cfg)); + } +} + static void mainboard_init(struct device *dev) { struct device *idedev, *sdhci_dev; diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 9fd9fd6..0a32201 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -364,51 +364,16 @@ #define C3_RES 0x54 #define TCO1_CNT 0x68 -/* SPIBAR - * - * SPI Opcode Menu setup for SPIBAR lockdown - * should support most common flash chips. +/* + * SPI lockdown configuration. */ +struct spi_config { + uint16_t preop; + uint16_t optype; + uint32_t opmenu[2]; +}; -#define PREOP 0x54 -#define OPTYPE 0x56 -#define OPMENU 0x58 - -#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ -#define SPI_OPTYPE_0 0x01 /* Write, no address */ - -#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ -#define SPI_OPTYPE_1 0x03 /* Write, address required */ - -#define SPI_OPMENU_2 0x03 /* READ: Read Data */ -#define SPI_OPTYPE_2 0x02 /* Read, address required */ - -#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ -#define SPI_OPTYPE_3 0x00 /* Read, no address */ - -#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ -#define SPI_OPTYPE_4 0x03 /* Write, address required */ - -#define SPI_OPMENU_5 0x9f /* RDID: Read ID */ -#define SPI_OPTYPE_5 0x00 /* Read, no address */ - -#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ -#define SPI_OPTYPE_6 0x03 /* Write, address required */ - -#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ -#define SPI_OPTYPE_7 0x02 /* Read, address required */ - -#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ - (SPI_OPMENU_5 << 8) | SPI_OPMENU_4) -#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ - (SPI_OPMENU_1 << 8) | SPI_OPMENU_0) - -#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ - (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ - (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ - (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0)) - -#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ +void mainboard_override_spi_config(struct spi_config *cfg); #endif /* __ACPI__ */ #endif /* SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H */ diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index e8cfc74..175b33a 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -645,21 +645,79 @@ } } +/* SPIBAR + * + * SPI Opcode Menu setup for SPIBAR lockdown + * should support most common flash chips. + */ + +#define PREOP 0x54 +#define OPTYPE 0x56 +#define OPMENU 0x58 + +#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ +#define SPI_OPTYPE_0 0x01 /* Write, no address */ + +#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ +#define SPI_OPTYPE_1 0x03 /* Write, address required */ + +#define SPI_OPMENU_2 0x03 /* READ: Read Data */ +#define SPI_OPTYPE_2 0x02 /* Read, address required */ + +#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ +#define SPI_OPTYPE_3 0x00 /* Read, no address */ + +#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ +#define SPI_OPTYPE_4 0x03 /* Write, address required */ + +#define SPI_OPMENU_5 0x9f /* RDID: Read ID */ +#define SPI_OPTYPE_5 0x00 /* Read, no address */ + +#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ +#define SPI_OPTYPE_6 0x03 /* Write, address required */ + +#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ +#define SPI_OPTYPE_7 0x02 /* Read, address required */ + +#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ + (SPI_OPMENU_5 << 8) | SPI_OPMENU_4) +#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ + (SPI_OPMENU_1 << 8) | SPI_OPMENU_0) + +#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ + (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ + (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ + (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0)) + +#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ + #define SPIBAR16(x) RCBA16(0x3020 + x) #define SPIBAR32(x) RCBA32(0x3020 + x) +void __weak mainboard_override_spi_config(struct spi_config *cfg) +{ +} + static void lpc_final(struct device *dev) { u16 tco1_cnt; + struct spi_config spi_cfg; if (!IS_ENABLED(CONFIG_INTEL_CHIPSET_LOCKDOWN)) return; - SPIBAR16(PREOP) = SPI_OPPREFIX; + spi_cfg.preop = SPI_OPPREFIX; + spi_cfg.optype = SPI_OPTYPE; + spi_cfg.opmenu[0] = SPI_OPMENU_LOWER; + spi_cfg.opmenu[1] = SPI_OPMENU_UPPER; + + mainboard_override_spi_config(&spi_cfg); + + SPIBAR16(PREOP) = spi_cfg.preop; /* Set SPI opcode menu */ - SPIBAR16(OPTYPE) = SPI_OPTYPE; - SPIBAR32(OPMENU) = SPI_OPMENU_LOWER; - SPIBAR32(OPMENU + 4) = SPI_OPMENU_UPPER; + SPIBAR16(OPTYPE) = spi_cfg.optype; + SPIBAR32(OPMENU) = spi_cfg.opmenu[0]; + SPIBAR32(OPMENU + 4) = spi_cfg.opmenu[1]; /* Lock SPIBAR */ SPIBAR16(0) = SPIBAR16(0) | (1 << 15); -- To view, visit https://review.coreboot.org/c/coreboot/+/30888 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43e6abcc5c761720b31bc023016cb71b860e76ed Gerrit-Change-Number: 30888 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP]cpu/x86/lapic: Link apic_timer.c into SMM
by Arthur Heymans (Code Review) 13 Oct '19

13 Oct '19

Arthur Heymans has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/30020 ) Change subject: [WIP]cpu/x86/lapic: Link apic_timer.c into SMM ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/30020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic14919f89b226b4d5185e49ae857e7dd61bbccce Gerrit-Change-Number: 30020 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: sb/intel/common/smihandler: Compile test CONFIG_ELOG_GSMI
by Arthur Heymans (Code Review) 13 Oct '19

13 Oct '19

Arthur Heymans has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/30013 ) Change subject: sb/intel/common/smihandler: Compile test CONFIG_ELOG_GSMI ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/30013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2491c14c4fd45c74dbf584a07d6d3bf5ede7f69c Gerrit-Change-Number: 30013 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: [WIP]util/autoport: Change the order in which chips and PCI devices a...
by Arthur Heymans (Code Review) 13 Oct '19

13 Oct '19

Arthur Heymans has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/27361 ) Change subject: [WIP]util/autoport: Change the order in which chips and PCI devices are added ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/27361 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4c7c43dd209678aa3d37fe75a8d010192ae2803 Gerrit-Change-Number: 27361 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: [TESTONLY]nb/intel/i945: Only disable VGA decode on IGD
by Arthur Heymans (Code Review) 13 Oct '19

13 Oct '19

Arthur Heymans has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/27985 ) Change subject: [TESTONLY]nb/intel/i945: Only disable VGA decode on IGD ...................................................................... Abandoned No PEG and IGD are mutually exclusive on i945 it seems. -- To view, visit https://review.coreboot.org/c/coreboot/+/27985 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f1e1ab349b3e4bcb4d49da4b6d091e57243ee8f Gerrit-Change-Number: 27985 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: abandon

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Change in coreboot[master]: drivers/mrc_cache: Allow non ChromeOS targets to write protect MRC_CACHE
by Arthur Heymans (Code Review) 13 Oct '19

13 Oct '19

Arthur Heymans has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/25552 ) Change subject: drivers/mrc_cache: Allow non ChromeOS targets to write protect MRC_CACHE ...................................................................... Abandoned Might resume this later, but abandoning for now. -- To view, visit https://review.coreboot.org/c/coreboot/+/25552 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7536e323c87d63deab59ed90115f2d83f74858e0 Gerrit-Change-Number: 25552 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: util/abuild: Allow use of payloads when not providing a configfile
by Arthur Heymans (Code Review) 13 Oct '19

13 Oct '19

Arthur Heymans has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/23676 ) Change subject: util/abuild: Allow use of payloads when not providing a configfile ...................................................................... Abandoned Too old patch... -- To view, visit https://review.coreboot.org/c/coreboot/+/23676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4368d9609bceb4cf7edb76c10bc0af0cdeb76958 Gerrit-Change-Number: 23676 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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coreboot-gerrit October 2019