coreboot-gerrit October 2019

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Change in coreboot[master]: x86 gdb: Extend GDB stub with CPUID command
by Werner Zeh (Code Review) 14 Oct '19

14 Oct '19

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36018 ) Change subject: x86 gdb: Extend GDB stub with CPUID command ...................................................................... x86 gdb: Extend GDB stub with CPUID command Add CPUID command to GDB stub. NOT FOR MERGE!!! Change-Id: I49a18c1fff01a139352acbac98a927f213ebcaa6 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/arch/x86/exception.c 1 file changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/36018/1 diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c index 7d10c3e..4759015 100644 --- a/src/arch/x86/exception.c +++ b/src/arch/x86/exception.c @@ -602,6 +602,26 @@ break; case 'q': /* query */ break; + case 'u': + /* uAA..AA: Execute CPUID with EAX given by AA..AA. */ + ptr = &in_buffer[1]; + if (parse_ulong(&ptr, &addr) && + (*(ptr++) == ':')) { + char *out_ptr = out_buffer; + struct cpuid_result result; + + result = cpuid(addr); + copy_to_hex(out_ptr, (void *)&(result.eax), 4); + out_ptr += (4 << 1); + copy_to_hex(out_ptr, (void *)&(result.ebx), 4); + out_ptr += (4 << 1); + copy_to_hex(out_ptr, (void *)&(result.ecx), 4); + out_ptr += (4 << 1); + copy_to_hex(out_ptr, (void *)&(result.edx), 4); + out_ptr += (4 << 1); + } else + memcpy(out_buffer, "E07", 4); + break; case 'z': /* z0AAAA,LLLL remove memory breakpoint */ /* z1AAAA,LLLL remove hardware breakpoint */ /* z2AAAA,LLLL remove write watchpoint */ -- To view, visit https://review.coreboot.org/c/coreboot/+/36018 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49a18c1fff01a139352acbac98a927f213ebcaa6 Gerrit-Change-Number: 36018 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: x86 gdb: Extend GDB stub with MSR read and write commands
by Werner Zeh (Code Review) 14 Oct '19

14 Oct '19

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36017 ) Change subject: x86 gdb: Extend GDB stub with MSR read and write commands ...................................................................... x86 gdb: Extend GDB stub with MSR read and write commands Add commands to read and write MSRs on x86. NOT FOR MERGE!!! Change-Id: I4addf44305dbcfb06c7573dc30541038356f2c33 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/arch/x86/exception.c 1 file changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/36017/1 diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c index c2783d5..7d10c3e 100644 --- a/src/arch/x86/exception.c +++ b/src/arch/x86/exception.c @@ -22,6 +22,7 @@ #include <stdint.h> #include <string.h> #include <arch/io.h> +#include <cpu/x86/msr.h> #if CONFIG(GDB_STUB) @@ -417,6 +418,7 @@ while (1) { unsigned long addr, length, val; char *ptr; + msr_t msr; out_buffer[0] = '\0'; out_buffer[1] = '\0'; if (!get_packet(in_buffer)) @@ -428,6 +430,37 @@ out_buffer[2] = hexchars[signo & 0xf]; out_buffer[3] = '\0'; break; + case 'e': + /* eAA..AA: Read MSR given by AA..AA. */ + ptr = &in_buffer[1]; + if (parse_ulong(&ptr, &addr) && + (*(ptr++) == ':')) { + char *out_buf_ptr = out_buffer; + + msr = rdmsr(addr); + copy_to_hex(out_buf_ptr, (void *)&(msr.hi), 4); + out_buf_ptr += (4 << 1); + copy_to_hex(out_buf_ptr, (void *)&(msr.lo), 4); + } else + memcpy(out_buffer, "E05", 4); + break; + case 'E': + /* EAA..AA,HHHH,LLLL: Write MSR given by AA..AA. */ + /* Put HHHH into high portion of the 64 bit */ + /* and LLLL into the low portion. */ + ptr = &in_buffer[1]; + if (parse_ulong(&ptr, &addr) && + (*(ptr++) == ',') && + parse_ulong(&ptr, (unsigned long *) &msr.hi) && + (*(ptr++) == ',') && + parse_ulong(&ptr, (unsigned long *) &msr.lo) && + (*(ptr++) == ':')) { + wrmsr(addr, msr); + memcpy(out_buffer, "OK", 3); + } else + memcpy(out_buffer, "E06", 4); + break; + case 'g': /* return the value of the CPU registers */ copy_to_hex(out_buffer, &gdb_stub_registers, sizeof(gdb_stub_registers)); -- To view, visit https://review.coreboot.org/c/coreboot/+/36017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4addf44305dbcfb06c7573dc30541038356f2c33 Gerrit-Change-Number: 36017 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mc_apl3: Enable UART for GDB debugging
by Werner Zeh (Code Review) 14 Oct '19

14 Oct '19

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36026 ) Change subject: mc_apl3: Enable UART for GDB debugging ...................................................................... mc_apl3: Enable UART for GDB debugging Change-Id: I69dba6a8cee0b11c07b553e2960871ee5c30e8cd Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/romstage.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/36026/1 diff --git a/src/mainboard/siemens/mc_apl1/romstage.c b/src/mainboard/siemens/mc_apl1/romstage.c index bd21dd1..9c992f7 100644 --- a/src/mainboard/siemens/mc_apl1/romstage.c +++ b/src/mainboard/siemens/mc_apl1/romstage.c @@ -145,13 +145,15 @@ #define FPGA_TEMP_BAR0 0xf7000000 #if CONFIG(BOARD_SIEMENS_MC_APL2) #define CUPER_ROOT_DEV (PCI_DEV(0, 0x13, 0x01)) +#elif CONFIG(BOARD_SIEMENS_MC_APL3) +#define CUPER_ROOT_DEV (PCI_DEV(0, 0x13, 0x03)) #endif #define CUPER_PCI_DEV (PCI_DEV(FPGA_PCI_BUS, 0, 0)) void mainboard_save_dimm_info(void) { uint32_t reg; - if (CONFIG(BOARD_SIEMENS_MC_APL2)) { + if (CONFIG(BOARD_SIEMENS_MC_APL2) || CONFIG(BOARD_SIEMENS_MC_APL3)) { /* First set up root port bridge to get access to the FPGA. */ /* Set secondary bus temporary. */ pci_write_config32(CUPER_ROOT_DEV, PCI_PRIMARY_BUS, -- To view, visit https://review.coreboot.org/c/coreboot/+/36026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69dba6a8cee0b11c07b553e2960871ee5c30e8cd Gerrit-Change-Number: 36026 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mc_apl2: Enable UART for GDB debugging
by Werner Zeh (Code Review) 14 Oct '19

14 Oct '19

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36025 ) Change subject: mc_apl2: Enable UART for GDB debugging ...................................................................... mc_apl2: Enable UART for GDB debugging Change-Id: Idd4504d8f11aa78196d6d87d0fa13338b708f53e Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/romstage.c 1 file changed, 54 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/36025/1 diff --git a/src/mainboard/siemens/mc_apl1/romstage.c b/src/mainboard/siemens/mc_apl1/romstage.c index 1483636..bd21dd1 100644 --- a/src/mainboard/siemens/mc_apl1/romstage.c +++ b/src/mainboard/siemens/mc_apl1/romstage.c @@ -127,3 +127,57 @@ memupd->FspmConfig.MrcDataSaving = 0x0; memupd->FspmConfig.MrcFastBoot = 0x1; } +#if CONFIG(GDB_STUB) +#include <device/device.h> +#include <device/pci.h> +#include <arch/io.h> +#include <soc/romstage.h> + +/* + * We need a way to hook in right after the romstage has been finished + * to enable the UART on CUPER. This must happen for sure before ramstage + * starts and the code is mainboard dependent. Due to FSP 2.0 there are no + * other mainboard-hooks for romstage beside the ones for DRAM parameter setup + * and this one. So use this hook now for the needed code. + * This is noting to release, just for internal usage. + */ +#define FPGA_PCI_BUS 1 +#define FPGA_TEMP_BAR0 0xf7000000 +#if CONFIG(BOARD_SIEMENS_MC_APL2) +#define CUPER_ROOT_DEV (PCI_DEV(0, 0x13, 0x01)) +#endif +#define CUPER_PCI_DEV (PCI_DEV(FPGA_PCI_BUS, 0, 0)) +void mainboard_save_dimm_info(void) +{ + uint32_t reg; + + if (CONFIG(BOARD_SIEMENS_MC_APL2)) { + /* First set up root port bridge to get access to the FPGA. */ + /* Set secondary bus temporary. */ + pci_write_config32(CUPER_ROOT_DEV, PCI_PRIMARY_BUS, + FPGA_PCI_BUS << 16 | FPGA_PCI_BUS << 8); + /* Define an address window to forward to the secondary bus. */ + pci_write_config32(CUPER_ROOT_DEV, PCI_MEMORY_BASE, + (FPGA_TEMP_BAR0 | (FPGA_TEMP_BAR0 >> 16))); + /* Enable memory mapped transfers */ + pci_write_config32(CUPER_ROOT_DEV, PCI_COMMAND, + PCI_COMMAND_MEMORY); + /* Now the FPGA is visible on bus 1, dev 0, function 0. */ + pci_write_config32(CUPER_PCI_DEV, PCI_BASE_ADDRESS_0, + FPGA_TEMP_BAR0); + pci_write_config32(CUPER_PCI_DEV, PCI_COMMAND, + PCI_COMMAND_MEMORY); + /* Now we can reach MMIO mapped registers in CUPER */ + reg = read32((void *)(FPGA_TEMP_BAR0 + 0xbc)); + reg |= (1 << 10); + write32((void *)(FPGA_TEMP_BAR0 + 0xbc), reg); + /* Now delete all the changes made in config space so that + * the PCI enumerator can do its work. */ + pci_write_config32(CUPER_PCI_DEV, PCI_BASE_ADDRESS_0, 0); + pci_write_config32(CUPER_PCI_DEV, PCI_COMMAND, 0); + pci_write_config32(CUPER_ROOT_DEV, PCI_PRIMARY_BUS, 0x0); + pci_write_config32(CUPER_ROOT_DEV, PCI_MEMORY_BASE, 0); + pci_write_config32(CUPER_ROOT_DEV, PCI_COMMAND, 0); + } +} +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/36025 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd4504d8f11aa78196d6d87d0fa13338b708f53e Gerrit-Change-Number: 36025 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mc_bdx1: Enable UART for GDB debugging
by Werner Zeh (Code Review) 14 Oct '19

14 Oct '19

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36023 ) Change subject: mc_bdx1: Enable UART for GDB debugging ...................................................................... mc_bdx1: Enable UART for GDB debugging Change-Id: I724402b51295be85500a79e21a4379ed43903e26 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_bdx1/romstage.c 1 file changed, 43 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/36023/1 diff --git a/src/mainboard/siemens/mc_bdx1/romstage.c b/src/mainboard/siemens/mc_bdx1/romstage.c index eec8f04..8051200 100644 --- a/src/mainboard/siemens/mc_bdx1/romstage.c +++ b/src/mainboard/siemens/mc_bdx1/romstage.c @@ -20,7 +20,47 @@ #include <drivers/intel/fsp1_0/fsp_util.h> #include <soc/gpio.h> #include "gpio.h" +#if IS_ENABLED(CONFIG_GDB_STUB) +#include <device/device.h> +#include <device/pci.h> +#include <arch/io.h> +#define FPGA_PCI_BUS 1 +#define FPGA_TEMP_BAR0 0xf7000000 + + +static void mainbaord_enable_gdb_stub(void) +{ + uint32_t reg; + + /* First set up root port bridge to get access to the FPGA. */ + /* Set secondary bus temporary. */ + pci_write_config32(PCI_DEV(0, 0x1c, 0x03), PCI_PRIMARY_BUS, + FPGA_PCI_BUS << 16 | FPGA_PCI_BUS << 8); + /* Define an address window to forward to the secondary bus. */ + pci_write_config32(PCI_DEV(0, 0x1c, 0x03), PCI_MEMORY_BASE, + (FPGA_TEMP_BAR0 | (FPGA_TEMP_BAR0 >> 16))); + /* Enable memory mapped transfers */ + pci_write_config32(PCI_DEV(0, 0x1c, 0x03), PCI_COMMAND, + PCI_COMMAND_MEMORY); + /* Now the FPGA is visible on bus 1, dev 0, function 0. */ + pci_write_config32(PCI_DEV(FPGA_PCI_BUS, 0, 0), PCI_BASE_ADDRESS_0, + FPGA_TEMP_BAR0); + pci_write_config32(PCI_DEV(FPGA_PCI_BUS, 0, 0), PCI_COMMAND, + PCI_COMMAND_MEMORY); + /* Now we can reach MMIO mapped registers in CUPER */ + reg = read32((void *)(FPGA_TEMP_BAR0 + 0xbc)); + reg |= (1 << 10); + write32((void *)(FPGA_TEMP_BAR0 + 0xbc), reg); + /* Now delete all the changes made in config space so that + the PCI enumerator can do it's work. */ + pci_write_config32(PCI_DEV(FPGA_PCI_BUS, 0, 0), PCI_BASE_ADDRESS_0, 0); + pci_write_config32(PCI_DEV(FPGA_PCI_BUS, 0, 0), PCI_COMMAND, 0); + pci_write_config32(PCI_DEV(0, 0x1c, 0x03), PCI_PRIMARY_BUS, 0x0); + pci_write_config32(PCI_DEV(0, 0x1c, 0x03), PCI_MEMORY_BASE, 0); + pci_write_config32(PCI_DEV(0, 0x1c, 0x03), PCI_COMMAND, 0); +} +#endif /** * /brief mainboard call for setup that needs to be done before fsp init * @@ -36,7 +76,9 @@ */ void late_mainboard_romstage_entry(void) { - +#if (IS_ENABLED(CONFIG_GDB_STUB)) + mainbaord_enable_gdb_stub(); +#endif } /** -- To view, visit https://review.coreboot.org/c/coreboot/+/36023 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I724402b51295be85500a79e21a4379ed43903e26 Gerrit-Change-Number: 36023 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: x86 gdb: Use copy_to_hex_{word, long} for 16 and 32 bit read
by Werner Zeh (Code Review) 14 Oct '19

14 Oct '19

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36022 ) Change subject: x86 gdb: Use copy_to_hex_{word, long} for 16 and 32 bit read ...................................................................... x86 gdb: Use copy_to_hex_{word, long} for 16 and 32 bit read I/O read can be done in 8, 16 and 32 bit. To handle the 16 and 32 bit wide read access right, use copy_to_hex_word() and copy_to_hex_long() respectively. The same applies to MSR read. Here we have two 32 bit values which now printed with copy_to_hex_long(). Change-Id: I1f4ab7a0135baac1fd324ced0e501ac2f096e1c4 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/arch/x86/exception.c 1 file changed, 22 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/36022/1 diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c index b1689cc..ae7e57e 100644 --- a/src/arch/x86/exception.c +++ b/src/arch/x86/exception.c @@ -609,9 +609,13 @@ char *out_buf_ptr = out_buffer; msr = rdmsr(addr); - copy_to_hex(out_buf_ptr, (void *)&(msr.hi), 4); + copy_to_hex_long(out_buf_ptr, + (void *)&(msr.hi), + 1); out_buf_ptr += (4 << 1); - copy_to_hex(out_buf_ptr, (void *)&(msr.lo), 4); + copy_to_hex_long(out_buf_ptr, + (void *)&(msr.lo), + 1); } else memcpy(out_buffer, "E05", 4); break; @@ -726,43 +730,35 @@ (*(ptr++) == ',') && ((*(ptr) == 'b') || (*(ptr) == 'w') || (*(ptr) == 'l'))) { - char width = *(ptr++), len; + char width = *(ptr++); char *out_buf_ptr = out_buffer; - unsigned long i, tmp; + unsigned long i; /* Read desired amount of I/O ports */ for (i = 0; i < length; i++) { switch (width) { case 'l': - tmp = inl(addr); - /* Rotate the byte order as */ - /* copy_to_hex() works on a */ - /* byte stream. */ - val = (((tmp >> 24) & 0xff) | - (((tmp >> 16) & 0xff) << 8) | - (((tmp >> 8) & 0xff) << 16) | - ((tmp & 0xff) << 24)); - len = 4; + val = inl(addr); + copy_to_hex_long(out_buf_ptr, + (void *)&val, 1); + out_buf_ptr += 4 << 1; + addr += 4; break; case 'w': - tmp = inw(addr); - /* Rotate the byte order as */ - /* copy_to_hex() works on a */ - /* byte stream. */ - val = (((tmp >> 8) & 0xff) | - ((tmp & 0xff) << 8)); - len = 2; + val = inw(addr); + copy_to_hex_word(out_buf_ptr, + (void *)&val, 1); + out_buf_ptr += 2 << 1; + addr += 2; break; case 'b': default: val = inb(addr); - len = 1; + copy_to_hex(out_buf_ptr, + (void *)&val, 1); + out_buf_ptr += 1 << 1; + addr += 1; break; - } - copy_to_hex(out_buf_ptr, (void *)&val, - len); - out_buf_ptr += len << 1; - addr += len; } } else memcpy(out_buffer, "E03", 4); -- To view, visit https://review.coreboot.org/c/coreboot/+/36022 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f4ab7a0135baac1fd324ced0e501ac2f096e1c4 Gerrit-Change-Number: 36022 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: x86 gdb: Extend GDB stub with a version information
by Werner Zeh (Code Review) 14 Oct '19

14 Oct '19

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36021 ) Change subject: x86 gdb: Extend GDB stub with a version information ...................................................................... x86 gdb: Extend GDB stub with a version information Add GDB command "w" to get the current version of the implemented GDB stub in coreboot. NOT FOR MERGE!!! Change-Id: Ia9951ee4800e8bbf2e40a7b94de1cf3ef4c2dccd Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/arch/x86/exception.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/36021/1 diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c index 646e962..b1689cc 100644 --- a/src/arch/x86/exception.c +++ b/src/arch/x86/exception.c @@ -30,6 +30,8 @@ * At least NUM_REGBYTES*2 are needed for register packets */ #define BUFMAX 400 +/* Add a version string. */ +#define GDB_STUB_EXTENSION_VERSION "1.0" enum regnames { EAX = 0, ECX, EDX, EBX, ESP, EBP, ESI, EDI, PC /* also known as eip */, @@ -837,6 +839,10 @@ } else memcpy(out_buffer, "E07", 4); break; + case 'w': + memcpy(out_buffer, GDB_STUB_EXTENSION_VERSION, + sizeof(GDB_STUB_EXTENSION_VERSION)); + break; case 'z': /* z0AAAA,LLLL remove memory breakpoint */ /* z1AAAA,LLLL remove hardware breakpoint */ /* z2AAAA,LLLL remove write watchpoint */ -- To view, visit https://review.coreboot.org/c/coreboot/+/36021 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia9951ee4800e8bbf2e40a7b94de1cf3ef4c2dccd Gerrit-Change-Number: 36021 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: x86 gdb: Extend GDB stub with I/O read and write commands
by Werner Zeh (Code Review) 14 Oct '19

14 Oct '19

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36016 ) Change subject: x86 gdb: Extend GDB stub with I/O read and write commands ...................................................................... x86 gdb: Extend GDB stub with I/O read and write commands Provide functionality in the GDB stub to read and write I/O ports on x86 CPUs. NOT FOR MERGE!!! Change-Id: I8718c576bba149475444947b6cc3d4932547e6eb Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/arch/x86/exception.c 1 file changed, 86 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/36016/1 diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c index b88f4a7..c2783d5 100644 --- a/src/arch/x86/exception.c +++ b/src/arch/x86/exception.c @@ -21,6 +21,7 @@ #include <cpu/x86/lapic.h> #include <stdint.h> #include <string.h> +#include <arch/io.h> #if CONFIG(GDB_STUB) @@ -335,6 +336,8 @@ /* now, read until a # or end of buffer is found */ while (count < BUFMAX) { ch = stub_getc() & 0x7f; + if (!ch) + continue; if (ch == '#') break; checksum = checksum + ch; @@ -412,7 +415,7 @@ put_packet(out_buffer); while (1) { - unsigned long addr, length; + unsigned long addr, length, val; char *ptr; out_buffer[0] = '\0'; out_buffer[1] = '\0'; @@ -462,6 +465,88 @@ } else memcpy(out_buffer, "E02", 4); break; + case 'n': + /* nAA..AA,LLLL,w Read I/O port given by AA..AA. */ + /* Use access width defined with w (b:byte, w:word, + * l:long) and read LLLL number of entries */ + ptr = &in_buffer[1]; + if (parse_ulong(&ptr, &addr) && + (*(ptr++) == ',') && + parse_ulong(&ptr, &length) && + (*(ptr++) == ',') && + ((*(ptr) == 'b') || (*(ptr) == 'w') || + (*(ptr) == 'l'))) { + char width = *(ptr++), len; + char *out_buf_ptr = out_buffer; + unsigned long i, tmp; + /* Read desired amount of I/O ports */ + for (i = 0; i < length; i++) { + switch (width) { + case 'l': + tmp = inl(addr); + /* Rotate the byte order as */ + /* copy_to_hex() works on a */ + /* byte stream. */ + val = (((tmp >> 24) & 0xff) | + (((tmp >> 16) & 0xff) << 8) | + (((tmp >> 8) & 0xff) << 16) | + ((tmp & 0xff) << 24)); + len = 4; + break; + case 'w': + tmp = inw(addr); + /* Rotate the byte order as */ + /* copy_to_hex() works on a */ + /* byte stream. */ + val = (((tmp >> 8) & 0xff) | + ((tmp & 0xff) << 8)); + len = 2; + break; + case 'b': + default: + val = inb(addr); + len = 1; + break; + + } + copy_to_hex(out_buf_ptr, (void *)&val, + len); + out_buf_ptr += len << 1; + addr += len; + } + } else + memcpy(out_buffer, "E03", 4); + break; + case 'N': + /* nAA..AA,VVVV,w: Write I/O port given by AA..AA. */ + /* Use access width defined with w (b:byte, w:word, + * l:long) and write value given by VVVV. */ + ptr = &in_buffer[1]; + if (parse_ulong(&ptr, &addr) && + (*(ptr++) == ',') && + parse_ulong(&ptr, &val) && + (*(ptr++) == ',') && + ((*(ptr) == 'b') || (*(ptr) == 'w') || + (*(ptr) == 'l')) && + (*(++ptr) == ':')) { + char width = *(ptr - 1); + + switch (width) { + case 'l': + outl(val, addr); + break; + case 'w': + outw(val, addr); + break; + case 'b': + default: + outb(val, addr); + break; + } + memcpy(out_buffer, "OK", 3); + } else + memcpy(out_buffer, "E04", 4); + break; case 's': case 'c': /* cAA..AA Continue at address AA..AA(optional) -- To view, visit https://review.coreboot.org/c/coreboot/+/36016 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8718c576bba149475444947b6cc3d4932547e6eb Gerrit-Change-Number: 36016 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mainboard/lenovo/t410: Add new port
by Patrick Rudolph (Code Review) 14 Oct '19

14 Oct '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/11791 ) Change subject: mainboard/lenovo/t410: Add new port ...................................................................... Patch Set 26: (1 comment) https://review.coreboot.org/c/coreboot/+/11791/25/src/mainboard/lenovo/t410… File src/mainboard/lenovo/t410/vboot-rwa.fmd: https://review.coreboot.org/c/coreboot/+/11791/25/src/mainboard/lenovo/t410… PS25, Line 20: 0x11f000 > remove the size on this one, to be certain that the COREBOOT region is always align to the top of th […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/11791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9d872e643dd242e925bfb46d18076e6ad100995 Gerrit-Change-Number: 11791 Gerrit-PatchSet: 26 Gerrit-Owner: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eloy Degen Gerrit-CC: Matt Parnell <mparnell(a)gmail.com> Gerrit-CC: Okashi Odayakana <okashi(a)okashi.me> Gerrit-CC: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Comment-Date: Mon, 14 Oct 2019 09:06:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard/lenovo/t410: Add new port
by Patrick Rudolph (Code Review) 14 Oct '19

14 Oct '19

Patrick Rudolph has uploaded a new patch set (#26) to the change originally created by Nicolas Reinecke. ( https://review.coreboot.org/c/coreboot/+/11791 ) Change subject: mainboard/lenovo/t410: Add new port ...................................................................... mainboard/lenovo/t410: Add new port The port is based on the x201 / t410s. 2537-vg5 / i5, no discrete gpu Tested and working: * Native raminit * Native gfxinit * Booting Seabios 1.12.1 * Booting from EHCI * Running GNU/Linux 5.0.0 * No errors in dmesg * EHCI debug on the devices left side, bottom-right * Keyboard * Fn keys (Mute, Volume, Mic) * Touchpad * TPM * Wifi * Sound * USB * Ethernet * S3 resume * VBOOT Testing in progress. Untested: * VGA * Displayport * Docking station Bugs: * AC adapter can't be read from ACPI * TPM not working with VBOOT and C_ENV BB Details for flashing externally: 1. Disconnect all power 2. Connect the external flasher 3. Connect the power cord (This fixes internal power control) 4. Remove the power cord Change-Id: Id9d872e643dd242e925bfb46d18076e6ad100995 Signed-off-by: Nicolas Reinecke <nr(a)das-labor.org> Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/lenovo/t410.md A Documentation/mainboard/lenovo/t410_chip_location.jpg A src/mainboard/lenovo/t410/Kconfig A src/mainboard/lenovo/t410/Kconfig.name A src/mainboard/lenovo/t410/Makefile.inc A src/mainboard/lenovo/t410/acpi/dock.asl A src/mainboard/lenovo/t410/acpi/ec.asl A src/mainboard/lenovo/t410/acpi/gpe.asl A src/mainboard/lenovo/t410/acpi/platform.asl A src/mainboard/lenovo/t410/acpi/superio.asl A src/mainboard/lenovo/t410/acpi_tables.c A src/mainboard/lenovo/t410/board_info.txt A src/mainboard/lenovo/t410/cmos.default A src/mainboard/lenovo/t410/cmos.layout A src/mainboard/lenovo/t410/data.vbt A src/mainboard/lenovo/t410/devicetree.cb A src/mainboard/lenovo/t410/dock.c A src/mainboard/lenovo/t410/dock.h A src/mainboard/lenovo/t410/dsdt.asl A src/mainboard/lenovo/t410/early_init.c A src/mainboard/lenovo/t410/gma-mainboard.ads A src/mainboard/lenovo/t410/gpio.c A src/mainboard/lenovo/t410/hda_verb.c A src/mainboard/lenovo/t410/mainboard.c A src/mainboard/lenovo/t410/romstage.c A src/mainboard/lenovo/t410/smihandler.c A src/mainboard/lenovo/t410/thermal.h A src/mainboard/lenovo/t410/vboot-rwa.fmd M src/southbridge/intel/common/Makefile.inc 30 files changed, 1,484 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/11791/26 -- To view, visit https://review.coreboot.org/c/coreboot/+/11791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9d872e643dd242e925bfb46d18076e6ad100995 Gerrit-Change-Number: 11791 Gerrit-PatchSet: 26 Gerrit-Owner: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eloy Degen Gerrit-CC: Matt Parnell <mparnell(a)gmail.com> Gerrit-CC: Okashi Odayakana <okashi(a)okashi.me> Gerrit-CC: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit October 2019