coreboot-gerrit October 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/hatch/variants/helios: Modify touchscreen power on sequence
by Kane Chen (Code Review) 15 Oct '19

15 Oct '19

Hello Philip Chen, Shelley Chen, build bot (Jenkins), Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35907 to look at the new patch set (#3). Change subject: mb/google/hatch/variants/helios: Modify touchscreen power on sequence ...................................................................... mb/google/hatch/variants/helios: Modify touchscreen power on sequence Modify GPP_D15 delay time. Modify GPP_D9 delay time. Add GPP_C4 setting. BUG=b:142368161 BRANCH=Master TEST=emerge-hatch coreboot chromeos-bootimage Signed-off-by: YenLu Chen <kane_chen(a)pegatron.corp-partner.google.com> Change-Id: I86c920ff1d5c0b510adde8a37f60003072d5f4e7 --- M src/mainboard/google/hatch/variants/helios/overridetree.cb 1 file changed, 7 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/35907/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/35907 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86c920ff1d5c0b510adde8a37f60003072d5f4e7 Gerrit-Change-Number: 35907 Gerrit-PatchSet: 3 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Assignee: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Documentation/gfx: Update support list of libgfxinit
by Nico Huber (Code Review) 14 Oct '19

14 Oct '19

Hello Patrick Rudolph, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/35989 to review the following change. Change subject: Documentation/gfx: Update support list of libgfxinit ...................................................................... Documentation/gfx: Update support list of libgfxinit Also get rid of some manual hyphenation. Change-Id: Ibeb4eceeae48cf375171d0261ed9475010b0d5b1 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M Documentation/gfx/libgfxinit.md 1 file changed, 7 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/35989/1 diff --git a/Documentation/gfx/libgfxinit.md b/Documentation/gfx/libgfxinit.md index c000f27..0608363 100644 --- a/Documentation/gfx/libgfxinit.md +++ b/Documentation/gfx/libgfxinit.md @@ -7,13 +7,14 @@ *libgfxinit* is a library of full-featured graphics initialization (aka. modesetting) drivers. It's implemented in SPARK (a subset of Ada with formal verification features). While not restricted to in -any way, it currently only supports Intel's integrated gfx control- -lers (GMA). +any way, it currently only supports Intel's integrated graphics +controllers (GMA). -Currently, it supports the Intel Core i3/i5/i7 processor line and -will support HDMI and DP on the Atom successor Apollo Lake. At the -time of writing, Sandy Bridge, Ivy Bridge, and Haswell are veri- -fied to work within *coreboot*. +Currently, it supports the Intel Core i3/i5/i7 processor line, HDMI +and DP on the Apollo Lake processors and everything but SDVO on G45 +and GM45 chipsets. At the time of writing, G45, GM45, everything +from Arrandale to Coffee Lake, and Apollo Lake are verified to work +within *coreboot*. GMA: Framebuffer Configuration ------------------------------ -- To view, visit https://review.coreboot.org/c/coreboot/+/35989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibeb4eceeae48cf375171d0261ed9475010b0d5b1 Gerrit-Change-Number: 35989 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/lenovo/x201: Add VBOOT support
by Arthur Heymans (Code Review) 14 Oct '19

14 Oct '19

Hello Alexander Couzens, Aaron Durbin, Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35959 to look at the new patch set (#5). Change subject: mb/lenovo/x201: Add VBOOT support ...................................................................... mb/lenovo/x201: Add VBOOT support Tested with CONFIG_H8_FN_KEY_AS_VBOOT_RECOVERY_SW to switch between RW_A and recovery, which works quite well as a developer mode to test RW_A with the COREBOOT slot as a fallback. Change-Id: I9d524988e991457032f63a947606d1b3581de5e7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/x201/Kconfig M src/mainboard/lenovo/x201/cmos.layout A src/mainboard/lenovo/x201/vboot-rwa.fmd 3 files changed, 52 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/35959/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/35959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d524988e991457032f63a947606d1b3581de5e7 Gerrit-Change-Number: 35959 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/hatch/variants/helios: Modify touchscreen power on sequence
by Shelley Chen (Code Review) 14 Oct '19

14 Oct '19

Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35907 ) Change subject: mb/google/hatch/variants/helios: Modify touchscreen power on sequence ...................................................................... Patch Set 2: > Patch Set 2: > > > Patch Set 2: > > > > (1 comment) > > We add some time buffer to avoid margin case . Were you seeing failures with the previous values? -- To view, visit https://review.coreboot.org/c/coreboot/+/35907 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86c920ff1d5c0b510adde8a37f60003072d5f4e7 Gerrit-Change-Number: 35907 Gerrit-PatchSet: 2 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Assignee: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Mon, 14 Oct 2019 16:53:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: superio: add support for IT8380
by Alexander Couzens (Code Review) 14 Oct '19

14 Oct '19

Hello Felix Held, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35626 to look at the new patch set (#3). Change subject: superio: add support for IT8380 ...................................................................... superio: add support for IT8380 The IT8380 is a SuperIO with a programmable MCU. Change-Id: Ife2bafa073d714d58756510018632e97d86aa280 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- M Documentation/superio/index.md A Documentation/superio/ite/it8380.md M src/superio/ite/Makefile.inc A src/superio/ite/it8380/Kconfig A src/superio/ite/it8380/Makefile.inc A src/superio/ite/it8380/it8380.h A src/superio/ite/it8380/superio.c 7 files changed, 190 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/35626/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/35626 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife2bafa073d714d58756510018632e97d86aa280 Gerrit-Change-Number: 35626 Gerrit-PatchSet: 3 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [NOTFORMERGE_YET]mb/lenovo/x201: Add VBOOT support
by Arthur Heymans (Code Review) 14 Oct '19

14 Oct '19

Hello Alexander Couzens, Aaron Durbin, Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35959 to look at the new patch set (#3). Change subject: [NOTFORMERGE_YET]mb/lenovo/x201: Add VBOOT support ...................................................................... [NOTFORMERGE_YET]mb/lenovo/x201: Add VBOOT support Tested with CONFIG_H8_FN_KEY_AS_VBOOT_RECOVERY_SW to switch between RW_A and recovery, which works quite well as a developer mode to test RW_A with the COREBOOT slot as a fallback. TODO: linking spi.c in verstage needs to be done in a different CL. Change-Id: I9d524988e991457032f63a947606d1b3581de5e7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/x201/Kconfig A src/mainboard/lenovo/x201/vboot-rwa.fmd M src/southbridge/intel/common/Makefile.inc 3 files changed, 50 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/35959/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/35959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d524988e991457032f63a947606d1b3581de5e7 Gerrit-Change-Number: 35959 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [NOTFORMERGE]mb/lenovo/x201: Add VBOOT support
by Arthur Heymans (Code Review) 14 Oct '19

14 Oct '19

Hello Alexander Couzens, Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35959 to look at the new patch set (#2). Change subject: [NOTFORMERGE]mb/lenovo/x201: Add VBOOT support ...................................................................... [NOTFORMERGE]mb/lenovo/x201: Add VBOOT support Tested with CONFIG_H8_FN_KEY_AS_VBOOT_RECOVERY_SW to switch between RW_A and recovery, which works quite well as a developer mode to test RW_A with the COREBOOT slot as a fallback. TODO the nehalem raminit does a CPU reset at some point, while the system is not reset and therefore TPM gets initialized twice and fails the second time. TODO: TPM init returns with errors which breaks VBOOT. Change-Id: I9d524988e991457032f63a947606d1b3581de5e7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/x201/Kconfig A src/mainboard/lenovo/x201/vboot-rwa.fmd M src/security/vboot/tpm_common.c M src/southbridge/intel/common/Makefile.inc 4 files changed, 59 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/35959/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/35959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d524988e991457032f63a947606d1b3581de5e7 Gerrit-Change-Number: 35959 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mainboard/lenovo/t410: Add new port
by Arthur Heymans (Code Review) 14 Oct '19

14 Oct '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/11791 ) Change subject: mainboard/lenovo/t410: Add new port ...................................................................... Patch Set 26: (1 comment) https://review.coreboot.org/c/coreboot/+/11791/26/src/southbridge/intel/com… File src/southbridge/intel/common/Makefile.inc: https://review.coreboot.org/c/coreboot/+/11791/26/src/southbridge/intel/com… PS26, Line 49: verstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c See https://review.coreboot.org/c/coreboot/+/33199/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/11791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9d872e643dd242e925bfb46d18076e6ad100995 Gerrit-Change-Number: 11791 Gerrit-PatchSet: 26 Gerrit-Owner: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eloy Degen Gerrit-CC: Matt Parnell <mparnell(a)gmail.com> Gerrit-CC: Okashi Odayakana <okashi(a)okashi.me> Gerrit-CC: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Comment-Date: Mon, 14 Oct 2019 14:17:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: x86 gdb: Extend GDB stub memory access with 64 bit access
by Werner Zeh (Code Review) 14 Oct '19

14 Oct '19

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36020 ) Change subject: x86 gdb: Extend GDB stub memory access with 64 bit access ...................................................................... x86 gdb: Extend GDB stub memory access with 64 bit access Add "q" for the width field n memory read and write which enables 64 bit access to memory. NOT FOR MERGE!!! Change-Id: I899dec25d3d6bf0658c491e5e71b64d5b9dd09fd Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/arch/x86/exception.c 1 file changed, 97 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/36020/1 diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c index 71d96fc..646e962 100644 --- a/src/arch/x86/exception.c +++ b/src/arch/x86/exception.c @@ -282,6 +282,31 @@ return start != *ptr; } +static void gdb_read64(void *addr, unsigned long *hi, unsigned long *lo) +{ + __asm__ volatile( + "movq (%%eax), %%xmm0;" + "movd %%xmm0, %%ebx;" + "pextrd $1, %%xmm0, %%ecx" + : "=b" (*lo), + "=c" (*hi) + : "a" (addr) + ); +} + +static void gdb_write64(void *addr, unsigned long hi, unsigned long lo) +{ + __asm__ volatile( + "movd %%ebx, %%xmm0;" + "pinsrd $1, %%ecx, %%xmm0;" + "movq %%xmm0, (%%eax);" + : + : "a" (addr), + "b" (lo), + "c" (hi) + ); +} + /* convert the memory pointed to by mem into hex, placing result in buf */ /* return a pointer to the last char put in buf (null) */ static void copy_to_hex(char *buf, void *addr, unsigned long count) @@ -337,6 +362,38 @@ *buf = 0; } +/* convert the memory pointed to by mem into hex, placing result in buf */ +/* return a pointer to the last char put in buf (null) */ +/* Use 32 bit wide memory access. */ +static void copy_to_hex_64(char *buf, void *addr, unsigned long count) +{ + unsigned long hi, lo; + long long *mem = addr; + + while (count--) { + hi = 0; + lo = 0; + gdb_read64(mem++, &hi, &lo); + *buf++ = hexchars[(hi >> 28) & 0x0f]; + *buf++ = hexchars[(hi >> 24) & 0x0f]; + *buf++ = hexchars[(hi >> 20) & 0x0f]; + *buf++ = hexchars[(hi >> 16) & 0x0f]; + *buf++ = hexchars[(hi >> 12) & 0x0f]; + *buf++ = hexchars[(hi >> 8) & 0x0f]; + *buf++ = hexchars[(hi >> 4) & 0x0f]; + *buf++ = hexchars[(hi >> 0) & 0x0f]; + *buf++ = hexchars[(lo >> 28) & 0x0f]; + *buf++ = hexchars[(lo >> 24) & 0x0f]; + *buf++ = hexchars[(lo >> 20) & 0x0f]; + *buf++ = hexchars[(lo >> 16) & 0x0f]; + *buf++ = hexchars[(lo >> 12) & 0x0f]; + *buf++ = hexchars[(lo >> 8) & 0x0f]; + *buf++ = hexchars[(lo >> 4) & 0x0f]; + *buf++ = hexchars[(lo >> 0) & 0x0f]; + } + *buf = 0; +} + /* convert the hex array pointed to by buf into binary to be placed in mem */ /* return a pointer to the character AFTER the last byte written */ @@ -392,6 +449,38 @@ } } +/* convert the hex array pointed to by buf into binary to be placed in mem */ +/* return a pointer to the character AFTER the last byte written */ +/* Use 64 bit wide memory access */ +static void copy_from_hex_64(void *addr, char *buf, unsigned long count) +{ + unsigned long hi, lo; + long long *mem = addr; + + while (count--) { + hi = 0; + lo = 0; + hi |= hex(*buf++) << 28; + hi |= hex(*buf++) << 24; + hi |= hex(*buf++) << 20; + hi |= hex(*buf++) << 16; + hi |= hex(*buf++) << 12; + hi |= hex(*buf++) << 8; + hi |= hex(*buf++) << 4; + hi |= hex(*buf++) << 0; + + lo |= hex(*buf++) << 28; + lo |= hex(*buf++) << 24; + lo |= hex(*buf++) << 20; + lo |= hex(*buf++) << 16; + lo |= hex(*buf++) << 12; + lo |= hex(*buf++) << 8; + lo |= hex(*buf++) << 4; + lo |= hex(*buf++); + gdb_write64(mem++, hi, lo); + } +} + /* scan for the sequence $<data>#<checksum> */ @@ -575,6 +664,10 @@ copy_to_hex_word(out_buffer, (void *)addr, length); + } else if (width == 'q') { + copy_to_hex_64(out_buffer, + (void *)addr, + length); } else { memcpy(out_buffer, "E01", 4); } @@ -608,6 +701,10 @@ copy_from_hex_word((void *)addr, ptr, length); + } else if (width == 'q') { + copy_from_hex_64((void *)addr, + ptr, + length); } else { memcpy(out_buffer, "E02", 4); } -- To view, visit https://review.coreboot.org/c/coreboot/+/36020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I899dec25d3d6bf0658c491e5e71b64d5b9dd09fd Gerrit-Change-Number: 36020 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: x86 gdb: Extend GDB stub memory access with word and dword access
by Werner Zeh (Code Review) 14 Oct '19

14 Oct '19

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36019 ) Change subject: x86 gdb: Extend GDB stub memory access with word and dword access ...................................................................... x86 gdb: Extend GDB stub memory access with word and dword access Add extension to the memory read and write commands so that one can define the access width to the memory. Up to now only byte access was possible. Now the user can specify whether he wants to access the memory ion 8- 16- or 32-bit. The extension keeps the original command format so that an unmodified GDB client can still use this commands as usual. NOT FOR MERGE!!! Change-Id: If0800577857471eef96550a2c7122032bd1b7f37 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/arch/x86/exception.c 1 file changed, 122 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/36019/1 diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c index 4759015..71d96fc 100644 --- a/src/arch/x86/exception.c +++ b/src/arch/x86/exception.c @@ -297,6 +297,46 @@ *buf = 0; } +/* convert the memory pointed to by mem into hex, placing result in buf */ +/* return a pointer to the last char put in buf (null) */ +/* Use 16 bit wide memory access. */ +static void copy_to_hex_word(char *buf, void *addr, unsigned long count) +{ + unsigned short ch; + short *mem = addr; + + while (count--) { + ch = *mem++; + *buf++ = hexchars[(ch >> 12) & 0x0f]; + *buf++ = hexchars[(ch >> 8) & 0x0f]; + *buf++ = hexchars[(ch >> 4) & 0x0f]; + *buf++ = hexchars[ch & 0x0f]; + } + *buf = 0; +} + +/* convert the memory pointed to by mem into hex, placing result in buf */ +/* return a pointer to the last char put in buf (null) */ +/* Use 32 bit wide memory access. */ +static void copy_to_hex_long(char *buf, void *addr, unsigned long count) +{ + unsigned long ch; + long *mem = addr; + + while (count--) { + ch = *mem++; + *buf++ = hexchars[(ch >> 28) & 0x0f]; + *buf++ = hexchars[(ch >> 24) & 0x0f]; + *buf++ = hexchars[(ch >> 20) & 0x0f]; + *buf++ = hexchars[(ch >> 16) & 0x0f]; + *buf++ = hexchars[(ch >> 12) & 0x0f]; + *buf++ = hexchars[(ch >> 8) & 0x0f]; + *buf++ = hexchars[(ch >> 4) & 0x0f]; + *buf++ = hexchars[ch & 0x0f]; + } + *buf = 0; +} + /* convert the hex array pointed to by buf into binary to be placed in mem */ /* return a pointer to the character AFTER the last byte written */ @@ -312,6 +352,46 @@ } } +/* convert the hex array pointed to by buf into binary to be placed in mem */ +/* return a pointer to the character AFTER the last byte written */ +/* Use 16 bit wide memory access */ +static void copy_from_hex_word(void *addr, char *buf, unsigned long count) +{ + unsigned short ch; + short *mem = addr; + + while (count--) { + ch = 0; + ch |= hex(*buf++) << 12; + ch |= hex(*buf++) << 8; + ch |= hex(*buf++) << 4; + ch |= hex(*buf++); + *mem++ = ch; + } +} + +/* convert the hex array pointed to by buf into binary to be placed in mem */ +/* return a pointer to the character AFTER the last byte written */ +/* Use 32 bit wide memory access */ +static void copy_from_hex_long(void *addr, char *buf, unsigned long count) +{ + unsigned long ch; + long *mem = addr; + + while (count--) { + ch = 0; + ch |= hex(*buf++) << 28; + ch |= hex(*buf++) << 24; + ch |= hex(*buf++) << 20; + ch |= hex(*buf++) << 16; + ch |= hex(*buf++) << 12; + ch |= hex(*buf++) << 8; + ch |= hex(*buf++) << 4; + ch |= hex(*buf++); + *mem++ = ch; + } +} + /* scan for the sequence $<data>#<checksum> */ @@ -475,25 +555,63 @@ memcpy(out_buffer, "OK", 3); break; case 'm': - /* mAA..AA,LLLL Read LLLL bytes at address AA..AA */ + /* mAA..AA,LLLL,w Read LLLL bytes at address AA..AA */ + /* ,w is optional and can define the access width to */ + /* the memory (b: 8bit, w:16 bit, l: 32 bit */ ptr = &in_buffer[1]; if (parse_ulong(&ptr, &addr) && (*ptr++ == ',') && parse_ulong(&ptr, &length)) { - copy_to_hex(out_buffer, (void *)addr, length); + if (*ptr != ',') { + copy_to_hex(out_buffer, (void *)addr, + length); + } else { + char width = *(++ptr); + if (width == 'l') { + copy_to_hex_long(out_buffer, + (void *)addr, + length); + } else if (width == 'w') { + copy_to_hex_word(out_buffer, + (void *)addr, + length); + } else { + memcpy(out_buffer, "E01", 4); + } + } } else memcpy(out_buffer, "E01", 4); break; case 'M': - /* MAA..AA,LLLL: Write LLLL bytes at address AA.AA + /* MAA..AA,LLLL:,w Write LLLL bytes at address AA.AA * return OK + * ,w is optional and can define the access width to + * the memory (b: 8bit, w:16 bit, l: 32 bit */ ptr = &in_buffer[1]; if (parse_ulong(&ptr, &addr) && (*(ptr++) == ',') && parse_ulong(&ptr, &length) && (*(ptr++) == ':')) { - copy_from_hex((void *)addr, ptr, length); + if (*ptr != ',') { + copy_from_hex((void *)addr, ptr, + length); + } else { + char width; + ptr++; /* move away from ',' */ + width = *ptr++; + if (width == 'l') { + copy_from_hex_long((void *)addr, + ptr, + length); + } else if (width == 'w') { + copy_from_hex_word((void *)addr, + ptr, + length); + } else { + memcpy(out_buffer, "E02", 4); + } + } memcpy(out_buffer, "OK", 3); } else memcpy(out_buffer, "E02", 4); -- To view, visit https://review.coreboot.org/c/coreboot/+/36019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0800577857471eef96550a2c7122032bd1b7f37 Gerrit-Change-Number: 36019 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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coreboot-gerrit October 2019