coreboot-gerrit October 2019

coreboot-gerrit@coreboot.org

1 participants
1921 discussions

Change in ...coreboot[master]: drivers/pc80/rtc: Move fetching and cleaning up the layout
by Arthur Heymans (Code Review) 13 Oct '19

13 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33057 Change subject: drivers/pc80/rtc: Move fetching and cleaning up the layout ...................................................................... drivers/pc80/rtc: Move fetching and cleaning up the layout Both get_option and set_option need to fetch the layout and clean up afterwards. Do this in a common location. Change-Id: I0623738838c62f49e9a8d93a34f01a509ef1f9cb Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/pc80/rtc/mc146818rtc.c 1 file changed, 39 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/33057/1 diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c index 6e37cd2..3667354 100644 --- a/src/drivers/pc80/rtc/mc146818rtc.c +++ b/src/drivers/pc80/rtc/mc146818rtc.c @@ -268,22 +268,12 @@ return CB_SUCCESS; } -enum cb_err get_option(void *dest, const char *name) +struct region_device rdev; + +static enum cb_err get_layout(struct cmos_option_table *ct) { - struct cmos_option_table *ct; - struct region_device rdev; - struct cmos_entries *ce; - size_t namelen; - int found = 0; - - if (!CONFIG(USE_OPTION_TABLE)) - return CB_CMOS_OTABLE_DISABLED; - LOCK_NVRAM_CBFS_SPINLOCK(); - /* Figure out how long name is */ - namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); - if (locate_cmos_layout(&rdev) != CB_SUCCESS) { UNLOCK_NVRAM_CBFS_SPINLOCK(); return CB_CMOS_LAYOUT_NOT_FOUND; @@ -296,6 +286,32 @@ UNLOCK_NVRAM_CBFS_SPINLOCK(); return CB_CMOS_LAYOUT_NOT_FOUND; } + return CB_SUCCESS; +} + +static void clean_up_layout(struct cmos_option_table *ct) +{ + rdev_munmap(&rdev, ct); + UNLOCK_NVRAM_CBFS_SPINLOCK(); +} + +enum cb_err get_option(void *dest, const char *name) +{ + struct cmos_option_table *ct = NULL;; + struct cmos_entries *ce; + size_t namelen; + int found = 0; + + if (!CONFIG(USE_OPTION_TABLE)) + return CB_CMOS_OTABLE_DISABLED; + + LOCK_NVRAM_CBFS_SPINLOCK(); + + /* Figure out how long name is */ + namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); + + if (get_layout(ct) != CB_SUCCESS) + return CB_CMOS_LAYOUT_NOT_FOUND; /* find the requested entry record */ ce = (struct cmos_entries *)((unsigned char *)ct + ct->header_length); @@ -308,23 +324,19 @@ } if (!found) { printk(BIOS_DEBUG, "No CMOS option '%s'.\n", name); - rdev_munmap(&rdev, ct); - UNLOCK_NVRAM_CBFS_SPINLOCK(); + clean_up_layout(ct); return CB_CMOS_OPTION_NOT_FOUND; } if (!cmos_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC)) { - rdev_munmap(&rdev, ct); - UNLOCK_NVRAM_CBFS_SPINLOCK(); + clean_up_layout(ct); return CB_CMOS_CHECKSUM_INVALID; } if (get_cmos_value(ce->bit, ce->length, dest) != CB_SUCCESS) { - rdev_munmap(&rdev, ct); - UNLOCK_NVRAM_CBFS_SPINLOCK(); + clean_up_layout(ct); return CB_CMOS_ACCESS_ERROR; } - rdev_munmap(&rdev, ct); - UNLOCK_NVRAM_CBFS_SPINLOCK(); + clean_up_layout(ct); return CB_SUCCESS; } @@ -383,8 +395,7 @@ enum cb_err set_option(const char *name, void *value) { - struct cmos_option_table *ct; - struct region_device rdev; + struct cmos_option_table *ct = NULL; struct cmos_entries *ce; unsigned long length; size_t namelen; @@ -396,18 +407,8 @@ /* Figure out how long name is */ namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); - if (locate_cmos_layout(&rdev) != CB_SUCCESS) { - UNLOCK_NVRAM_CBFS_SPINLOCK(); + if (get_layout(ct) != CB_SUCCESS) return CB_CMOS_LAYOUT_NOT_FOUND; - } - ct = rdev_mmap_full(&rdev); - if (!ct) { - printk(BIOS_ERR, "RTC: cmos_layout.bin could not be mapped. " - "Options are disabled\n"); - - UNLOCK_NVRAM_CBFS_SPINLOCK(); - return CB_CMOS_LAYOUT_NOT_FOUND; - } /* find the requested entry record */ ce = (struct cmos_entries *)((unsigned char *)ct + ct->header_length); @@ -420,7 +421,7 @@ } if (!found) { printk(BIOS_DEBUG, "WARNING: No CMOS option '%s'.\n", name); - rdev_munmap(&rdev, ct); + clean_up_layout(ct); return CB_CMOS_OPTION_NOT_FOUND; } @@ -430,17 +431,17 @@ /* make sure the string is null terminated */ if (set_cmos_value(ce->bit + ce->length - 8, 8, &(u8[]){0}) != CB_SUCCESS) { - rdev_munmap(&rdev, ct); + clean_up_layout(ct); return CB_CMOS_ACCESS_ERROR; } } if (set_cmos_value(ce->bit, length, value) != CB_SUCCESS) { - rdev_munmap(&rdev, ct); + clean_up_layout(ct); return CB_CMOS_ACCESS_ERROR; } - rdev_munmap(&rdev, ct); + clean_up_layout(ct); return CB_SUCCESS; } -- To view, visit https://review.coreboot.org/c/coreboot/+/33057 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0623738838c62f49e9a8d93a34f01a509ef1f9cb Gerrit-Change-Number: 33057 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

2 3

Change in ...coreboot[master]: soc/intel/baytrail: Use cpu/intel/car/romstage.c entry point
by Arthur Heymans (Code Review) 13 Oct '19

13 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32969 Change subject: soc/intel/baytrail: Use cpu/intel/car/romstage.c entry point ...................................................................... soc/intel/baytrail: Use cpu/intel/car/romstage.c entry point This moves some boilerplate like setting up timestamps and entering postcar to a common location. Change-Id: I256b4149163245697fe1c2d4406bd6229a45b556 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/baytrail/romstage/Makefile.inc M src/soc/intel/baytrail/romstage/romstage.c 2 files changed, 4 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/32969/1 diff --git a/src/soc/intel/baytrail/romstage/Makefile.inc b/src/soc/intel/baytrail/romstage/Makefile.inc index f1a3463..8f009bd 100644 --- a/src/soc/intel/baytrail/romstage/Makefile.inc +++ b/src/soc/intel/baytrail/romstage/Makefile.inc @@ -1,5 +1,6 @@ cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S cpu_incs-y += $(obj)/fmap_config.h +romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += romstage.c romstage-y += raminit.c romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += uart.c diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index cc3bcd9..2a530b4 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -21,6 +21,7 @@ #include <bootblock_common.h> #include <console/console.h> #include <cbmem.h> +#include <cpu/intel/romstage.h> #include <cpu/x86/mtrr.h> #if CONFIG(EC_GOOGLE_CHROMEEC) #include <ec/google/chromeec/ec.h> @@ -49,8 +50,6 @@ * Because we can't use global variables the stack is used for allocations -- * thus the need to call back and forth. */ -static void platform_enter_postcar(void); - static void program_base_addresses(void) { uint32_t reg; @@ -166,18 +165,12 @@ } /* Entry from cache-as-ram.inc. */ -static void romstage_main(uint64_t tsc, uint32_t bist) +void mainboard_romstage_entry(unsigned long bist) { struct mrc_params mrc_params; struct chipset_power_state *ps; int prev_sleep_state; - /* Save initial timestamp from bootblock. */ - timestamp_init(tsc); - - /* Save romstage begin */ - timestamp_add_now(TS_START_ROMSTAGE); - program_base_addresses(); tco_disable(); @@ -215,25 +208,13 @@ timestamp_add_now(TS_AFTER_INITRAM); romstage_handoff_init(prev_sleep_state == ACPI_S3); - - platform_enter_postcar(); - - /* We don't return here */ -} - -/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK, - * keeping changes in cache_as_ram.S easy to manage. - */ -asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) -{ - romstage_main(base_timestamp, bist); } #define ROMSTAGE_RAM_STACK_SIZE 0x5000 /* setup_stack_and_mtrrs() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use. */ -static void platform_enter_postcar(void) +void platform_enter_postcar(void) { struct postcar_frame pcf; uintptr_t top_of_ram; -- To view, visit https://review.coreboot.org/c/coreboot/+/32969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I256b4149163245697fe1c2d4406bd6229a45b556 Gerrit-Change-Number: 32969 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: soc/intel/baytrail: Place the raminit in a common location
by Arthur Heymans (Code Review) 13 Oct '19

13 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32968 Change subject: soc/intel/baytrail: Place the raminit in a common location ...................................................................... soc/intel/baytrail: Place the raminit in a common location Change-Id: I784382d5c5251fac7039f991f8a6ad123a0b4f83 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/google/rambi/romstage.c M src/soc/intel/baytrail/include/soc/romstage.h M src/soc/intel/baytrail/romstage/romstage.c 3 files changed, 43 insertions(+), 52 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/32968/1 diff --git a/src/mainboard/google/rambi/romstage.c b/src/mainboard/google/rambi/romstage.c index c244c83..93b6ba4 100644 --- a/src/mainboard/google/rambi/romstage.c +++ b/src/mainboard/google/rambi/romstage.c @@ -58,7 +58,7 @@ return spd_ptr; } -void mainboard_romstage_entry(struct mrc_params *mrc_params) +void mainboard_pre_raminit(struct mrc_params *mrc_params) { void *spd_content; int dual_channel = 0; @@ -80,6 +80,4 @@ mrc_params->mainboard.dram_data[0] = spd_content; if (dual_channel) mrc_params->mainboard.dram_data[1] = spd_content; - - romstage_common(mrc_params); } diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h index ea6298b..7730893 100644 --- a/src/soc/intel/baytrail/include/soc/romstage.h +++ b/src/soc/intel/baytrail/include/soc/romstage.h @@ -24,8 +24,7 @@ #include <arch/cpu.h> #include <soc/mrc_wrapper.h> -void mainboard_romstage_entry(struct mrc_params *mrc_params); -void romstage_common(struct mrc_params *mrc_params); +void mainboard_pre_raminit(struct mrc_params *mrc_params); void raminit(struct mrc_params *mp, int prev_sleep_state); void gfx_init(void); void tco_disable(void); diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 73991df..cc3bcd9 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -96,49 +96,6 @@ write32(bcr, reg); } -/* Entry from cache-as-ram.inc. */ -static void romstage_main(uint64_t tsc, uint32_t bist) -{ - struct mrc_params mrc_params; - - /* Save initial timestamp from bootblock. */ - timestamp_init(tsc); - - /* Save romstage begin */ - timestamp_add_now(TS_START_ROMSTAGE); - - program_base_addresses(); - - tco_disable(); - - byt_config_com1_and_enable(); - - console_init(); - - spi_init(); - - set_max_freq(); - - punit_init(); - - gfx_init(); - - /* Call into mainboard. */ - mainboard_romstage_entry(&mrc_params); - - platform_enter_postcar(); - - /* We don't return here */ -} - -/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK, - * keeping changes in cache_as_ram.S easy to manage. - */ -asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) -{ - romstage_main(base_timestamp, bist); -} - static struct chipset_power_state power_state; static void migrate_power_state(int is_recovery) @@ -208,12 +165,38 @@ return prev_sleep_state; } -/* Entry from the mainboard. */ -void romstage_common(struct mrc_params *mrc_params) +/* Entry from cache-as-ram.inc. */ +static void romstage_main(uint64_t tsc, uint32_t bist) { + struct mrc_params mrc_params; struct chipset_power_state *ps; int prev_sleep_state; + /* Save initial timestamp from bootblock. */ + timestamp_init(tsc); + + /* Save romstage begin */ + timestamp_add_now(TS_START_ROMSTAGE); + + program_base_addresses(); + + tco_disable(); + + byt_config_com1_and_enable(); + + console_init(); + + spi_init(); + + set_max_freq(); + + punit_init(); + + gfx_init(); + + /* Call into mainboard. */ + mainboard_pre_raminit(&mrc_params); + timestamp_add_now(TS_BEFORE_INITRAM); ps = fill_power_state(); @@ -226,13 +209,24 @@ boot_count_increment(); #endif - /* Initialize RAM */ - raminit(mrc_params, prev_sleep_state); + raminit(&mrc_params, prev_sleep_state); timestamp_add_now(TS_AFTER_INITRAM); romstage_handoff_init(prev_sleep_state == ACPI_S3); + + platform_enter_postcar(); + + /* We don't return here */ +} + +/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK, + * keeping changes in cache_as_ram.S easy to manage. + */ +asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) +{ + romstage_main(base_timestamp, bist); } #define ROMSTAGE_RAM_STACK_SIZE 0x5000 -- To view, visit https://review.coreboot.org/c/coreboot/+/32968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I784382d5c5251fac7039f991f8a6ad123a0b4f83 Gerrit-Change-Number: 32968 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: soc/intel/baytrail: Extend the scope of the mrc_params
by Arthur Heymans (Code Review) 13 Oct '19

13 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32967 Change subject: soc/intel/baytrail: Extend the scope of the mrc_params ...................................................................... soc/intel/baytrail: Extend the scope of the mrc_params This makes it easier to call the common_romstage code in a common place. Change-Id: I58c5c376c51b48a7cb9b3bc79dd77e417c98d8ae Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/google/rambi/romstage.c M src/soc/intel/baytrail/include/soc/romstage.h 2 files changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/32967/1 diff --git a/src/mainboard/google/rambi/romstage.c b/src/mainboard/google/rambi/romstage.c index eba8beb..c244c83 100644 --- a/src/mainboard/google/rambi/romstage.c +++ b/src/mainboard/google/rambi/romstage.c @@ -21,6 +21,8 @@ #include <soc/romstage.h> #include <variant/variant.h> +static void *spd_ptr; + static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual) { int ram_id = 0; @@ -52,7 +54,8 @@ if (dual_channel_config & (1 << ram_id)) *dual = 1; - return &spd_file_content[SPD_SIZE * ram_id]; + spd_ptr = &spd_file_content[SPD_SIZE * ram_id]; + return spd_ptr; } void mainboard_romstage_entry(struct mrc_params *mrc_params) @@ -73,6 +76,7 @@ spd_content = get_spd_pointer(spd_file, spd_fsize / SPD_SIZE, &dual_channel); + mrc_params->mainboard.dram_data[0] = spd_content; if (dual_channel) mrc_params->mainboard.dram_data[1] = spd_content; diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h index 4fceefb..ea6298b 100644 --- a/src/soc/intel/baytrail/include/soc/romstage.h +++ b/src/soc/intel/baytrail/include/soc/romstage.h @@ -26,7 +26,6 @@ void mainboard_romstage_entry(struct mrc_params *mrc_params); void romstage_common(struct mrc_params *mrc_params); - void raminit(struct mrc_params *mp, int prev_sleep_state); void gfx_init(void); void tco_disable(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/32967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58c5c376c51b48a7cb9b3bc79dd77e417c98d8ae Gerrit-Change-Number: 32967 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: soc/intel/baytrail: Get rid of struct romstage_params
by Arthur Heymans (Code Review) 13 Oct '19

13 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32966 Change subject: soc/intel/baytrail: Get rid of struct romstage_params ...................................................................... soc/intel/baytrail: Get rid of struct romstage_params struct romstage_params holds the BIST and a struct mrc_params pointer. The BIST information is unused. It is easier to just use a mrc_params struct variable. Change-Id: I54b7c6af2f47e85f66e67c81b7a0510488ca8da2 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/google/rambi/romstage.c M src/soc/intel/baytrail/include/soc/romstage.h M src/soc/intel/baytrail/romstage/romstage.c 3 files changed, 13 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/32966/1 diff --git a/src/mainboard/google/rambi/romstage.c b/src/mainboard/google/rambi/romstage.c index 5322267..eba8beb 100644 --- a/src/mainboard/google/rambi/romstage.c +++ b/src/mainboard/google/rambi/romstage.c @@ -55,20 +55,16 @@ return &spd_file_content[SPD_SIZE * ram_id]; } -void mainboard_romstage_entry(struct romstage_params *rp) +void mainboard_romstage_entry(struct mrc_params *mrc_params) { void *spd_content; int dual_channel = 0; void *spd_file; size_t spd_fsize; - struct mrc_params mp = { - .mainboard = { - .dram_type = DRAM_DDR3L, - .dram_info_location = DRAM_INFO_SPD_MEM, - .weaker_odt_settings = 1, - }, - }; + mrc_params->mainboard.dram_type = DRAM_DDR3L; + mrc_params->mainboard.dram_info_location = DRAM_INFO_SPD_MEM; + mrc_params->mainboard.weaker_odt_settings = 1; spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, &spd_fsize); @@ -77,10 +73,9 @@ spd_content = get_spd_pointer(spd_file, spd_fsize / SPD_SIZE, &dual_channel); - mp.mainboard.dram_data[0] = spd_content; + mrc_params->mainboard.dram_data[0] = spd_content; if (dual_channel) - mp.mainboard.dram_data[1] = spd_content; + mrc_params->mainboard.dram_data[1] = spd_content; - rp->mrc_params = &mp; - romstage_common(rp); + romstage_common(mrc_params); } diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h index 3e8b6a2..4fceefb 100644 --- a/src/soc/intel/baytrail/include/soc/romstage.h +++ b/src/soc/intel/baytrail/include/soc/romstage.h @@ -24,13 +24,8 @@ #include <arch/cpu.h> #include <soc/mrc_wrapper.h> -struct romstage_params { - unsigned long bist; - struct mrc_params *mrc_params; -}; - -void mainboard_romstage_entry(struct romstage_params *params); -void romstage_common(struct romstage_params *params); +void mainboard_romstage_entry(struct mrc_params *mrc_params); +void romstage_common(struct mrc_params *mrc_params); void raminit(struct mrc_params *mp, int prev_sleep_state); void gfx_init(void); diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 5621dd1..73991df 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -99,10 +99,7 @@ /* Entry from cache-as-ram.inc. */ static void romstage_main(uint64_t tsc, uint32_t bist) { - struct romstage_params rp = { - .bist = bist, - .mrc_params = NULL, - }; + struct mrc_params mrc_params; /* Save initial timestamp from bootblock. */ timestamp_init(tsc); @@ -127,7 +124,7 @@ gfx_init(); /* Call into mainboard. */ - mainboard_romstage_entry(&rp); + mainboard_romstage_entry(&mrc_params); platform_enter_postcar(); @@ -212,7 +209,7 @@ } /* Entry from the mainboard. */ -void romstage_common(struct romstage_params *params) +void romstage_common(struct mrc_params *mrc_params) { struct chipset_power_state *ps; int prev_sleep_state; @@ -231,7 +228,7 @@ /* Initialize RAM */ - raminit(params->mrc_params, prev_sleep_state); + raminit(mrc_params, prev_sleep_state); timestamp_add_now(TS_AFTER_INITRAM); -- To view, visit https://review.coreboot.org/c/coreboot/+/32966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54b7c6af2f47e85f66e67c81b7a0510488ca8da2 Gerrit-Change-Number: 32966 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mb/lenovo/x200: Use lower C-states on battery
by Arthur Heymans (Code Review) 13 Oct '19

13 Oct '19

Hello Alexander Couzens, Patrick Rudolph, Duncan Laurie, Paul Menzel, Stefan Reinauer, build bot (Jenkins), Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/22932 to look at the new patch set (#16). Change subject: mb/lenovo/x200: Use lower C-states on battery ...................................................................... mb/lenovo/x200: Use lower C-states on battery This adds an array with C6 as lowest CPU cstate on battery for thinkpad x200. This is changed when the PNOT method is called which notifies the CPU to update C- and P-states. This adds a weak function get_bat_cst_entries which is analogous to get_cst_entries and expects an implementation in a mainboard specific code. For other boards the same C-states are on battery as on AC. Without thorough testing this seems to shave off something between ~0.5W and ~1W while idle compared to having C3/C4 as the lowest C-state. Change-Id: Idf32ee2ac3272fee74ce3b92b2c537cb722991d7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/include/arch/acpigen.h M src/cpu/intel/speedstep/acpi.c M src/mainboard/lenovo/x200/cstates.c 3 files changed, 61 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/22932/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/22932 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf32ee2ac3272fee74ce3b92b2c537cb722991d7 Gerrit-Change-Number: 22932 Gerrit-PatchSet: 16 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/lenovo/x200: Use lower C-states on battery
by Arthur Heymans (Code Review) 13 Oct '19

13 Oct '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/22932 ) Change subject: mb/lenovo/x200: Use lower C-states on battery ...................................................................... Patch Set 15: (2 comments) It would be better if this information was passed via devicetree and then checked if both CPU and SB support the C-state. For now this may be good enough? https://review.coreboot.org/c/coreboot/+/22932/15/src/cpu/intel/speedstep/a… File src/cpu/intel/speedstep/acpi.c: https://review.coreboot.org/c/coreboot/+/22932/15/src/cpu/intel/speedstep/a… PS15, Line 159: acpigen_emit_namestring("PWRS") > Does PWRS exist on all callers? PWRS is in the GNVS of i82810{g,i,j}x which are all the platforms using this code. https://review.coreboot.org/c/coreboot/+/22932/15/src/cpu/intel/speedstep/a… PS15, Line 163: num_bat_cstates > Always true? Can be 0, just like num_cstates can be 0. -- To view, visit https://review.coreboot.org/c/coreboot/+/22932 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf32ee2ac3272fee74ce3b92b2c537cb722991d7 Gerrit-Change-Number: 22932 Gerrit-PatchSet: 15 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 13 Oct 2019 18:29:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/lenovo/x200: Use lower C-states on battery
by Patrick Rudolph (Code Review) 13 Oct '19

13 Oct '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/22932 ) Change subject: mb/lenovo/x200: Use lower C-states on battery ...................................................................... Patch Set 15: (2 comments) https://review.coreboot.org/c/coreboot/+/22932/15/src/cpu/intel/speedstep/a… File src/cpu/intel/speedstep/acpi.c: https://review.coreboot.org/c/coreboot/+/22932/15/src/cpu/intel/speedstep/a… PS15, Line 159: acpigen_emit_namestring("PWRS") Does PWRS exist on all callers? https://review.coreboot.org/c/coreboot/+/22932/15/src/cpu/intel/speedstep/a… PS15, Line 163: num_bat_cstates Always true? -- To view, visit https://review.coreboot.org/c/coreboot/+/22932 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf32ee2ac3272fee74ce3b92b2c537cb722991d7 Gerrit-Change-Number: 22932 Gerrit-PatchSet: 15 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 13 Oct 2019 18:20:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: nb/intel/sandybridge: Fix domain resources
by Arthur Heymans (Code Review) 13 Oct '19

13 Oct '19

Arthur Heymans has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/27118 ) Change subject: nb/intel/sandybridge: Fix domain resources ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/27118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c69ff8ec269d472f034fd79aafb337463193adf Gerrit-Change-Number: 27118 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: abandon

1 0

Change in coreboot[master]: soc/intel/skylake: clean up unused header
by Arthur Heymans (Code Review) 13 Oct '19

13 Oct '19

Arthur Heymans has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/31309 ) Change subject: soc/intel/skylake: clean up unused header ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/31309 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifde73533085bf602ffc4595d4292c54fe5e823e7 Gerrit-Change-Number: 31309 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2019