Arthur Heymans has abandoned this change. ( https://review.coreboot.org/c/libgfxinit/+/21066 )
Change subject: [TEST]Transcoder setup: Increase timeout on PIPExCONF status read
......................................................................
Abandoned
Might resume this later, but abandoning for now. It didn't fix anything iirc.
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Gerrit-Change-Number: 21066
Gerrit-PatchSet: 1
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Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35994
to look at the new patch set (#10).
Change subject: cpu/intel/core2: Cache XIP romstage with C_ENVIRONMENT_BOOTBLOCK.
......................................................................
cpu/intel/core2: Cache XIP romstage with C_ENVIRONMENT_BOOTBLOCK.
Tested on Thinkpad X200: the romstage execution speeds are back to
pre-C_ENVIRONMENT_BOOTBLOCK levels.
Change-Id: Id0b50d2f56e7cc0e055cdc8b9aa28794327eca28
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/cpu/intel/model_1067x/Kconfig
M src/cpu/intel/model_6fx/Kconfig
2 files changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/35994/10
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35995 )
Change subject: nb/intel/gm45: Don't run graphics init on s3 resume
......................................................................
Patch Set 8: Code-Review+2
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35994 )
Change subject: cpu/intel/core2: Cache XIP romstage with C_ENVIRONMENT_BOOTBLOCK.
......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35994/9/src/cpu/x86/mtrr/xip_cache…
File src/cpu/x86/mtrr/xip_cache.c:
https://review.coreboot.org/c/coreboot/+/35994/9/src/cpu/x86/mtrr/xip_cache…
PS9, Line 58: if (end < ALIGN_UP(base, mtrr_mask_size) &&
trailing statements should be on next line
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Gerrit-PatchSet: 9
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
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Gerrit-Comment-Date: Sun, 13 Oct 2019 13:12:11 +0000
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35994 )
Change subject: cpu/intel/core2: Cache XIP romstage with C_ENVIRONMENT_BOOTBLOCK.
......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35994/7/src/cpu/x86/mtrr/xip_cache…
File src/cpu/x86/mtrr/xip_cache.c:
https://review.coreboot.org/c/coreboot/+/35994/7/src/cpu/x86/mtrr/xip_cache…
PS7, Line 58: if (end < ALIGN_UP(base, mtrr_mask_size) &&
trailing statements should be on next line
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Gerrit-Change-Number: 35994
Gerrit-PatchSet: 7
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
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Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
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Gerrit-Comment-Date: Sun, 13 Oct 2019 12:50:05 +0000
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Gerrit-MessageType: comment
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35994
to look at the new patch set (#7).
Change subject: cpu/intel/core2: Cache XIP romstage with C_ENVIRONMENT_BOOTBLOCK.
......................................................................
cpu/intel/core2: Cache XIP romstage with C_ENVIRONMENT_BOOTBLOCK.
Tested on Thinkpad X200: the romstage execution speeds are back to
pre-C_ENVIRONMENT_BOOTBLOCK levels.
Change-Id: Id0b50d2f56e7cc0e055cdc8b9aa28794327eca28
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/cpu/intel/model_1067x/Kconfig
M src/cpu/intel/model_6fx/Kconfig
M src/cpu/x86/mtrr/xip_cache.c
3 files changed, 10 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/35994/7
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Gerrit-Change-Number: 35994
Gerrit-PatchSet: 7
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