coreboot-gerrit October 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: ec/acpi/ec.c Link EC code in bootblock & verstage
by Arthur Heymans (Code Review) 12 Oct '19

12 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35950 ) Change subject: ec/acpi/ec.c Link EC code in bootblock & verstage ...................................................................... ec/acpi/ec.c Link EC code in bootblock & verstage This allows to read and set bits in the EC ram in the bootblock or verstage. This can be useful if one needs to read a keyboard key as an input for get_recovery_mode_switch in vboot. Change-Id: I20b2264012b2a364a4157d85bfe5a2303cc5e677 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/ec/acpi/Makefile.inc 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/35950/1 diff --git a/src/ec/acpi/Makefile.inc b/src/ec/acpi/Makefile.inc index fae8fbf..34c113b 100644 --- a/src/ec/acpi/Makefile.inc +++ b/src/ec/acpi/Makefile.inc @@ -1,7 +1,9 @@ ifeq ($(CONFIG_EC_ACPI),y) -ramstage-y += ec.c +bootblock-y += ec.c +verstage-y += ec.c romstage-y += ec.c +ramstage-y += ec.c smm-y += ec.c endif -- To view, visit https://review.coreboot.org/c/coreboot/+/35950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20b2264012b2a364a4157d85bfe5a2303cc5e677 Gerrit-Change-Number: 35950 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/inteltool: remove unsupported MSRs for 06_9EH
by Maxim Polyakov (Code Review) 12 Oct '19

12 Oct '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35916 ) Change subject: util/inteltool: remove unsupported MSRs for 06_9EH ...................................................................... util/inteltool: remove unsupported MSRs for 06_9EH Change-Id: I5c1e4d20efa7630bf4e6210591790055ead0161c Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M util/inteltool/cpu.c 1 file changed, 0 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/35916/1 diff --git a/util/inteltool/cpu.c b/util/inteltool/cpu.c index 6c72922..245ea22 100644 --- a/util/inteltool/cpu.c +++ b/util/inteltool/cpu.c @@ -1738,22 +1738,6 @@ { 0x0600, "IA32_DS_AREA" }, { 0x064E, "MSR_PPERF"}, { 0x0653, "MSR_CORE_HDC_RESIDENCY"}, - { 0x0680, "MSR_LASTBRANCH_0_FROM_IP" }, - { 0x0681, "MSR_LASTBRANCH_1_FROM_IP" }, - { 0x0682, "MSR_LASTBRANCH_2_FROM_IP" }, - { 0x0683, "MSR_LASTBRANCH_3_FROM_IP" }, - { 0x0684, "MSR_LASTBRANCH_4_FROM_IP" }, - { 0x0685, "MSR_LASTBRANCH_5_FROM_IP" }, - { 0x0686, "MSR_LASTBRANCH_6_FROM_IP" }, - { 0x0687, "MSR_LASTBRANCH_7_FROM_IP" }, - { 0x0688, "MSR_LASTBRANCH_8_FROM_IP" }, - { 0x0689, "MSR_LASTBRANCH_9_FROM_IP" }, - { 0x068a, "MSR_LASTBRANCH_10_FROM_IP" }, - { 0x068b, "MSR_LASTBRANCH_11_FROM_IP" }, - { 0x068c, "MSR_LASTBRANCH_12_FROM_IP" }, - { 0x068d, "MSR_LASTBRANCH_13_FROM_IP" }, - { 0x068e, "MSR_LASTBRANCH_14_FROM_IP" }, - { 0x068f, "MSR_LASTBRANCH_15_FROM_IP" }, { 0x0690, "MSR_LASTBRANCH_16_FROM_IP" }, { 0x0691, "MSR_LASTBRANCH_17_FROM_IP" }, { 0x0692, "MSR_LASTBRANCH_18_FROM_IP" }, @@ -1770,22 +1754,6 @@ { 0x069D, "MSR_LASTBRANCH_29_FROM_IP" }, { 0x069E, "MSR_LASTBRANCH_30_FROM_IP" }, { 0x069F, "MSR_LASTBRANCH_31_FROM_IP" }, - { 0x06c0, "MSR_LASTBRANCH_0_TO_IP" }, - { 0x06c1, "MSR_LASTBRANCH_1_TO_IP" }, - { 0x06c2, "MSR_LASTBRANCH_2_TO_IP" }, - { 0x06c3, "MSR_LASTBRANCH_3_TO_IP" }, - { 0x06c4, "MSR_LASTBRANCH_4_TO_IP" }, - { 0x06c5, "MSR_LASTBRANCH_5_TO_IP" }, - { 0x06c6, "MSR_LASTBRANCH_6_TO_IP" }, - { 0x06c7, "MSR_LASTBRANCH_7_TO_IP" }, - { 0x06c8, "MSR_LASTBRANCH_8_TO_IP" }, - { 0x06c9, "MSR_LASTBRANCH_9_TO_IP" }, - { 0x06ca, "MSR_LASTBRANCH_10_TO_IP" }, - { 0x06cb, "MSR_LASTBRANCH_11_TO_IP" }, - { 0x06cc, "MSR_LASTBRANCH_12_TO_IP" }, - { 0x06cd, "MSR_LASTBRANCH_13_TO_IP" }, - { 0x06ce, "MSR_LASTBRANCH_14_TO_IP" }, - { 0x06cf, "MSR_LASTBRANCH_15_TO_IP" }, { 0x06d0, "MSR_LASTBRANCH_16_TO_IP" }, { 0x06d1, "MSR_LASTBRANCH_17_TO_IP" }, { 0x06d2, "MSR_LASTBRANCH_18_TO_IP" }, -- To view, visit https://review.coreboot.org/c/coreboot/+/35916 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c1e4d20efa7630bf4e6210591790055ead0161c Gerrit-Change-Number: 35916 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/inteltool: fix 6d0H-6dfH MSR names for 06_9EH
by Maxim Polyakov (Code Review) 12 Oct '19

12 Oct '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35915 ) Change subject: util/inteltool: fix 6d0H-6dfH MSR names for 06_9EH ...................................................................... util/inteltool: fix 6d0H-6dfH MSR names for 06_9EH Change-Id: I92e8f5194114f7756e3858ff13c207daebe8167c Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M util/inteltool/cpu.c 1 file changed, 16 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/35915/1 diff --git a/util/inteltool/cpu.c b/util/inteltool/cpu.c index 446fd82..6c72922 100644 --- a/util/inteltool/cpu.c +++ b/util/inteltool/cpu.c @@ -1786,22 +1786,22 @@ { 0x06cd, "MSR_LASTBRANCH_13_TO_IP" }, { 0x06ce, "MSR_LASTBRANCH_14_TO_IP" }, { 0x06cf, "MSR_LASTBRANCH_15_TO_IP" }, - { 0x06d0, "MSR_LASTBRANCH_16_FROM_IP" }, - { 0x06d1, "MSR_LASTBRANCH_17_FROM_IP" }, - { 0x06d2, "MSR_LASTBRANCH_18_FROM_IP" }, - { 0x06d3, "MSR_LASTBRANCH_19_FROM_IP" }, - { 0x06d4, "MSR_LASTBRANCH_20_FROM_IP" }, - { 0x06d5, "MSR_LASTBRANCH_21_FROM_IP" }, - { 0x06d6, "MSR_LASTBRANCH_22_FROM_IP" }, - { 0x06d7, "MSR_LASTBRANCH_23_FROM_IP" }, - { 0x06d8, "MSR_LASTBRANCH_24_FROM_IP" }, - { 0x06d9, "MSR_LASTBRANCH_25_FROM_IP" }, - { 0x06da, "MSR_LASTBRANCH_26_FROM_IP" }, - { 0x06db, "MSR_LASTBRANCH_27_FROM_IP" }, - { 0x06dc, "MSR_LASTBRANCH_28_FROM_IP" }, - { 0x06dd, "MSR_LASTBRANCH_29_FROM_IP" }, - { 0x06de, "MSR_LASTBRANCH_30_FROM_IP" }, - { 0x06df, "MSR_LASTBRANCH_31_FROM_IP" }, + { 0x06d0, "MSR_LASTBRANCH_16_TO_IP" }, + { 0x06d1, "MSR_LASTBRANCH_17_TO_IP" }, + { 0x06d2, "MSR_LASTBRANCH_18_TO_IP" }, + { 0x06d3, "MSR_LASTBRANCH_19_TO_IP" }, + { 0x06d4, "MSR_LASTBRANCH_20_TO_IP" }, + { 0x06d5, "MSR_LASTBRANCH_21_TO_IP" }, + { 0x06d6, "MSR_LASTBRANCH_22_TO_IP" }, + { 0x06d7, "MSR_LASTBRANCH_23_TO_IP" }, + { 0x06d8, "MSR_LASTBRANCH_24_TO_IP" }, + { 0x06d9, "MSR_LASTBRANCH_25_TO_IP" }, + { 0x06da, "MSR_LASTBRANCH_26_TO_IP" }, + { 0x06db, "MSR_LASTBRANCH_27_TO_IP" }, + { 0x06dc, "MSR_LASTBRANCH_28_TO_IP" }, + { 0x06dd, "MSR_LASTBRANCH_29_TO_IP" }, + { 0x06de, "MSR_LASTBRANCH_30_TO_IP" }, + { 0x06df, "MSR_LASTBRANCH_31_TO_IP" }, { 0x06E0, "IA32_TSC_DEADLINE"}, { 0x0771, "IA32_HWP_CAPABILITIES"}, { 0x0773, "IA32_HWP_INTERRUPT"}, -- To view, visit https://review.coreboot.org/c/coreboot/+/35915 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92e8f5194114f7756e3858ff13c207daebe8167c Gerrit-Change-Number: 35915 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/inteltool/cpu: fix IA32_PLATFORM_ID MSR addr
by Maxim Polyakov (Code Review) 12 Oct '19

12 Oct '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35913 ) Change subject: util/inteltool/cpu: fix IA32_PLATFORM_ID MSR addr ...................................................................... util/inteltool/cpu: fix IA32_PLATFORM_ID MSR addr According to the documentation [1], IA32_PLATFORM_ID MSR register address should be 17H. [1] Table 2-2. Intel (R) 64 and IA-32 Architectures Software Developer’s Manual. Volume 4: Model-Specific Registers. May 2019. Order Number: 335592-070US Change-Id: I9a16b162db51d21c7849b3c08c987ab341845b1e Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M util/inteltool/cpu.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/35913/1 diff --git a/util/inteltool/cpu.c b/util/inteltool/cpu.c index d2c8ede..12b7dcb 100644 --- a/util/inteltool/cpu.c +++ b/util/inteltool/cpu.c @@ -1539,7 +1539,7 @@ */ static const msr_entry_t model96ex_global_msrs[] = { - { 0x0000, "IA32_PLATFORM_ID"}, + { 0x0017, "IA32_PLATFORM_ID"}, { 0x0080, "MSR_TRACE_HUB_STH_ACPIBAR_BASE"}, { 0x00CE, "MSR_PLATFORM_INFO"}, { 0x0198, "IA32_PERF_STATUS"}, -- To view, visit https://review.coreboot.org/c/coreboot/+/35913 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a16b162db51d21c7849b3c08c987ab341845b1e Gerrit-Change-Number: 35913 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/inteltool: remove duplicate MSR for 06_9EH
by Maxim Polyakov (Code Review) 12 Oct '19

12 Oct '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35914 ) Change subject: util/inteltool: remove duplicate MSR for 06_9EH ...................................................................... util/inteltool: remove duplicate MSR for 06_9EH Change-Id: I34981a69ad027444bc757449db2366f51c13f0e3 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M util/inteltool/cpu.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/35914/1 diff --git a/util/inteltool/cpu.c b/util/inteltool/cpu.c index 12b7dcb..446fd82 100644 --- a/util/inteltool/cpu.c +++ b/util/inteltool/cpu.c @@ -1634,7 +1634,6 @@ { 0x01F3, "IA32_SMRR_PHYSMASK"}, { 0x01F4, "MSR_PRMRR_PHYS_BASE"}, { 0x01F5, "MSR_PRMRR_PHYS_MASK"}, - { 0x01F4, "MSR_PRMRR_PHYS_BASE"}, { 0x01FB, "MSR_PRMRR_VALID_CONFIG"}, { 0x01FC, "MSR_POWER_CTL"}, { 0x0200, "IA32_MTRR_PHYSBASE0"}, -- To view, visit https://review.coreboot.org/c/coreboot/+/35914 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34981a69ad027444bc757449db2366f51c13f0e3 Gerrit-Change-Number: 35914 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/biostar/am1ml: Use ite's common early_serial functions
by HAOUAS Elyes (Code Review) 12 Oct '19

12 Oct '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35966 ) Change subject: mb/biostar/am1ml: Use ite's common early_serial functions ...................................................................... mb/biostar/am1ml: Use ite's common early_serial functions Change-Id: I0b1356420c9ae419b2a0a247b9dc6c8e92b7689a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/biostar/am1ml/romstage.c 1 file changed, 28 insertions(+), 52 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/35966/1 diff --git a/src/mainboard/biostar/am1ml/romstage.c b/src/mainboard/biostar/am1ml/romstage.c index 721df67..a93c978 100644 --- a/src/mainboard/biostar/am1ml/romstage.c +++ b/src/mainboard/biostar/am1ml/romstage.c @@ -24,8 +24,6 @@ #include <superio/ite/common/ite.h> #include <superio/ite/it8728f/it8728f.h> - -#define ITE_CONFIG_REG_CC 0x02 #define SERIAL_DEV PNP_DEV(0x2e, IT8728F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8728F_GPIO) #define ENVC_DEV PNP_DEV(0x2e, IT8728F_EC) @@ -34,62 +32,40 @@ #define MMIO_NON_POSTED_END 0xfedfffff #define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x)) - -static void it_sio_write(pnp_devfn_t dev, u8 reg, u8 value) -{ - pnp_set_logical_device(dev); - pnp_write_config(dev, reg, value); -} - -static void ite_enter_conf(pnp_devfn_t dev) -{ - u16 port = dev >> 8; - - outb(0x87, port); - outb(0x01, port); - outb(0x55, port); - outb((port == 0x4e) ? 0xaa : 0x55, port); -} - -static void ite_exit_conf(pnp_devfn_t dev) -{ - it_sio_write(dev, ITE_CONFIG_REG_CC, 0x02); -} - static void ite_evc_conf(pnp_devfn_t dev) { - ite_enter_conf(dev); - it_sio_write(dev, 0xf1, 0x40); - it_sio_write(dev, 0xf4, 0x80); - it_sio_write(dev, 0xf5, 0x00); - it_sio_write(dev, 0xf6, 0xf0); - it_sio_write(dev, 0xf9, 0x48); - it_sio_write(dev, 0xfa, 0x00); - it_sio_write(dev, 0xfb, 0x00); - ite_exit_conf(dev); + pnp_enter_conf_state(dev); + ite_sio_write(dev, 0xf1, 0x40); + ite_sio_write(dev, 0xf4, 0x80); + ite_sio_write(dev, 0xf5, 0x00); + ite_sio_write(dev, 0xf6, 0xf0); + ite_sio_write(dev, 0xf9, 0x48); + ite_sio_write(dev, 0xfa, 0x00); + ite_sio_write(dev, 0xfb, 0x00); + pnp_exit_conf_state(dev); } static void ite_gpio_conf(pnp_devfn_t dev) { - ite_enter_conf (dev); - it_sio_write(dev, 0x25, 0x80); - it_sio_write(dev, 0x26, 0x07); - it_sio_write(dev, 0x28, 0x81); - it_sio_write(dev, 0x2c, 0x06); - it_sio_write(dev, 0x72, 0x00); - it_sio_write(dev, 0x73, 0x00); - it_sio_write(dev, 0xb3, 0x01); - it_sio_write(dev, 0xb8, 0x00); - it_sio_write(dev, 0xc0, 0x00); - it_sio_write(dev, 0xc3, 0x00); - it_sio_write(dev, 0xc8, 0x00); - it_sio_write(dev, 0xc9, 0x07); - it_sio_write(dev, 0xcb, 0x01); - it_sio_write(dev, 0xf0, 0x10); - it_sio_write(dev, 0xf4, 0x27); - it_sio_write(dev, 0xf8, 0x20); - it_sio_write(dev, 0xf9, 0x01); - ite_exit_conf(dev); + pnp_enter_conf_state(dev); + ite_sio_write(dev, 0x25, 0x80); + ite_sio_write(dev, 0x26, 0x07); + ite_sio_write(dev, 0x28, 0x81); + ite_sio_write(dev, 0x2c, 0x06); + ite_sio_write(dev, 0x72, 0x00); + ite_sio_write(dev, 0x73, 0x00); + ite_sio_write(dev, 0xb3, 0x01); + ite_sio_write(dev, 0xb8, 0x00); + ite_sio_write(dev, 0xc0, 0x00); + ite_sio_write(dev, 0xc3, 0x00); + ite_sio_write(dev, 0xc8, 0x00); + ite_sio_write(dev, 0xc9, 0x07); + ite_sio_write(dev, 0xcb, 0x01); + ite_sio_write(dev, 0xf0, 0x10); + ite_sio_write(dev, 0xf4, 0x27); + ite_sio_write(dev, 0xf8, 0x20); + ite_sio_write(dev, 0xf9, 0x01); + pnp_exit_conf_state(dev); } void board_BeforeAgesa(struct sysinfo *cb) -- To view, visit https://review.coreboot.org/c/coreboot/+/35966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b1356420c9ae419b2a0a247b9dc6c8e92b7689a Gerrit-Change-Number: 35966 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/roda/rk886ex: Use pnp_write_config function
by HAOUAS Elyes (Code Review) 12 Oct '19

12 Oct '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35965 ) Change subject: mb/roda/rk886ex: Use pnp_write_config function ...................................................................... mb/roda/rk886ex: Use pnp_write_config function Change-Id: Ic56367d64b9304b36f5ba5a4b7d5237574eb73ae Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/roda/rk886ex/romstage.c 1 file changed, 22 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/35965/1 diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index f550632..02c2217 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -69,13 +69,6 @@ outb(0xaa, port); } -static void pnp_write_register(pnp_devfn_t dev, int reg, int val) -{ - unsigned int port = dev >> 8; - outb(reg, port); - outb(val, port+1); -} - static void early_superio_config(void) { pnp_devfn_t dev; @@ -83,30 +76,30 @@ dev = PNP_DEV(0x2e, 0x00); pnp_enter_ext_func_mode(dev); - pnp_write_register(dev, 0x01, 0x94); /* Extended Parport modes */ - pnp_write_register(dev, 0x02, 0x88); /* UART power on */ - pnp_write_register(dev, 0x03, 0x72); /* Floppy */ - pnp_write_register(dev, 0x04, 0x01); /* EPP + SPP */ - pnp_write_register(dev, 0x14, 0x03); /* Floppy */ - pnp_write_register(dev, 0x20, (0x3f0 >> 2)); /* Floppy */ - pnp_write_register(dev, 0x23, (0x378 >> 2)); /* PP base */ - pnp_write_register(dev, 0x24, (0x3f8 >> 2)); /* UART1 base */ - pnp_write_register(dev, 0x25, (0x2f8 >> 2)); /* UART2 base */ - pnp_write_register(dev, 0x26, (2 << 4) | 0); /* FDC + PP DMA */ - pnp_write_register(dev, 0x27, (6 << 4) | 7); /* FDC + PP DMA */ - pnp_write_register(dev, 0x28, (4 << 4) | 3); /* UART1,2 IRQ */ + pnp_write_config(dev, 0x01, 0x94); /* Extended Parport modes */ + pnp_write_config(dev, 0x02, 0x88); /* UART power on */ + pnp_write_config(dev, 0x03, 0x72); /* Floppy */ + pnp_write_config(dev, 0x04, 0x01); /* EPP + SPP */ + pnp_write_config(dev, 0x14, 0x03); /* Floppy */ + pnp_write_config(dev, 0x20, (0x3f0 >> 2)); /* Floppy */ + pnp_write_config(dev, 0x23, (0x378 >> 2)); /* PP base */ + pnp_write_config(dev, 0x24, (0x3f8 >> 2)); /* UART1 base */ + pnp_write_config(dev, 0x25, (0x2f8 >> 2)); /* UART2 base */ + pnp_write_config(dev, 0x26, (2 << 4) | 0); /* FDC + PP DMA */ + pnp_write_config(dev, 0x27, (6 << 4) | 7); /* FDC + PP DMA */ + pnp_write_config(dev, 0x28, (4 << 4) | 3); /* UART1,2 IRQ */ /* These are the SMI status registers in the SIO: */ - pnp_write_register(dev, 0x30, (0x600 >> 4)); /* Runtime Register Block Base */ + pnp_write_config(dev, 0x30, (0x600 >> 4)); /* Runtime Register Block Base */ - pnp_write_register(dev, 0x31, 0x00); /* GPIO1 DIR */ - pnp_write_register(dev, 0x32, 0x00); /* GPIO1 POL */ - pnp_write_register(dev, 0x33, 0x40); /* GPIO2 DIR */ - pnp_write_register(dev, 0x34, 0x00); /* GPIO2 POL */ - pnp_write_register(dev, 0x35, 0xff); /* GPIO3 DIR */ - pnp_write_register(dev, 0x36, 0x00); /* GPIO3 POL */ - pnp_write_register(dev, 0x37, 0xe0); /* GPIO4 DIR */ - pnp_write_register(dev, 0x38, 0x00); /* GPIO4 POL */ - pnp_write_register(dev, 0x39, 0x80); /* GPIO4 POL */ + pnp_write_config(dev, 0x31, 0x00); /* GPIO1 DIR */ + pnp_write_config(dev, 0x32, 0x00); /* GPIO1 POL */ + pnp_write_config(dev, 0x33, 0x40); /* GPIO2 DIR */ + pnp_write_config(dev, 0x34, 0x00); /* GPIO2 POL */ + pnp_write_config(dev, 0x35, 0xff); /* GPIO3 DIR */ + pnp_write_config(dev, 0x36, 0x00); /* GPIO3 POL */ + pnp_write_config(dev, 0x37, 0xe0); /* GPIO4 DIR */ + pnp_write_config(dev, 0x38, 0x00); /* GPIO4 POL */ + pnp_write_config(dev, 0x39, 0x80); /* GPIO4 POL */ pnp_exit_ext_func_mode(dev); } -- To view, visit https://review.coreboot.org/c/coreboot/+/35965 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic56367d64b9304b36f5ba5a4b7d5237574eb73ae Gerrit-Change-Number: 35965 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/getac/p470: Use pnp_write_config function
by HAOUAS Elyes (Code Review) 12 Oct '19

12 Oct '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35964 ) Change subject: mb/getac/p470: Use pnp_write_config function ...................................................................... mb/getac/p470: Use pnp_write_config function Change-Id: Iaf9a4608f1b7d25cf5d8dbe2c1489b3d2d00f25a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/getac/p470/romstage.c 1 file changed, 31 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/35964/1 diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index a7c64bd..15930af 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -90,13 +90,6 @@ outb(0xaa, port); } -static void pnp_write_register(pnp_devfn_t dev, int reg, int val) -{ - unsigned int port = dev >> 8; - outb(reg, port); - outb(val, port+1); -} - static void early_superio_config(void) { pnp_devfn_t dev; @@ -104,40 +97,40 @@ dev = PNP_DEV(0x4e, 0x00); pnp_enter_ext_func_mode(dev); - pnp_write_register(dev, 0x02, 0x0e); // UART power - pnp_write_register(dev, 0x1b, (0x3e8 >> 2)); // UART3 base - pnp_write_register(dev, 0x1c, (0x2e8 >> 2)); // UART4 base - pnp_write_register(dev, 0x1d, (5 << 4) | 11); // UART3,4 IRQ - pnp_write_register(dev, 0x1e, 1); // no 32khz clock - pnp_write_register(dev, 0x24, (0x3f8 >> 2)); // UART1 base - pnp_write_register(dev, 0x28, (4 << 4) | 0); // UART1,2 IRQ - pnp_write_register(dev, 0x2c, 0); // DMA0 FIR - pnp_write_register(dev, 0x30, (0x600 >> 4)); // Runtime Register Block Base + pnp_write_config(dev, 0x02, 0x0e); // UART power + pnp_write_config(dev, 0x1b, (0x3e8 >> 2)); // UART3 base + pnp_write_config(dev, 0x1c, (0x2e8 >> 2)); // UART4 base + pnp_write_config(dev, 0x1d, (5 << 4) | 11); // UART3,4 IRQ + pnp_write_config(dev, 0x1e, 1); // no 32khz clock + pnp_write_config(dev, 0x24, (0x3f8 >> 2)); // UART1 base + pnp_write_config(dev, 0x28, (4 << 4) | 0); // UART1,2 IRQ + pnp_write_config(dev, 0x2c, 0); // DMA0 FIR + pnp_write_config(dev, 0x30, (0x600 >> 4)); // Runtime Register Block Base - pnp_write_register(dev, 0x31, 0xce); // GPIO1 DIR - pnp_write_register(dev, 0x32, 0x00); // GPIO1 POL - pnp_write_register(dev, 0x33, 0x0f); // GPIO2 DIR - pnp_write_register(dev, 0x34, 0x00); // GPIO2 POL - pnp_write_register(dev, 0x35, 0xa8); // GPIO3 DIR - pnp_write_register(dev, 0x36, 0x00); // GPIO3 POL - pnp_write_register(dev, 0x37, 0xa8); // GPIO4 DIR - pnp_write_register(dev, 0x38, 0x00); // GPIO4 POL + pnp_write_config(dev, 0x31, 0xce); // GPIO1 DIR + pnp_write_config(dev, 0x32, 0x00); // GPIO1 POL + pnp_write_config(dev, 0x33, 0x0f); // GPIO2 DIR + pnp_write_config(dev, 0x34, 0x00); // GPIO2 POL + pnp_write_config(dev, 0x35, 0xa8); // GPIO3 DIR + pnp_write_config(dev, 0x36, 0x00); // GPIO3 POL + pnp_write_config(dev, 0x37, 0xa8); // GPIO4 DIR + pnp_write_config(dev, 0x38, 0x00); // GPIO4 POL - pnp_write_register(dev, 0x39, 0x00); // GPIO1 OUT - pnp_write_register(dev, 0x40, 0x80); // GPIO2/MISC OUT - pnp_write_register(dev, 0x41, 0x00); // GPIO5 OUT - pnp_write_register(dev, 0x42, 0xa8); // GPIO5 DIR - pnp_write_register(dev, 0x43, 0x00); // GPIO5 POL - pnp_write_register(dev, 0x44, 0x00); // GPIO ALT1 - pnp_write_register(dev, 0x45, 0x50); // GPIO ALT2 - pnp_write_register(dev, 0x46, 0x00); // GPIO ALT3 + pnp_write_config(dev, 0x39, 0x00); // GPIO1 OUT + pnp_write_config(dev, 0x40, 0x80); // GPIO2/MISC OUT + pnp_write_config(dev, 0x41, 0x00); // GPIO5 OUT + pnp_write_config(dev, 0x42, 0xa8); // GPIO5 DIR + pnp_write_config(dev, 0x43, 0x00); // GPIO5 POL + pnp_write_config(dev, 0x44, 0x00); // GPIO ALT1 + pnp_write_config(dev, 0x45, 0x50); // GPIO ALT2 + pnp_write_config(dev, 0x46, 0x00); // GPIO ALT3 - pnp_write_register(dev, 0x48, 0x55); // GPIO ALT5 - pnp_write_register(dev, 0x49, 0x55); // GPIO ALT6 - pnp_write_register(dev, 0x4a, 0x55); // GPIO ALT7 - pnp_write_register(dev, 0x4b, 0x55); // GPIO ALT8 - pnp_write_register(dev, 0x4c, 0x55); // GPIO ALT9 - pnp_write_register(dev, 0x4d, 0x55); // GPIO ALT10 + pnp_write_config(dev, 0x48, 0x55); // GPIO ALT5 + pnp_write_config(dev, 0x49, 0x55); // GPIO ALT6 + pnp_write_config(dev, 0x4a, 0x55); // GPIO ALT7 + pnp_write_config(dev, 0x4b, 0x55); // GPIO ALT8 + pnp_write_config(dev, 0x4c, 0x55); // GPIO ALT9 + pnp_write_config(dev, 0x4d, 0x55); // GPIO ALT10 pnp_exit_ext_func_mode(dev); } -- To view, visit https://review.coreboot.org/c/coreboot/+/35964 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf9a4608f1b7d25cf5d8dbe2c1489b3d2d00f25a Gerrit-Change-Number: 35964 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skylake: Add Lewisburg PCH family SKUs
by Maxim Polyakov (Code Review) 12 Oct '19

12 Oct '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35030 ) Change subject: soc/intel/skylake: Add Lewisburg PCH family SKUs ...................................................................... soc/intel/skylake: Add Lewisburg PCH family SKUs Adds the Lewisburg PCH family product and super SKUs These changes are in accordance with the documentation: [*] page 39, Intel(R) C620 Series Chipset Platform Controller Hub (PCH) Datasheet, May 2019. Document Number: 336067-007US Change-Id: I7eaf2c1bb725ffed66f86c023c415ad17fe5793d Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/skylake/bootblock/report_platform.c 3 files changed, 27 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/35030/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 3ac6560..8de8241 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2713,6 +2713,19 @@ #define PCI_DEVICE_ID_INTEL_SPT_H_HM175 0xa152 #define PCI_DEVICE_ID_INTEL_SPT_H_QM175 0xa153 #define PCI_DEVICE_ID_INTEL_SPT_H_CM238 0xa154 +#define PCI_DEVICE_ID_INTEL_LWB_C621 0xa1c1 +#define PCI_DEVICE_ID_INTEL_LWB_C622 0xa1c2 +#define PCI_DEVICE_ID_INTEL_LWB_C624 0xa1c3 +#define PCI_DEVICE_ID_INTEL_LWB_C625 0xa1c4 +#define PCI_DEVICE_ID_INTEL_LWB_C626 0xa1c5 +#define PCI_DEVICE_ID_INTEL_LWB_C627 0xa1c6 +#define PCI_DEVICE_ID_INTEL_LWB_C628 0xa1c7 +#define PCI_DEVICE_ID_INTEL_LWB_C629 0xa1ca +#define PCI_DEVICE_ID_INTEL_LWB_C624_SUPER 0xa242 +#define PCI_DEVICE_ID_INTEL_LWB_C627_SUPER_1 0xa243 +#define PCI_DEVICE_ID_INTEL_LWB_C621_SUPER 0xa244 +#define PCI_DEVICE_ID_INTEL_LWB_C627_SUPER_2 0xa245 +#define PCI_DEVICE_ID_INTEL_LWB_C628_SUPER 0xa246 #define PCI_DEVICE_ID_INTEL_KBP_H_H270 0xa2c4 #define PCI_DEVICE_ID_INTEL_KBP_H_Z270 0xa2c5 #define PCI_DEVICE_ID_INTEL_KBP_H_Q270 0xa2c6 diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index d7917d6..178b895 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -138,6 +138,7 @@ PCI_DEVICE_ID_INTEL_SPT_H_HM175, PCI_DEVICE_ID_INTEL_SPT_H_QM175, PCI_DEVICE_ID_INTEL_SPT_H_CM238, + PCI_DEVICE_ID_INTEL_SPT_H_CM238, PCI_DEVICE_ID_INTEL_KBP_H_Q270, PCI_DEVICE_ID_INTEL_KBP_H_H270, PCI_DEVICE_ID_INTEL_KBP_H_Z270, diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c index a643bbe..d4d26c1 100644 --- a/src/soc/intel/skylake/bootblock/report_platform.c +++ b/src/soc/intel/skylake/bootblock/report_platform.c @@ -87,6 +87,19 @@ { PCI_DEVICE_ID_INTEL_SPT_H_HM175, "Skylake PCH-H HM175" }, { PCI_DEVICE_ID_INTEL_SPT_H_QM175, "Skylake PCH-H QM175" }, { PCI_DEVICE_ID_INTEL_SPT_H_CM238, "Skylake PCH-H CM238" }, + { PCI_DEVICE_ID_INTEL_LWB_C621, "Lewisburg PCH C621" }, + { PCI_DEVICE_ID_INTEL_LWB_C622, "Lewisburg PCH C622" }, + { PCI_DEVICE_ID_INTEL_LWB_C624, "Lewisburg PCH C624" }, + { PCI_DEVICE_ID_INTEL_LWB_C625, "Lewisburg PCH C625" }, + { PCI_DEVICE_ID_INTEL_LWB_C626, "Lewisburg PCH C626" }, + { PCI_DEVICE_ID_INTEL_LWB_C627, "Lewisburg PCH C627" }, + { PCI_DEVICE_ID_INTEL_LWB_C628, "Lewisburg PCH C628" }, + { PCI_DEVICE_ID_INTEL_LWB_C629, "Lewisburg PCH C629" }, + { PCI_DEVICE_ID_INTEL_LWB_C624_SUPER, "Lewisburg PCH C624 Super Sku" }, + { PCI_DEVICE_ID_INTEL_LWB_C627_SUPER_1, "Lewisburg PCH C627 Super Sku" }, + { PCI_DEVICE_ID_INTEL_LWB_C621_SUPER, "Lewisburg PCH C621 Super Sku" }, + { PCI_DEVICE_ID_INTEL_LWB_C627_SUPER_2, "Lewisburg PCH C627 Super Sku" }, + { PCI_DEVICE_ID_INTEL_LWB_C628_SUPER, "Lewisburg PCH C628 Super Sku" }, { PCI_DEVICE_ID_INTEL_KBP_H_Q270, "Kabylake-H Q270" }, { PCI_DEVICE_ID_INTEL_KBP_H_H270, "Kabylake-H H270" }, { PCI_DEVICE_ID_INTEL_KBP_H_Z270, "Kabylake-H Z270" }, -- To view, visit https://review.coreboot.org/c/coreboot/+/35030 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7eaf2c1bb725ffed66f86c023c415ad17fe5793d Gerrit-Change-Number: 35030 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/hatch/variants/helios: Modify touchscreen power on sequence
by Shelley Chen (Code Review) 11 Oct '19

11 Oct '19

Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35907 ) Change subject: mb/google/hatch/variants/helios: Modify touchscreen power on sequence ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/35907/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/35907/2//COMMIT_MSG@13 PS2, Line 13: TEST > I assume that you tested touchscreen functionality is ok with this CL? Also, looking at the values, they do not match the timings in that data sheet. Can you tell us why you made the timings longer? Were you seeing a failure before? -- To view, visit https://review.coreboot.org/c/coreboot/+/35907 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86c920ff1d5c0b510adde8a37f60003072d5f4e7 Gerrit-Change-Number: 35907 Gerrit-PatchSet: 2 Gerrit-Owner: YenLu Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Assignee: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: YenLu Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Fri, 11 Oct 2019 21:48:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: comment

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