coreboot-gerrit October 2019

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Change in coreboot[master]: mb/google/hatch: Add new touchscreen option for Kohaku
by Tim Wawrzynczak (Code Review) 11 Oct '19

11 Oct '19

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35944 ) Change subject: mb/google/hatch: Add new touchscreen option for Kohaku ...................................................................... mb/google/hatch: Add new touchscreen option for Kohaku The next board rev will have a new option for an Elan touchscreen. Add support for this in the devicetree, as well as use the 'probed' property on both touchscreen options. BUG=b:141957731 BRANCH=none TEST=compiles (next board rev not available yet) Change-Id: I135e693304cbb8dffc0caf4c07846033d6802208 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/hatch/variants/kohaku/overridetree.cb 1 file changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/35944/1 diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index 37914fa..ecf4682 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -179,8 +179,24 @@ register "enable_delay_ms" = "1" # 90 ns register "has_power_resource" = "1" register "disable_gpio_export_in_crs" = "1" + register "probed" = "1" device i2c 4b on end end + + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "probed" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C12)" + register "enable_delay_ms" = "10" + register "enable_off_delay_ms" = "100" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "reset_delay_ms" = "20" + register "reset_off_delay_ms" = "2" + register "has_power_resource" = "1" + device i2c 10 on end + end end # I2C #1 device pci 15.2 on -- To view, visit https://review.coreboot.org/c/coreboot/+/35944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I135e693304cbb8dffc0caf4c07846033d6802208 Gerrit-Change-Number: 35944 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/kunimitsu: drop support for FSP 1.1
by Michael Niewöhner (Code Review) 11 Oct '19

11 Oct '19

Hello Matt DeVillier, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/35922 to review the following change. Change subject: mb/intel/kunimitsu: drop support for FSP 1.1 ...................................................................... mb/intel/kunimitsu: drop support for FSP 1.1 This patch is part of the patch series to drop support for FSP 1.1 in soc/intel/skylake. The following modifications have been done to migrate the board(s) from FSP 1.1 to FSP 2.0: - remove deprecated devicetree VR_RING domain (only 4 domains in FSP 2.0) - add AC/DC loadline values to devicetree (see TODO) - drop FSP-1.1-only romstage.c and spd.c - add FSP parameter DmiVc1 (see TODO) - set FSP board type to "mobile" TODO: - check loadline values again - loadline values in devicetree maybe can dropped again, as Maxim is working on adding missing loadline values in CB:35167 - find out why some boards set DmiVc1 - testing Change-Id: I9d312ac959a7dac4b018d5ca1d007b1347bcf1dd Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/intel/kunimitsu/Kconfig M src/mainboard/intel/kunimitsu/Makefile.inc M src/mainboard/intel/kunimitsu/devicetree.cb D src/mainboard/intel/kunimitsu/romstage.c M src/mainboard/intel/kunimitsu/romstage_fsp20.c M src/mainboard/intel/kunimitsu/spd/Makefile.inc D src/mainboard/intel/kunimitsu/spd/spd.c M src/mainboard/intel/kunimitsu/spd/spd.h 8 files changed, 67 insertions(+), 208 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/35922/1 diff --git a/src/mainboard/intel/kunimitsu/Kconfig b/src/mainboard/intel/kunimitsu/Kconfig index 6396151..26cfe96 100644 --- a/src/mainboard/intel/kunimitsu/Kconfig +++ b/src/mainboard/intel/kunimitsu/Kconfig @@ -19,20 +19,8 @@ select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM select SOC_INTEL_SKYLAKE - -choice - prompt "FSP driver" - default KUNIMITSU_USES_FSP1_1 - -config KUNIMITSU_USES_FSP1_1 - bool "FSP driver 1.1" - -config KUNIMITSU_USES_FSP2_0 - bool "FSP driver 2.0" select MAINBOARD_USES_FSP2_0 -endchoice - config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES select VBOOT_LID_SWITCH diff --git a/src/mainboard/intel/kunimitsu/Makefile.inc b/src/mainboard/intel/kunimitsu/Makefile.inc index 933074b..826c958 100644 --- a/src/mainboard/intel/kunimitsu/Makefile.inc +++ b/src/mainboard/intel/kunimitsu/Makefile.inc @@ -30,6 +30,4 @@ smm-y += smihandler.c -ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y) romstage-srcs := $(subst $(MAINBOARDDIR)/romstage.c,$(MAINBOARDDIR)/romstage_fsp20.c,$(romstage-srcs)) -endif diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index f2c9f43..31dfec1 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -60,82 +60,80 @@ register "PmConfigSlpAMinAssert" = "0x03" - # VR Settings Configuration for 5 Domains - #+----------------+-------+-------+-------------+-------------+-------+ - #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | - #+----------------+-------+-------+-------------+-------------+-------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | 0 | - #| IccMax | 7A | 34A | 34A | 35A | 35A | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | - #+----------------+-------+-------+-------------+-------------+-------+ + # VR Settings Configuration for 4 Domains + #+----------------+-----------+-----------+-------------+----------+ + #| Domain/Setting | SA | IA | GT Unsliced | GT | + #+----------------+-----------+-----------+-------------+----------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #| AC LoadLine | 15 mOhm | 5.7 mOhm | 5.2 mOhm | 5.2 mOhm | + #| DC LoadLine | 14.3 mOhm | 4.83 mOhm | 4.2 mOhm | 4.2 mOhm | + #+----------------+-----------+-----------+-------------+----------+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x10, \ - .psi3threshold = 0x4, \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x1C, \ - .voltage_limit = 0x5F0 \ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(4), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(7), + .voltage_limit = 1520, + .ac_loadline = 1500, + .dc_loadline = 1430, }" register "domain_vr_config[VR_IA_CORE]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x88, \ - .voltage_limit = 0x5F0 \ - }" - register "domain_vr_config[VR_RING]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x88, \ - .voltage_limit = 0x5F0, \ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(34), + .voltage_limit = 1520, + .ac_loadline = 570, + .dc_loadline = 483, }" register "domain_vr_config[VR_GT_UNSLICED]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x8C ,\ - .voltage_limit = 0x5F0 \ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520, + .ac_loadline = 520, + .dc_loadline = 420, }" register "domain_vr_config[VR_GT_SLICED]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x8C, \ - .voltage_limit = 0x5F0 \ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520, + .ac_loadline = 520, + .dc_loadline = 420, }" # Enable Root port 1 and 5. diff --git a/src/mainboard/intel/kunimitsu/romstage.c b/src/mainboard/intel/kunimitsu/romstage.c deleted file mode 100644 index 0312ad1..0000000 --- a/src/mainboard/intel/kunimitsu/romstage.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <gpio.h> -#include <soc/romstage.h> -#include "gpio.h" -#include "spd/spd.h" - -void mainboard_memory_init_params(struct romstage_params *params, - MEMORY_INIT_UPD *memory_params) -{ - spd_memory_init_params(memory_params); - mainboard_fill_dq_map_data(&memory_params->DqByteMapCh0, - &memory_params->DqByteMapCh1); - mainboard_fill_dqs_map_data(&memory_params->DqsMapCpu2DramCh0, - &memory_params->DqsMapCpu2DramCh1); - mainboard_fill_rcomp_res_data(&memory_params->RcompResistor); - mainboard_fill_rcomp_strength_data(&memory_params->RcompTarget); - memory_params->MemorySpdDataLen = SPD_LEN; - memory_params->DqPinsInterleaved = FALSE; -} diff --git a/src/mainboard/intel/kunimitsu/romstage_fsp20.c b/src/mainboard/intel/kunimitsu/romstage_fsp20.c index 2a4474e..ebecdb2 100644 --- a/src/mainboard/intel/kunimitsu/romstage_fsp20.c +++ b/src/mainboard/intel/kunimitsu/romstage_fsp20.c @@ -37,4 +37,7 @@ if (mainboard_has_dual_channel_mem()) mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; mem_cfg->MemorySpdDataLen = SPD_LEN; + mem_cfg->UserBd = BOARD_TYPE_MOBILE; + + mupd->FspmTestConfig.DmiVc1 = 1; } diff --git a/src/mainboard/intel/kunimitsu/spd/Makefile.inc b/src/mainboard/intel/kunimitsu/spd/Makefile.inc index 9856368e..bbcf183 100644 --- a/src/mainboard/intel/kunimitsu/spd/Makefile.inc +++ b/src/mainboard/intel/kunimitsu/spd/Makefile.inc @@ -14,7 +14,6 @@ ## GNU General Public License for more details. ## -romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += spd.c romstage-y += spd_util.c SPD_BIN = $(obj)/spd.bin diff --git a/src/mainboard/intel/kunimitsu/spd/spd.c b/src/mainboard/intel/kunimitsu/spd/spd.c deleted file mode 100644 index db5e24e..0000000 --- a/src/mainboard/intel/kunimitsu/spd/spd.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <fsp/soc_binding.h> -#include <soc/romstage.h> -#include <stdint.h> -#include <string.h> - -#include "spd.h" - -static void mainboard_print_spd_info(uint8_t spd[]) -{ - const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; - const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 }; - const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 }; - const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 }; - const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 }; - const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 }; - const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; - char spd_name[SPD_PART_LEN+1] = { 0 }; - - int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7]; - int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256; - int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7]; - int cols = spd_cols[spd[SPD_ADDRESSING] & 7]; - int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7]; - int devw = spd_devw[spd[SPD_ORGANIZATION] & 7]; - int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7]; - - /* Module type */ - printk(BIOS_INFO, "SPD: module type is "); - switch (spd[SPD_DRAM_TYPE]) { - case SPD_DRAM_DDR3: - printk(BIOS_INFO, "DDR3\n"); - break; - case SPD_DRAM_LPDDR3: - printk(BIOS_INFO, "LPDDR3\n"); - break; - default: - printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]); - break; - } - - /* Module Part Number */ - memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN); - spd_name[SPD_PART_LEN] = 0; - printk(BIOS_INFO, "SPD: module part is %s\n", spd_name); - - printk(BIOS_INFO, - "SPD: banks %d, ranks %d, rows %d, columns %d, density %d Mb\n", - banks, ranks, rows, cols, capmb); - printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n", - devw, busw); - - if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) { - /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */ - printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n", - capmb / 8 * busw / devw * ranks); - } -} - -/* Fill SPD pointers for on-board memory */ -void spd_memory_init_params(MEMORY_INIT_UPD *memory_params) -{ - uintptr_t spd_data; - spd_data = mainboard_get_spd_data(); - - /* Make sure a valid SPD was found */ - if (*(uint8_t *)spd_data == 0) - die("Invalid SPD data."); - - memory_params->MemorySpdPtr00 = spd_data; - if (mainboard_has_dual_channel_mem()) - memory_params->MemorySpdPtr10 = spd_data; - - mainboard_print_spd_info((uint8_t *)spd_data); -} diff --git a/src/mainboard/intel/kunimitsu/spd/spd.h b/src/mainboard/intel/kunimitsu/spd/spd.h index 8bc7336..c6e47f0 100644 --- a/src/mainboard/intel/kunimitsu/spd/spd.h +++ b/src/mainboard/intel/kunimitsu/spd/spd.h @@ -54,7 +54,6 @@ }; return (gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios))); } -void spd_memory_init_params(MEMORY_INIT_UPD *memory_params); void mainboard_fill_dq_map_data(void *dq_map_ch0, void *dq_map_ch1); void mainboard_fill_dqs_map_data(void *dqs_map_ch0, void *dqs_map_ch1); void mainboard_fill_rcomp_res_data(void *rcomp_ptr); -- To view, visit https://review.coreboot.org/c/coreboot/+/35922 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d312ac959a7dac4b018d5ca1d007b1347bcf1dd Gerrit-Change-Number: 35922 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/glados: port to FSP 2.0
by Matt DeVillier (Code Review) 11 Oct '19

11 Oct '19

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35921 ) Change subject: mb/google/glados: port to FSP 2.0 ...................................................................... Patch Set 6: Code-Review+2 verified working on google/chell w/QHD display -- To view, visit https://review.coreboot.org/c/coreboot/+/35921 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id747ef484dfdcb2d346f817976f52073912468d0 Gerrit-Change-Number: 35921 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 11 Oct 2019 03:40:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: HACK trogdor: SoC makefile BLOB support HACK
by mturney mturney (Code Review) 11 Oct '19

11 Oct '19

Hello ashk(a)codeaurora.org, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35508 to look at the new patch set (#8). Change subject: HACK trogdor: SoC makefile BLOB support HACK ...................................................................... HACK trogdor: SoC makefile BLOB support HACK Change-Id: I85a20ef31ec91c6f22221d16fd4c3097c5cb97d1 Signed-off-by: Ashwin Kumar <ashk(a)codeaurora.org> --- M src/soc/qualcomm/sc7180/Makefile.inc 1 file changed, 118 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/35508/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/35508 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85a20ef31ec91c6f22221d16fd4c3097c5cb97d1 Gerrit-Change-Number: 35508 Gerrit-PatchSet: 8 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: ashk(a)codeaurora.org Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: sc7180: Add UART support
by mturney mturney (Code Review) 11 Oct '19

11 Oct '19

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35500 to look at the new patch set (#7). Change subject: sc7180: Add UART support ...................................................................... sc7180: Add UART support This implements the UART driver in SoC + libpayload Developer/Reviewer, be aware of this patch from Napali: https://review.coreboot.org/c/coreboot/+/25373/78 Change-Id: I6494daa108197c030577ac86dab71f9ca6c21bdb Signed-off-by: Roja Rani Yarubandi <rojay(a)codeaurora.org> --- M src/soc/qualcomm/sc7180/Kconfig M src/soc/qualcomm/sc7180/Makefile.inc A src/soc/qualcomm/sc7180/uart.c 3 files changed, 177 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/35500/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/35500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6494daa108197c030577ac86dab71f9ca6c21bdb Gerrit-Change-Number: 35500 Gerrit-PatchSet: 7 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/glados: port to FSP 2.0
by Michael Niewöhner (Code Review) 10 Oct '19

10 Oct '19

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35921 ) Change subject: mb/google/glados: port to FSP 2.0 ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/c/coreboot/+/35921/5/src/mainboard/google/glado… File src/mainboard/google/glados/romstage.c: https://review.coreboot.org/c/coreboot/+/35921/5/src/mainboard/google/glado… PS5, Line 34: /* Turn on keyboard backlight to indicate we are booting */ : const FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd; : if (arch_upd->BootMode != FSP_BOOT_ON_S3_RESUME) : google_chromeec_kbbacklight(25); > remove indent for this whole block Done -- To view, visit https://review.coreboot.org/c/coreboot/+/35921 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id747ef484dfdcb2d346f817976f52073912468d0 Gerrit-Change-Number: 35921 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 10 Oct 2019 19:07:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/glados: port to FSP 2.0
by build bot (Jenkins) (Code Review) 10 Oct '19

10 Oct '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35921 ) Change subject: mb/google/glados: port to FSP 2.0 ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/c/coreboot/+/35921/6/src/mainboard/google/glado… File src/mainboard/google/glados/romstage.c: https://review.coreboot.org/c/coreboot/+/35921/6/src/mainboard/google/glado… PS6, Line 35: const FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd; need consistent spacing around '*' (ctx:WxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/35921 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id747ef484dfdcb2d346f817976f52073912468d0 Gerrit-Change-Number: 35921 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 10 Oct 2019 19:06:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/glados: port to FSP 2.0
by Michael Niewöhner (Code Review) 10 Oct '19

10 Oct '19

1 0

Change in coreboot[master]: mb/google/glados: port to FSP 2.0
by Michael Niewöhner (Code Review) 10 Oct '19

10 Oct '19

Hello Patrick Rudolph, Matt DeVillier, Paul Menzel, build bot (Jenkins), Nico Huber, Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35921 to look at the new patch set (#6). Change subject: mb/google/glados: port to FSP 2.0 ...................................................................... mb/google/glados: port to FSP 2.0 This patch is part of the patch series to drop support for FSP 1.1 in soc/intel/skylake. The following modifications have been done to migrate the board(s) from FSP 1.1 to FSP 2.0: - remove deprecated devicetree VR_RING domain (only 4 domains in FSP 2.0) - switch to using the FSP default VBT TODO: - testing Change-Id: Id747ef484dfdcb2d346f817976f52073912468d0 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/glados/Kconfig M src/mainboard/google/glados/ramstage.c M src/mainboard/google/glados/romstage.c M src/mainboard/google/glados/spd/spd.c M src/mainboard/google/glados/spd/spd_util.h D src/mainboard/google/glados/variants/asuka/data.vbt M src/mainboard/google/glados/variants/asuka/devicetree.cb M src/mainboard/google/glados/variants/asuka/variant.c M src/mainboard/google/glados/variants/baseboard/include/baseboard/variant.h D src/mainboard/google/glados/variants/caroline/data.vbt M src/mainboard/google/glados/variants/caroline/devicetree.cb M src/mainboard/google/glados/variants/caroline/variant.c D src/mainboard/google/glados/variants/cave/data.vbt M src/mainboard/google/glados/variants/cave/devicetree.cb M src/mainboard/google/glados/variants/cave/variant.c D src/mainboard/google/glados/variants/chell/data.vbt M src/mainboard/google/glados/variants/chell/devicetree.cb M src/mainboard/google/glados/variants/chell/variant.c M src/mainboard/google/glados/variants/glados/devicetree.cb M src/mainboard/google/glados/variants/glados/variant.c D src/mainboard/google/glados/variants/lars/data.vbt M src/mainboard/google/glados/variants/lars/devicetree.cb M src/mainboard/google/glados/variants/lars/variant.c D src/mainboard/google/glados/variants/sentry/data.vbt M src/mainboard/google/glados/variants/sentry/devicetree.cb M src/mainboard/google/glados/variants/sentry/variant.c 26 files changed, 192 insertions(+), 304 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/35921/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/35921 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id747ef484dfdcb2d346f817976f52073912468d0 Gerrit-Change-Number: 35921 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/octopus/variants/fleex: Remove NC GPIO_138 and GPIO_139 set...
by John Su (Code Review) 10 Oct '19

10 Oct '19

John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35881 ) Change subject: mb/google/octopus/variants/fleex: Remove NC GPIO_138 and GPIO_139 setting to fix EMR function ...................................................................... mb/google/octopus/variants/fleex: Remove NC GPIO_138 and GPIO_139 setting to fix EMR function Update GPIO_138 and GPIO_139 setting to fix EMR function. BUG=b:141729962,b:141281846 BRANCH=octopus TEST=verify EMR function in Grob360S. Change-Id: I28cef592374fb4aeee2f3d3010cc0e237d62a2fd Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> --- M src/mainboard/google/octopus/variants/fleex/gpio.c 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/35881/1 diff --git a/src/mainboard/google/octopus/variants/fleex/gpio.c b/src/mainboard/google/octopus/variants/fleex/gpio.c index a1e02d2..b7dbd92 100644 --- a/src/mainboard/google/octopus/variants/fleex/gpio.c +++ b/src/mainboard/google/octopus/variants/fleex/gpio.c @@ -26,8 +26,6 @@ PAD_NC(GPIO_67, UP_20K), PAD_NC(GPIO_117, UP_20K), - PAD_NC(GPIO_138, UP_20K), - PAD_NC(GPIO_139, UP_20K), /* GPIO_140 -- PEN_RESET */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_140, 0, DEEP, NONE, Tx1RxDCRx0, DISPUPD), PAD_NC(GPIO_143, UP_20K), -- To view, visit https://review.coreboot.org/c/coreboot/+/35881 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28cef592374fb4aeee2f3d3010cc0e237d62a2fd Gerrit-Change-Number: 35881 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit October 2019