Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35921 )
Change subject: mb/google/glados: port to FSP 2.0
......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35921/5/src/mainboard/google/glado…
File src/mainboard/google/glados/romstage.c:
https://review.coreboot.org/c/coreboot/+/35921/5/src/mainboard/google/glado…
PS5, Line 34: /* Turn on keyboard backlight to indicate we are booting */
: const FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd;
: if (arch_upd->BootMode != FSP_BOOT_ON_S3_RESUME)
: google_chromeec_kbbacklight(25);
remove indent for this whole block
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Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35921 )
Change subject: mb/google/glados: port to FSP 2.0
......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35921/4/src/mainboard/google/glado…
File src/mainboard/google/glados/variants/chell/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/35921/4/src/mainboard/google/glado…
PS4, Line 84: #| IccMax | 7A | 34A | 35A | 35A |
> outside of the scope of this patch, but it appears that chell is using the wrong IccMax values (usin […]
addressed this in a follow-on patch - CB:35958
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35921 )
Change subject: mb/google/glados: port to FSP 2.0
......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35921/5/src/mainboard/google/glado…
File src/mainboard/google/glados/romstage.c:
https://review.coreboot.org/c/coreboot/+/35921/5/src/mainboard/google/glado…
PS5, Line 35: const FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd;
need consistent spacing around '*' (ctx:WxV)
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35921 )
Change subject: mb/google/glados: port to FSP 2.0
......................................................................
Uploaded patch set 5.
(1 comment)
https://review.coreboot.org/c/coreboot/+/35921/4/src/mainboard/google/glado…
File src/mainboard/google/glados/romstage.c:
https://review.coreboot.org/c/coreboot/+/35921/4/src/mainboard/google/glado…
PS4, Line 33: #ifdef EC_ENABLE_KEYBOARD_BACKLIGHT
: /* Turn on keyboard backlight to indicate we are booting */
: const FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd;
: if (arch_upd->BootMode != FSP_BOOT_ON_S3_RESUME)
: google_chromeec_kbbacklight(25);
: #endif
> remove one tab from entire block - #ifdefs are not indented to match current code level
Done
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Hello Patrick Rudolph, Matt DeVillier, Paul Menzel, build bot (Jenkins), Nico Huber, Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35921
to look at the new patch set (#5).
Change subject: mb/google/glados: port to FSP 2.0
......................................................................
mb/google/glados: port to FSP 2.0
This patch is part of the patch series to drop support for FSP 1.1 in
soc/intel/skylake.
The following modifications have been done to migrate the board(s) from
FSP 1.1 to FSP 2.0:
- remove deprecated devicetree VR_RING domain (only 4 domains in FSP 2.0)
- switch to using the FSP default VBT
TODO:
- testing
Change-Id: Id747ef484dfdcb2d346f817976f52073912468d0
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M src/mainboard/google/glados/Kconfig
M src/mainboard/google/glados/ramstage.c
M src/mainboard/google/glados/romstage.c
M src/mainboard/google/glados/spd/spd.c
M src/mainboard/google/glados/spd/spd_util.h
D src/mainboard/google/glados/variants/asuka/data.vbt
M src/mainboard/google/glados/variants/asuka/devicetree.cb
M src/mainboard/google/glados/variants/asuka/variant.c
M src/mainboard/google/glados/variants/baseboard/include/baseboard/variant.h
D src/mainboard/google/glados/variants/caroline/data.vbt
M src/mainboard/google/glados/variants/caroline/devicetree.cb
M src/mainboard/google/glados/variants/caroline/variant.c
D src/mainboard/google/glados/variants/cave/data.vbt
M src/mainboard/google/glados/variants/cave/devicetree.cb
M src/mainboard/google/glados/variants/cave/variant.c
D src/mainboard/google/glados/variants/chell/data.vbt
M src/mainboard/google/glados/variants/chell/devicetree.cb
M src/mainboard/google/glados/variants/chell/variant.c
M src/mainboard/google/glados/variants/glados/devicetree.cb
M src/mainboard/google/glados/variants/glados/variant.c
D src/mainboard/google/glados/variants/lars/data.vbt
M src/mainboard/google/glados/variants/lars/devicetree.cb
M src/mainboard/google/glados/variants/lars/variant.c
D src/mainboard/google/glados/variants/sentry/data.vbt
M src/mainboard/google/glados/variants/sentry/devicetree.cb
M src/mainboard/google/glados/variants/sentry/variant.c
26 files changed, 196 insertions(+), 308 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/35921/5
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/11791 )
Change subject: mainboard/lenovo/t410: Add new port
......................................................................
Patch Set 25:
(1 comment)
https://review.coreboot.org/c/coreboot/+/11791/25/src/mainboard/lenovo/t410…
File src/mainboard/lenovo/t410/vboot-rwa.fmd:
https://review.coreboot.org/c/coreboot/+/11791/25/src/mainboard/lenovo/t410…
PS25, Line 20: 0x11f000
remove the size on this one, to be certain that the COREBOOT region is always align to the top of the flash.
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Hello Stefan Reinauer, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: util/inteltool: set number of CPU cores at run time
......................................................................
util/inteltool: set number of CPU cores at run time
The cores number for some processors exceeds the limit of 8 cores,
which is hardcoded in cpu.c. The patch adds code that determines the
number of processor cores at run time.
Change-Id: I4a4408f286f245d1d109adf98f430ad7a6b1b2fa
Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com>
---
M util/inteltool/cpu.c
1 file changed, 7 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/35918/3
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Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35921 )
Change subject: mb/google/glados: port to FSP 2.0
......................................................................
Patch Set 4: Code-Review+1
(2 comments)
https://review.coreboot.org/c/coreboot/+/35921/4/src/mainboard/google/glado…
File src/mainboard/google/glados/romstage.c:
https://review.coreboot.org/c/coreboot/+/35921/4/src/mainboard/google/glado…
PS4, Line 33: #ifdef EC_ENABLE_KEYBOARD_BACKLIGHT
: /* Turn on keyboard backlight to indicate we are booting */
: const FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd;
: if (arch_upd->BootMode != FSP_BOOT_ON_S3_RESUME)
: google_chromeec_kbbacklight(25);
: #endif
remove one tab from entire block - #ifdefs are not indented to match current code level
https://review.coreboot.org/c/coreboot/+/35921/4/src/mainboard/google/glado…
File src/mainboard/google/glados/variants/chell/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/35921/4/src/mainboard/google/glado…
PS4, Line 84: #| IccMax | 7A | 34A | 35A | 35A |
outside of the scope of this patch, but it appears that chell is using the wrong IccMax values (using ones for SKL-U, not SKL-Y) unless it's intentionally different from the other Y-series boards (caroline/cave)
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35921 )
Change subject: mb/google/glados: port to FSP 2.0
......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35921/4/src/mainboard/google/glado…
File src/mainboard/google/glados/romstage.c:
https://review.coreboot.org/c/coreboot/+/35921/4/src/mainboard/google/glado…
PS4, Line 35: const FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd;
need consistent spacing around '*' (ctx:WxV)
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35921 )
Change subject: mb/google/glados: port to FSP 2.0
......................................................................
Uploaded patch set 4.
(3 comments)
https://review.coreboot.org/c/coreboot/+/35921/3//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/35921/3//COMMIT_MSG@18
PS3, Line 18: - set FSP board type to "mobile"
> this is being set to BOARD_TYPE_ULT_ULX at SoC level, why do we want to override? what are consequen […]
overlooked that, thanks!
https://review.coreboot.org/c/coreboot/+/35921/3//COMMIT_MSG@19
PS3, Line 19: - add FSP parameter DmiVc1 (see TODO)
> this doesn't seem necessary (at least on chell), so def need better understanding on its addition gi […]
hmm, interesting. I found that vendor BIOS on supermicro boards has a option for the user to enable/disable this. enabling channel 1 (Vc1) for dmi shall improve performance of the PCH-MCH communication.... it is not required, but I wonder if we should set this as default on SKL/KBL/...?
https://review.coreboot.org/c/coreboot/+/35921/3//COMMIT_MSG@23
PS3, Line 23: - loadline values in devicetree maybe can dropped again, as Maxim is
: working on adding missing loadline values in CB:35167
> I would recommend dropping them and simply rebasing your patchset on top of that change, no reason t […]
Ack
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