coreboot-gerrit October 2019

coreboot-gerrit@coreboot.org

1 participants
1921 discussions

Change in coreboot[master]: util/cbfstool: Add optional argument ibb
by Patrick Rudolph (Code Review) 10 Oct '19

10 Oct '19

Patrick Rudolph has uploaded a new patch set (#22) to the change originally created by Philipp Deppenwiese. ( https://review.coreboot.org/c/coreboot/+/29744 ) Change subject: util/cbfstool: Add optional argument ibb ...................................................................... util/cbfstool: Add optional argument ibb * Mark files in CBFS as IBB (Initial BootBlock) * Will be used to identify the IBB by any TEE Change-Id: Idb4857c894b9ee1edc464c0a1216cdda29937bbd Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M util/cbfstool/cbfs.h M util/cbfstool/cbfs_image.c M util/cbfstool/cbfs_image.h M util/cbfstool/cbfstool.c 4 files changed, 39 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/29744/22 -- To view, visit https://review.coreboot.org/c/coreboot/+/29744 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb4857c894b9ee1edc464c0a1216cdda29937bbd Gerrit-Change-Number: 29744 Gerrit-PatchSet: 22 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Amol N Sukerkar <amol.n.sukerkar(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kai Michaelis <kai.michaelis(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mainboard/lenovo/t410: Add new port
by Arthur Heymans (Code Review) 10 Oct '19

10 Oct '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/11791 ) Change subject: mainboard/lenovo/t410: Add new port ...................................................................... Patch Set 25: Code-Review+2 LGTM -- To view, visit https://review.coreboot.org/c/coreboot/+/11791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9d872e643dd242e925bfb46d18076e6ad100995 Gerrit-Change-Number: 11791 Gerrit-PatchSet: 25 Gerrit-Owner: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eloy Degen Gerrit-CC: Matt Parnell <mparnell(a)gmail.com> Gerrit-CC: Okashi Odayakana <okashi(a)okashi.me> Gerrit-CC: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Comment-Date: Thu, 10 Oct 2019 07:28:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard/lenovo/t410: Add new port
by Patrick Rudolph (Code Review) 10 Oct '19

10 Oct '19

Patrick Rudolph has uploaded a new patch set (#25) to the change originally created by Nicolas Reinecke. ( https://review.coreboot.org/c/coreboot/+/11791 ) Change subject: mainboard/lenovo/t410: Add new port ...................................................................... mainboard/lenovo/t410: Add new port The port is based on the x201 / t410s. 2537-vg5 / i5, no discrete gpu Tested and working: * Native raminit * Native gfxinit * Booting Seabios 1.12.1 * Booting from EHCI * Running GNU/Linux 5.0.0 * No errors in dmesg * EHCI debug on the devices left side, bottom-right * Keyboard * Fn keys (Mute, Volume, Mic) * Touchpad * TPM * Wifi * Sound * USB * Ethernet * S3 resume * VBOOT Testing in progress. Untested: * VGA * Displayport * Docking station Bugs: * AC adapter can't be read from ACPI Details for flashing externally: 1. Disconnect all power 2. Connect the external flasher 3. Connect the power cord (This fixes internal power control) 4. Remove the power cord Change-Id: Id9d872e643dd242e925bfb46d18076e6ad100995 Signed-off-by: Nicolas Reinecke <nr(a)das-labor.org> Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/lenovo/t410.md A Documentation/mainboard/lenovo/t410_chip_location.jpg A src/mainboard/lenovo/t410/Kconfig A src/mainboard/lenovo/t410/Kconfig.name A src/mainboard/lenovo/t410/Makefile.inc A src/mainboard/lenovo/t410/acpi/dock.asl A src/mainboard/lenovo/t410/acpi/ec.asl A src/mainboard/lenovo/t410/acpi/gpe.asl A src/mainboard/lenovo/t410/acpi/platform.asl A src/mainboard/lenovo/t410/acpi/superio.asl A src/mainboard/lenovo/t410/acpi_tables.c A src/mainboard/lenovo/t410/board_info.txt A src/mainboard/lenovo/t410/cmos.default A src/mainboard/lenovo/t410/cmos.layout A src/mainboard/lenovo/t410/data.vbt A src/mainboard/lenovo/t410/devicetree.cb A src/mainboard/lenovo/t410/dock.c A src/mainboard/lenovo/t410/dock.h A src/mainboard/lenovo/t410/dsdt.asl A src/mainboard/lenovo/t410/gma-mainboard.ads A src/mainboard/lenovo/t410/gpio.c A src/mainboard/lenovo/t410/hda_verb.c A src/mainboard/lenovo/t410/mainboard.c A src/mainboard/lenovo/t410/romstage.c A src/mainboard/lenovo/t410/smihandler.c A src/mainboard/lenovo/t410/thermal.h A src/mainboard/lenovo/t410/vboot-rwa.fmd 28 files changed, 1,459 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/11791/25 -- To view, visit https://review.coreboot.org/c/coreboot/+/11791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9d872e643dd242e925bfb46d18076e6ad100995 Gerrit-Change-Number: 11791 Gerrit-PatchSet: 25 Gerrit-Owner: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eloy Degen Gerrit-CC: Matt Parnell <mparnell(a)gmail.com> Gerrit-CC: Okashi Odayakana <okashi(a)okashi.me> Gerrit-CC: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mainboard/lenovo/t410: Add new port
by Patrick Rudolph (Code Review) 10 Oct '19

10 Oct '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/11791 ) Change subject: mainboard/lenovo/t410: Add new port ...................................................................... Patch Set 23: (8 comments) https://review.coreboot.org/c/coreboot/+/11791/21/src/mainboard/lenovo/t410… File src/mainboard/lenovo/t410/acpi/ec.asl: https://review.coreboot.org/c/coreboot/+/11791/21/src/mainboard/lenovo/t410… PS21, Line 19: Scope(\_SB.PCI0.LPCB.EC) : { : } > Maybe put the dock. […] removed https://review.coreboot.org/c/coreboot/+/11791/23/src/mainboard/lenovo/t410… File src/mainboard/lenovo/t410/devicetree.cb: https://review.coreboot.org/c/coreboot/+/11791/23/src/mainboard/lenovo/t410… PS23, Line 120: > remove tab and fix alignment of things below. Done https://review.coreboot.org/c/coreboot/+/11791/21/src/mainboard/lenovo/t410… File src/mainboard/lenovo/t410/hda_verb.c: https://review.coreboot.org/c/coreboot/+/11791/21/src/mainboard/lenovo/t410… PS21, Line 25: / > I think you can remove all of these comments Done https://review.coreboot.org/c/coreboot/+/11791/10/src/mainboard/lenovo/t410… File src/mainboard/lenovo/t410/mainboard.c: https://review.coreboot.org/c/coreboot/+/11791/10/src/mainboard/lenovo/t410… PS10, Line 99: outl(0, pmbase + SMI_EN); > write_pmbase32(SMI_EN, 0); […] removed https://review.coreboot.org/c/coreboot/+/11791/10/src/mainboard/lenovo/t410… PS10, Line 108: /* If we're resuming from suspend, blink suspend LED */ > Copied as is from x201/mainboard.c. I personally have no idea what the original author meant here. removed https://review.coreboot.org/c/coreboot/+/11791/21/src/mainboard/lenovo/t410… File src/mainboard/lenovo/t410/romstage.c: https://review.coreboot.org/c/coreboot/+/11791/21/src/mainboard/lenovo/t410… PS21, Line 54: : pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); : pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); : pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, 0x1c1681); : pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, (0x68 & ~3) | 0x00040001); > Any idea if you need those during romstage as there is ramstage code to set those up based on dt (co […] 15e0 is used by pmh7_* functions. Sounds like a good plan to move that to romstage, like done on bd82x6x https://review.coreboot.org/c/coreboot/+/11791/23/src/mainboard/lenovo/t410… File src/mainboard/lenovo/t410/romstage.c: https://review.coreboot.org/c/coreboot/+/11791/23/src/mainboard/lenovo/t410… PS23, Line 28: : /* Seems copied from Lenovo Thinkpad x201, might be wrong */ > fix? Done https://review.coreboot.org/c/coreboot/+/11791/18/src/mainboard/lenovo/t410… File src/mainboard/lenovo/t410/thermal.h: https://review.coreboot.org/c/coreboot/+/11791/18/src/mainboard/lenovo/t410… PS18, Line 4: * Copyright (C) 2008-2009 coresystems GmbH : * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. : * Copyright (C) 2014 Vladimir Serbinenko : * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> : * Copyright (C) 2017 James Ye <jye836(a)gmail.com> : * > makes little sense here? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/11791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9d872e643dd242e925bfb46d18076e6ad100995 Gerrit-Change-Number: 11791 Gerrit-PatchSet: 23 Gerrit-Owner: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eloy Degen Gerrit-CC: Matt Parnell <mparnell(a)gmail.com> Gerrit-CC: Okashi Odayakana <okashi(a)okashi.me> Gerrit-CC: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Comment-Date: Thu, 10 Oct 2019 06:41:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard/lenovo/t410: Add new port
by Patrick Rudolph (Code Review) 10 Oct '19

10 Oct '19

Patrick Rudolph has uploaded a new patch set (#24) to the change originally created by Nicolas Reinecke. ( https://review.coreboot.org/c/coreboot/+/11791 ) Change subject: mainboard/lenovo/t410: Add new port ...................................................................... mainboard/lenovo/t410: Add new port The port is based on the x201 / t410s. 2537-vg5 / i5, no discrete gpu Tested and working: * Native raminit * Native gfxinit * Booting Seabios 1.12.1 * Booting from EHCI * Running GNU/Linux 5.0.0 * No errors in dmesg * EHCI debug on the devices left side, bottom-right * Keyboard * Fn keys (Mute, Volume, Mic) * Touchpad * TPM * Wifi * Sound * USB * Ethernet * S3 resume * VBOOT Testing in progress. Untested: * VGA * Displayport Bugs: * AC adapter can't be read from ACPI Details for flashing externally: 1. Disconnect all power 2. Connect the external flasher 3. Connect the power cord (This fixes internal power control) 4. Remove the power cord Change-Id: Id9d872e643dd242e925bfb46d18076e6ad100995 Signed-off-by: Nicolas Reinecke <nr(a)das-labor.org> Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/lenovo/t410.md A Documentation/mainboard/lenovo/t410_chip_location.jpg A src/mainboard/lenovo/t410/Kconfig A src/mainboard/lenovo/t410/Kconfig.name A src/mainboard/lenovo/t410/Makefile.inc A src/mainboard/lenovo/t410/acpi/dock.asl A src/mainboard/lenovo/t410/acpi/ec.asl A src/mainboard/lenovo/t410/acpi/gpe.asl A src/mainboard/lenovo/t410/acpi/platform.asl A src/mainboard/lenovo/t410/acpi/superio.asl A src/mainboard/lenovo/t410/acpi_tables.c A src/mainboard/lenovo/t410/board_info.txt A src/mainboard/lenovo/t410/cmos.default A src/mainboard/lenovo/t410/cmos.layout A src/mainboard/lenovo/t410/data.vbt A src/mainboard/lenovo/t410/devicetree.cb A src/mainboard/lenovo/t410/dock.c A src/mainboard/lenovo/t410/dock.h A src/mainboard/lenovo/t410/dsdt.asl A src/mainboard/lenovo/t410/gma-mainboard.ads A src/mainboard/lenovo/t410/gpio.c A src/mainboard/lenovo/t410/hda_verb.c A src/mainboard/lenovo/t410/mainboard.c A src/mainboard/lenovo/t410/romstage.c A src/mainboard/lenovo/t410/smi.h A src/mainboard/lenovo/t410/smihandler.c A src/mainboard/lenovo/t410/thermal.h A src/mainboard/lenovo/t410/vboot-rwa.fmd 29 files changed, 1,505 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/11791/24 -- To view, visit https://review.coreboot.org/c/coreboot/+/11791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9d872e643dd242e925bfb46d18076e6ad100995 Gerrit-Change-Number: 11791 Gerrit-PatchSet: 24 Gerrit-Owner: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eloy Degen Gerrit-CC: Matt Parnell <mparnell(a)gmail.com> Gerrit-CC: Okashi Odayakana <okashi(a)okashi.me> Gerrit-CC: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/cannonlake: Remove DMA support for PTT
by Subrata Banik (Code Review) 10 Oct '19

10 Oct '19

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27176 ) Change subject: soc/intel/cannonlake: Remove DMA support for PTT ...................................................................... Patch Set 3: > Patch Set 3: > > I am running into an issue on Whiskey Lake-U where the calculated reserved memory in coreboot is different from the calculated reserved memory in the FSP by 0x1000. Reverting this change fixes this miscalculation. Is it possible that this needs to be reinstated on some systems? we do have WHL-U based several designs and don't see such issue, are you sure you are seeing issue because of this CL. its been a year old now ? adding @bora owning WHL-U based design and @Lean Sheng for CFL based design -- To view, visit https://review.coreboot.org/c/coreboot/+/27176 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11993cef77fd5e879eedabc1ed344f91f8257c90 Gerrit-Change-Number: 27176 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jeremy Soller <jeremy(a)system76.com> Gerrit-Comment-Date: Thu, 10 Oct 2019 04:42:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/hatch/variants/helios: Modify touchscreen power on sequence
by Shelley Chen (Code Review) 10 Oct '19

10 Oct '19

Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35907 ) Change subject: mb/google/hatch/variants/helios: Modify touchscreen power on sequence ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/35907/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/35907/2//COMMIT_MSG@13 PS2, Line 13: TEST I assume that you tested touchscreen functionality is ok with this CL? -- To view, visit https://review.coreboot.org/c/coreboot/+/35907 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86c920ff1d5c0b510adde8a37f60003072d5f4e7 Gerrit-Change-Number: 35907 Gerrit-PatchSet: 2 Gerrit-Owner: YenLu Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Assignee: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: YenLu Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Thu, 10 Oct 2019 01:36:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: HACK sc7180: bootblock/verstage/romstage need to zero bss HACK
by Julius Werner (Code Review) 10 Oct '19

10 Oct '19

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35896 ) Change subject: HACK sc7180: bootblock/verstage/romstage need to zero bss HACK ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/c/coreboot/+/35896/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/35896/1//COMMIT_MSG@8 PS1, Line 8: > The verstage.c change allowed code to reach romstage. Yeah, this is super weird. I can see plenty of reasons why BSS clearing for the bootblock might be broken, but for the verstage I have no idea how that might happen. I have a hunch that it might be a toolchain problem at this point, although I'm not really sure what toolchain would cause such a bad result. When you run cbfstool print -v on the images it will show you more detailed output for stages, including the size in memory (the number behind the slash). Do you see a big difference between the same stages for the working and the broken images there? Like something might have dropped the BSS section from the ELF? -- To view, visit https://review.coreboot.org/c/coreboot/+/35896 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iafe0ccfb776b8150f547cb691e082c206f80a8fc Gerrit-Change-Number: 35896 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Thu, 10 Oct 2019 00:05:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Aaron Durbin <adurbin(a)chromium.org> Comment-In-Reply-To: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/qualcomm: Remove default ops to generate bootblock.bin
by Arthur Heymans (Code Review) 09 Oct '19

09 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35899 ) Change subject: soc/qualcomm: Remove default ops to generate bootblock.bin ...................................................................... soc/qualcomm: Remove default ops to generate bootblock.bin This is done by default in the main Makefile.inc. TEST: With BUILD_TIMELESS=1 the resulting binary is identical before and after the change. Change-Id: Ie85e023df1f1c2b0f115e4f92719a511f60019c3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/sdm845/Makefile.inc 2 files changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/35899/1 diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc index 0ebfcae..f21ea54 100644 --- a/src/soc/qualcomm/qcs405/Makefile.inc +++ b/src/soc/qualcomm/qcs405/Makefile.inc @@ -52,8 +52,4 @@ CPPFLAGS_common += -Isrc/soc/qualcomm/qcs405/include -$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin - @printf "Generating: $(subst $(obj)/,,$(@))\n" - cp $(objcbfs)/bootblock.raw.bin $(objcbfs)/bootblock.bin - endif diff --git a/src/soc/qualcomm/sdm845/Makefile.inc b/src/soc/qualcomm/sdm845/Makefile.inc index c20be14..fd39bd9 100644 --- a/src/soc/qualcomm/sdm845/Makefile.inc +++ b/src/soc/qualcomm/sdm845/Makefile.inc @@ -48,8 +48,4 @@ CPPFLAGS_common += -Isrc/soc/qualcomm/sdm845/include CPPFLAGS_common += -Isrc/soc/qualcomm/common/include -$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin - @printf "Generating: $(subst $(obj)/,,$(@))\n" - cp $(objcbfs)/bootblock.raw.bin $(objcbfs)/bootblock.bin - endif -- To view, visit https://review.coreboot.org/c/coreboot/+/35899 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie85e023df1f1c2b0f115e4f92719a511f60019c3 Gerrit-Change-Number: 35899 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8183: Change argument type of mt_set_emi
by Yu-Ping Wu (Code Review) 09 Oct '19

09 Oct '19

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35846 ) Change subject: soc/mediatek/mt8183: Change argument type of mt_set_emi ...................................................................... soc/mediatek/mt8183: Change argument type of mt_set_emi Since struct dramc_param has been defined, we can pass the struct directly from mt_mem_init(). BUG=b:139099592 BRANCH=none TEST=emerge-kukui coreboot Change-Id: If7333fb579eff76dd9d1c2bf6fdfe7eccb22050f Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/emi.h M src/soc/mediatek/mt8183/memory.c 3 files changed, 11 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/35846/1 diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index 3b5b2a7..52baeb1 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -14,10 +14,11 @@ */ #include <device/mmio.h> -#include <soc/emi.h> -#include <soc/infracfg.h> +#include <soc/dramc_param.h> #include <soc/dramc_pi_api.h> #include <soc/dramc_register.h> +#include <soc/emi.h> +#include <soc/infracfg.h> static const u8 freq_shuffle[DRAM_DFS_SHUFFLE_MAX] = { [DRAM_DFS_SHUFFLE_1] = LP4X_DDR3200, @@ -355,7 +356,7 @@ dramc_runtime_config(); } -void mt_set_emi(const struct sdram_params *freq_params) +void mt_set_emi(const struct dramc_param *dparam) { const u8 *freq_tbl; const int shuffle = DRAM_DFS_SHUFFLE_1; @@ -368,7 +369,7 @@ freq_tbl = freq_shuffle; current_freqsel = freq_tbl[shuffle]; - params = &freq_params[shuffle]; + params = &dparam->freq_params[shuffle]; init_dram(params, current_freqsel); do_calib(params, current_freqsel); diff --git a/src/soc/mediatek/mt8183/include/soc/emi.h b/src/soc/mediatek/mt8183/include/soc/emi.h index 7957753..d9b2d94 100644 --- a/src/soc/mediatek/mt8183/include/soc/emi.h +++ b/src/soc/mediatek/mt8183/include/soc/emi.h @@ -70,6 +70,8 @@ u16 delay_cell_unit; }; +struct dramc_param; + enum { LP4X_DDR1600, LP4X_DDR2400, @@ -84,6 +86,6 @@ size_t sdram_size(void); const struct sdram_params *get_sdram_config(void); void enable_emi_dcm(void); -void mt_set_emi(const struct sdram_params *freq_params); +void mt_set_emi(const struct dramc_param *dparam); #endif /* SOC_MEDIATEK_MT8183_EMI_H */ diff --git a/src/soc/mediatek/mt8183/memory.c b/src/soc/mediatek/mt8183/memory.c index 038424c..9d53dc8 100644 --- a/src/soc/mediatek/mt8183/memory.c +++ b/src/soc/mediatek/mt8183/memory.c @@ -125,7 +125,6 @@ void mt_mem_init(struct dramc_param_ops *dparam_ops) { struct dramc_param *dparam = &dparam_ops->param; - struct sdram_params *freq_params = dparam->freq_params; u16 config = 0; if (CONFIG(MT8183_DRAM_EMCP)) @@ -136,7 +135,7 @@ if (dram_run_fast_calibration(dparam, config) == 0) { printk(BIOS_INFO, "DRAM calibraion params loaded from flash\n"); - mt_set_emi(freq_params); + mt_set_emi(dparam); mt_mem_test(); return; } @@ -161,7 +160,7 @@ "falling back to load default sdram param\n", err); /* Init params from sdram configs and run partial calibration */ - init_sdram_params(freq_params, get_sdram_config()); - mt_set_emi(freq_params); + init_sdram_params(dparam->freq_params, get_sdram_config()); + mt_set_emi(dparam); mt_mem_test(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/35846 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7333fb579eff76dd9d1c2bf6fdfe7eccb22050f Gerrit-Change-Number: 35846 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit October 2019