coreboot-gerrit October 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: [WIP]soc/intel/cannonlake: Allow coreboot to reserve stack for fsp
by Bora Guvendik (Code Review) 09 Oct '19

09 Oct '19

Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33746 Change subject: [WIP]soc/intel/cannonlake: Allow coreboot to reserve stack for fsp ...................................................................... [WIP]soc/intel/cannonlake: Allow coreboot to reserve stack for fsp Change-Id: I0778ee21cb4f66b8ec884b77788c05a73c609be6 Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/soc/intel/cannonlake/Kconfig 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/33746/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index dac3522..8e362c1 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -62,6 +62,7 @@ select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select FSP_M_XIP + select FSP_USES_CB_STACK select GENERIC_GPIO_LIB select HAVE_FSP_GOP select INTEL_DESCRIPTOR_MODE_CAPABLE @@ -120,6 +121,7 @@ config DCACHE_BSP_STACK_SIZE hex + default 0x20000 if FSP_USES_CB_STACK default 0x4000 help The amount of anticipated stack usage in CAR by bootblock and -- To view, visit https://review.coreboot.org/c/coreboot/+/33746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0778ee21cb4f66b8ec884b77788c05a73c609be6 Gerrit-Change-Number: 33746 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cannonlake: Remove DMA support for PTT
by Jeremy Soller (Code Review) 09 Oct '19

09 Oct '19

Jeremy Soller has created a revert of this change. ( https://review.coreboot.org/c/coreboot/+/27176 ) Change subject: soc/intel/cannonlake: Remove DMA support for PTT ...................................................................... -- To view, visit https://review.coreboot.org/c/coreboot/+/27176 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11993cef77fd5e879eedabc1ed344f91f8257c90 Gerrit-Change-Number: 27176 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jeremy Soller <jackpot51(a)gmail.com> Gerrit-MessageType: revert

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Change in coreboot[master]: util/inteltool: set num of cores depends on CPUID
by Maxim Polyakov (Code Review) 09 Oct '19

09 Oct '19

Hello Stefan Reinauer, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35918 to look at the new patch set (#2). Change subject: util/inteltool: set num of cores depends on CPUID ...................................................................... util/inteltool: set num of cores depends on CPUID The cores number for some processors exceeds the limit of 8 cores, which is hardcoded in cpu.c. For example, the Intel Cooper Lake CPU contains up to 56 cores in the package. The patch adds a new variable to the cpu_t structure - max_core_limit contains the maximum number of cores for the corresponding processor. Change-Id: I4a4408f286f245d1d109adf98f430ad7a6b1b2fa Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M util/inteltool/cpu.c 1 file changed, 16 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/35918/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/35918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a4408f286f245d1d109adf98f430ad7a6b1b2fa Gerrit-Change-Number: 35918 Gerrit-PatchSet: 2 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8183: Add the shared 'dramc_param' module
by Hung-Te Lin (Code Review) 09 Oct '19

09 Oct '19

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35775 ) Change subject: soc/mediatek/mt8183: Add the shared 'dramc_param' module ...................................................................... Patch Set 12: (1 comment) https://review.coreboot.org/c/coreboot/+/35775/12//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/35775/12//COMMIT_MSG@14 PS12, Line 14: BRANCH=none nit: BRANCH=kukui -- To view, visit https://review.coreboot.org/c/coreboot/+/35775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4cfd634da1855a76706aab0b050197251e2ed4dd Gerrit-Change-Number: 35775 Gerrit-PatchSet: 12 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 09 Oct 2019 13:29:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/hatch/variants/helios: Modify DPTF parameters
by Paul Menzel (Code Review) 09 Oct '19

09 Oct '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35794 ) Change subject: mb/google/hatch/variants/helios: Modify DPTF parameters ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/35794/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/35794/2//COMMIT_MSG@9 PS2, Line 9: Modify DPTF parameters and TDP PL1 values to 15 1. Please add a dot/period at the end of sentences. 2. If possible, please split the commit up? 3. Where did you get these values from? 4. What tests pass now, which did not before? -- To view, visit https://review.coreboot.org/c/coreboot/+/35794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e5c079856a167b1c2ef52e446d055404e565858 Gerrit-Change-Number: 35794 Gerrit-PatchSet: 2 Gerrit-Owner: YenLu Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Rajat Jain <rajatja(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YenLu Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Anson Tseng <anson.tseng(a)intel.corp-partner.google.com> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Comment-Date: Wed, 09 Oct 2019 12:08:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/hatch/variants/helios: Modify DPTF parameters
by Sumeet R Pawnikar (Code Review) 09 Oct '19

09 Oct '19

Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35794 ) Change subject: mb/google/hatch/variants/helios: Modify DPTF parameters ...................................................................... Patch Set 2: (2 comments) > Patch Set 2: > > > Patch Set 2: > > > > (1 comment) > > Set 0 means set null . It will make passive setting disabled by filled value 0 . Does that mean, you do not want any kind of passive throttling (PL1) when CPU, TSR1 and TSR2 goes above passive temperature threshold limits ? https://review.coreboot.org/c/coreboot/+/35794/2/src/mainboard/google/hatch… File src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl: https://review.coreboot.org/c/coreboot/+/35794/2/src/mainboard/google/hatch… PS2, Line 65: Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ any reason for this removing this ? https://review.coreboot.org/c/coreboot/+/35794/2/src/mainboard/google/hatch… PS2, Line 93: /* CPU Throttle Effect on CPU */ : Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 60, 0, 0, 0, 0 }, Do you still need this ? Above passive threshold for CPU set to 0. -- To view, visit https://review.coreboot.org/c/coreboot/+/35794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e5c079856a167b1c2ef52e446d055404e565858 Gerrit-Change-Number: 35794 Gerrit-PatchSet: 2 Gerrit-Owner: YenLu Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Rajat Jain <rajatja(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YenLu Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Anson Tseng <anson.tseng(a)intel.corp-partner.google.com> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Comment-Date: Wed, 09 Oct 2019 11:58:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: SMBIOS: (Type 17) Add High Bandwidth Memory device type value
by HAOUAS Elyes (Code Review) 09 Oct '19

09 Oct '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35893 ) Change subject: SMBIOS: (Type 17) Add High Bandwidth Memory device type value ...................................................................... SMBIOS: (Type 17) Add High Bandwidth Memory device type value Change-Id: Ia174e09bffdadeed4a18d443f75e2386d756e9bf Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/include/smbios.h 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/35893/1 diff --git a/src/include/smbios.h b/src/include/smbios.h index 4247183..d7eff00 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -170,6 +170,8 @@ MEMORY_TYPE_LPDDR3 = 0x1d, MEMORY_TYPE_LPDDR4 = 0x1e, MEMORY_TYPE_LOGICAL_NON_VOLATILE_DEVICE = 0x1f, + MEMORY_TYPE_HBM = 0x20, + MEMORY_TYPE_HBM2 = 0x21, } smbios_memory_type; typedef enum { -- To view, visit https://review.coreboot.org/c/coreboot/+/35893 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia174e09bffdadeed4a18d443f75e2386d756e9bf Gerrit-Change-Number: 35893 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: SMBIOS: (Type 9) Add PCI Express Gen 4 values
by HAOUAS Elyes (Code Review) 09 Oct '19

09 Oct '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35890 ) Change subject: SMBIOS: (Type 9) Add PCI Express Gen 4 values ...................................................................... SMBIOS: (Type 9) Add PCI Express Gen 4 values Change-Id: I616a435d80715bee6f7530d7318319556a7580e7 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/include/smbios.h 1 file changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/35890/1 diff --git a/src/include/smbios.h b/src/include/smbios.h index 0bba0a7..4247183 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -550,7 +550,13 @@ SlotTypePciExpressGen3X2 = 0xB3, SlotTypePciExpressGen3X4 = 0xB4, SlotTypePciExpressGen3X8 = 0xB5, - SlotTypePciExpressGen3X16 = 0xB6 + SlotTypePciExpressGen3X16 = 0xB6, + SlotTypePciExpressGen4 = 0xB8, + SlotTypePciExpressGen4x1 = 0xB9, + SlotTypePciExpressGen4x2 = 0xBA, + SlotTypePciExpressGen4x4 = 0xBB, + SlotTypePciExpressGen4x8 = 0xBC, + SlotTypePciExpressGen4x16 = 0xBD }; /* System Slots - Slot Data Bus Width. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35890 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I616a435d80715bee6f7530d7318319556a7580e7 Gerrit-Change-Number: 35890 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/hatch/variants/helios: Modify touchscreen power on sequence
by YenLu Chen (Code Review) 09 Oct '19

09 Oct '19

YenLu Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35907 ) Change subject: mb/google/hatch/variants/helios: Modify touchscreen power on sequence ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/35907 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86c920ff1d5c0b510adde8a37f60003072d5f4e7 Gerrit-Change-Number: 35907 Gerrit-PatchSet: 2 Gerrit-Owner: YenLu Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: YenLu Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Wed, 09 Oct 2019 10:21:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/hatch/variants/helios: Modify touchscreen power on sequence
by YenLu Chen (Code Review) 09 Oct '19

09 Oct '19

Hello Philip Chen, Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35907 to look at the new patch set (#2). Change subject: mb/google/hatch/variants/helios: Modify touchscreen power on sequence ...................................................................... mb/google/hatch/variants/helios: Modify touchscreen power on sequence Modify GPP_D9 delay time and add GPP_C4 setting. BUG=b:142368161 BRANCH=Master TEST=emerge-hatch coreboot chromeos-bootimage Signed-off-by: YenLu Chen <kane_chen(a)pegatron.corp-partner.google.com> Change-Id: I86c920ff1d5c0b510adde8a37f60003072d5f4e7 --- M src/mainboard/google/hatch/variants/helios/overridetree.cb 1 file changed, 6 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/35907/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/35907 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86c920ff1d5c0b510adde8a37f60003072d5f4e7 Gerrit-Change-Number: 35907 Gerrit-PatchSet: 2 Gerrit-Owner: YenLu Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: YenLu Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit October 2019